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Reservation_station.h

Last change on this file was 136, checked in by rosiere, 15 years ago
1) Add new algo in ifetch queue 2) Add Cancel bit 3) new config
Property svn:keywords set to `Id`
File size: 10.1 KB

Rev	Line
[55]	1	#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_read_unit_read_unit_reservation_station_Reservation_station_h
	2	#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_read_unit_read_unit_reservation_station_Reservation_station_h
	3
	4	/*
	5	* $Id: Reservation_station.h 136 2009-10-20 18:52:15Z rosiere $
	6	*
[76]	7	* [ Description ]
[55]	8	*
	9	*/
	10
	11	#ifdef SYSTEMC
	12	#include "systemc.h"
	13	#endif
	14
	15	#include <iostream>
	16	#include "Common/include/ToString.h"
	17	#include "Common/include/Debug.h"
	18
[69]	19	#ifndef SYSTEMC_VHDL_COMPATIBILITY
[56]	20	#include "Behavioural/Generic/Queue_Control/include/Queue_Control.h"
[69]	21	#endif
[55]	22	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Parameters.h"
[82]	23	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Types.h"
[55]	24	#ifdef STATISTICS
[75]	25	#include "Behavioural/include/Stat.h"
[55]	26	#endif
	27	#include "Behavioural/include/Component.h"
	28	#ifdef VHDL
	29	#include "Behavioural/include/Vhdl.h"
	30	#endif
[82]	31	#include "Behavioural/include/Usage.h"
[55]	32
	33	namespace morpheo {
	34	namespace behavioural {
	35	namespace core {
	36	namespace multi_execute_loop {
	37	namespace execute_loop {
	38	namespace multi_read_unit {
	39	namespace read_unit {
	40	namespace reservation_station {
	41
	42	class Reservation_station
	43	#if SYSTEMC
	44	: public sc_module
	45	#endif
	46	{
[76]	47	// -----[ fields ]----------------------------------------------------
[55]	48	// Parameters
[82]	49	protected : const std::string _name;
[55]	50	protected : const Parameters * _param;
[82]	51	private : const Tusage_t _usage;
[55]	52
	53	#ifdef STATISTICS
[75]	54	public : Stat * _stat;
[55]	55	#endif
	56
	57	public : Component * _component;
	58	private : Interfaces * _interfaces;
	59
	60	#ifdef SYSTEMC
[76]	61	// ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	62	// Interface
	63	public : SC_CLOCK * in_CLOCK ;
	64	public : SC_IN (Tcontrol_t) * in_NRESET ;
	65
[76]	66	// ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~
[69]	67	public : SC_IN (Tcontrol_t ) * in_INSERT_VAL ;
	68	public : SC_OUT(Tcontrol_t ) * out_INSERT_ACK ;
	69	public : SC_IN (Tcontext_t ) * in_INSERT_CONTEXT_ID ;
	70	public : SC_IN (Tcontext_t ) * in_INSERT_FRONT_END_ID ;
	71	public : SC_IN (Tcontext_t ) * in_INSERT_OOO_ENGINE_ID ;
	72	public : SC_IN (Tpacket_t ) * in_INSERT_ROB_ID ;
	73	public : SC_IN (Toperation_t ) * in_INSERT_OPERATION ;
	74	public : SC_IN (Ttype_t ) * in_INSERT_TYPE ;
[136]	75	public : SC_IN (Tcontrol_t ) * in_INSERT_CANCEL ;
[76]	76	public : SC_IN (Tlsq_ptr_t ) * in_INSERT_STORE_QUEUE_PTR_WRITE;
[122]	77	public : SC_IN (Tlsq_ptr_t ) * in_INSERT_STORE_QUEUE_PTR_READ ;
	78	public : SC_IN (Tcontrol_t ) * in_INSERT_STORE_QUEUE_EMPTY ;
[76]	79	public : SC_IN (Tlsq_ptr_t ) * in_INSERT_LOAD_QUEUE_PTR_WRITE ;
[69]	80	public : SC_IN (Tcontrol_t ) * in_INSERT_HAS_IMMEDIAT ;
	81	public : SC_IN (Tgeneral_data_t ) * in_INSERT_IMMEDIAT ;
	82	//public : SC_IN (Tcontrol_t ) * in_INSERT_READ_RA ;
	83	public : SC_IN (Tgeneral_address_t) * in_INSERT_NUM_REG_RA ;
	84	public : SC_IN (Tcontrol_t ) * in_INSERT_DATA_RA_VAL ;
	85	public : SC_IN (Tgeneral_data_t ) * in_INSERT_DATA_RA ;
	86	//public : SC_IN (Tcontrol_t ) * in_INSERT_READ_RB ;
	87	public : SC_IN (Tgeneral_address_t) * in_INSERT_NUM_REG_RB ;
	88	public : SC_IN (Tcontrol_t ) * in_INSERT_DATA_RB_VAL ;
	89	public : SC_IN (Tgeneral_data_t ) * in_INSERT_DATA_RB ;
	90	//public : SC_IN (Tcontrol_t ) * in_INSERT_READ_RC ;
	91	public : SC_IN (Tspecial_address_t) * in_INSERT_NUM_REG_RC ;
	92	public : SC_IN (Tcontrol_t ) * in_INSERT_DATA_RC_VAL ;
	93	public : SC_IN (Tspecial_data_t ) * in_INSERT_DATA_RC ;
	94	public : SC_IN (Tcontrol_t ) * in_INSERT_WRITE_RD ;
	95	public : SC_IN (Tgeneral_address_t) * in_INSERT_NUM_REG_RD ;
	96	public : SC_IN (Tcontrol_t ) * in_INSERT_WRITE_RE ;
	97	public : SC_IN (Tspecial_address_t) * in_INSERT_NUM_REG_RE ;
[55]	98
[76]	99	// ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~
[69]	100	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_VAL ;
	101	public : SC_IN (Tcontrol_t ) ** in_RETIRE_ACK ;
	102	public : SC_OUT(Tcontext_t ) ** out_RETIRE_CONTEXT_ID ;
	103	public : SC_OUT(Tcontext_t ) ** out_RETIRE_FRONT_END_ID ;
	104	public : SC_OUT(Tcontext_t ) ** out_RETIRE_OOO_ENGINE_ID ;
	105	public : SC_OUT(Tpacket_t ) ** out_RETIRE_ROB_ID ;
	106	public : SC_OUT(Toperation_t ) ** out_RETIRE_OPERATION ;
	107	public : SC_OUT(Ttype_t ) ** out_RETIRE_TYPE ;
[136]	108	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_CANCEL ;
[76]	109	public : SC_OUT(Tlsq_ptr_t ) ** out_RETIRE_STORE_QUEUE_PTR_WRITE;
[122]	110	public : SC_OUT(Tlsq_ptr_t ) ** out_RETIRE_STORE_QUEUE_PTR_READ ;
	111	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_STORE_QUEUE_EMPTY ;
[76]	112	public : SC_OUT(Tlsq_ptr_t ) ** out_RETIRE_LOAD_QUEUE_PTR_WRITE ;
[69]	113	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_HAS_IMMEDIAT ;
	114	public : SC_OUT(Tgeneral_data_t ) ** out_RETIRE_IMMEDIAT ;
	115	public : SC_OUT(Tgeneral_data_t ) ** out_RETIRE_DATA_RA ;
	116	public : SC_OUT(Tgeneral_data_t ) ** out_RETIRE_DATA_RB ;
	117	public : SC_OUT(Tspecial_data_t ) ** out_RETIRE_DATA_RC ;
	118	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_WRITE_RD ;
	119	public : SC_OUT(Tgeneral_address_t) ** out_RETIRE_NUM_REG_RD ;
	120	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_WRITE_RE ;
	121	public : SC_OUT(Tspecial_address_t) ** out_RETIRE_NUM_REG_RE ;
[55]	122
[76]	123	// ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	124
[69]	125	public : SC_IN (Tcontrol_t ) ** in_GPR_WRITE_VAL ; // val and ack
	126	public : SC_IN (Tcontext_t ) ** in_GPR_WRITE_OOO_ENGINE_ID;
	127	public : SC_IN (Tgeneral_address_t) ** in_GPR_WRITE_NUM_REG ;
	128	public : SC_IN (Tgeneral_data_t ) ** in_GPR_WRITE_DATA ;
[55]	129
[76]	130	// ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	131
[69]	132	public : SC_IN (Tcontrol_t ) ** in_SPR_WRITE_VAL ; // val and ack
	133	public : SC_IN (Tcontext_t ) ** in_SPR_WRITE_OOO_ENGINE_ID;
	134	public : SC_IN (Tspecial_address_t) ** in_SPR_WRITE_NUM_REG ;
	135	public : SC_IN (Tspecial_data_t ) ** in_SPR_WRITE_DATA ;
[55]	136
[76]	137	// ~~~~~[ Interface "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	138
[69]	139	public : SC_IN (Tcontext_t ) ** in_BYPASS_WRITE_OOO_ENGINE_ID ;
	140	public : SC_IN (Tcontrol_t ) ** in_BYPASS_WRITE_GPR_VAL ;
	141	public : SC_IN (Tgeneral_address_t) ** in_BYPASS_WRITE_GPR_NUM_REG ; // RD
	142	public : SC_IN (Tgeneral_data_t ) ** in_BYPASS_WRITE_GPR_DATA ;
	143	public : SC_IN (Tcontrol_t ) ** in_BYPASS_WRITE_SPR_VAL ;
	144	public : SC_IN (Tspecial_address_t) ** in_BYPASS_WRITE_SPR_NUM_REG ; // RE
	145	public : SC_IN (Tspecial_data_t ) ** in_BYPASS_WRITE_SPR_DATA ;
[55]	146
[76]	147	// ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	148
[69]	149	public : SC_IN (Tcontrol_t ) ** in_BYPASS_MEMORY_VAL ;
	150	public : SC_IN (Tcontext_t ) ** in_BYPASS_MEMORY_OOO_ENGINE_ID;
	151	public : SC_IN (Tgeneral_address_t) ** in_BYPASS_MEMORY_NUM_REG ;
	152	public : SC_IN (Tgeneral_data_t ) ** in_BYPASS_MEMORY_DATA ;
[55]	153
	154
[76]	155	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	156
[76]	157	// ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	158
[76]	159	// ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[69]	160	#ifdef SYSTEMC_VHDL_COMPATIBILITY
	161	protected : bool * _queue_valid;
	162	protected : uint32_t internal_INSERT_SLOT;
	163	#else
[56]	164	protected : morpheo::behavioural::generic::queue_control::Queue_Control * _queue_control;
[69]	165	#endif
[55]	166	protected : Treservation_station_entry_t * _queue;
	167
[69]	168	protected : Tcontrol_t internal_INSERT_ACK;
	169	protected : Tcontrol_t * internal_RETIRE_VAL;
	170	protected : uint32_t * internal_RETIRE_SLOT;
[55]	171	#endif
	172
[76]	173	// -----[ methods ]---------------------------------------------------
[55]	174
	175	#ifdef SYSTEMC
	176	SC_HAS_PROCESS (Reservation_station);
	177	#endif
	178	public : Reservation_station (
	179	#ifdef SYSTEMC
[75]	180	sc_module_name name,
[55]	181	#else
[75]	182	string name,
[55]	183	#endif
	184	#ifdef STATISTICS
[75]	185	morpheo::behavioural::Parameters_Statistics * param_statistics,
[55]	186	#endif
[82]	187	Parameters * param,
	188	morpheo::behavioural::Tusage_t usage );
	189
[55]	190	public : ~Reservation_station (void);
	191
	192	#ifdef SYSTEMC
	193	private : void allocation (void);
	194	private : void deallocation (void);
	195
	196	public : void transition (void);
	197	public : void genMoore (void);
	198	#endif
[75]	199
[55]	200	#ifdef STATISTICS
[75]	201	public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics);
[55]	202	#endif
	203
	204	#if VHDL
	205	public : void vhdl (void);
	206	private : void vhdl_declaration (Vhdl * & vhdl);
	207	private : void vhdl_body (Vhdl * & vhdl);
	208	#endif
	209
[75]	210	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
[69]	211	private : void end_cycle (void);
[75]	212	#endif
[55]	213	};
	214
	215	}; // end namespace reservation_station
	216	}; // end namespace read_unit
	217	}; // end namespace multi_read_unit
	218	}; // end namespace execute_loop
	219	}; // end namespace multi_execute_loop
	220	}; // end namespace core
	221
	222	}; // end namespace behavioural
	223	}; // end namespace morpheo
	224
	225	#endif

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h

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