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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h @ 122

Last change on this file since 122 was 122, checked in by rosiere, 15 years ago
Modif for performance : 1) Load Store Unit : store send request to valid exeception 2) Commit_unit : retire can bypass store 3) Commit_unit : add stat to manage store instruction 4) Load Store Unit and Load Store Pointer Manager : add store_queue_ptr_read 5) Fix lot of bug
Property svn:keywords set to `Id`
File size: 10.0 KB

Rev	Line
[55]	1	#ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_read_unit_read_unit_reservation_station_Reservation_station_h
	2	#define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_read_unit_read_unit_reservation_station_Reservation_station_h
	3
	4	/*
	5	* $Id: Reservation_station.h 122 2009-06-03 08:15:51Z rosiere $
	6	*
[76]	7	* [ Description ]
[55]	8	*
	9	*/
	10
	11	#ifdef SYSTEMC
	12	#include "systemc.h"
	13	#endif
	14
	15	#include <iostream>
	16	#include "Common/include/ToString.h"
	17	#include "Common/include/Debug.h"
	18
[69]	19	#ifndef SYSTEMC_VHDL_COMPATIBILITY
[56]	20	#include "Behavioural/Generic/Queue_Control/include/Queue_Control.h"
[69]	21	#endif
[55]	22	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Parameters.h"
[82]	23	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Types.h"
[55]	24	#ifdef STATISTICS
[75]	25	#include "Behavioural/include/Stat.h"
[55]	26	#endif
	27	#include "Behavioural/include/Component.h"
	28	#ifdef VHDL
	29	#include "Behavioural/include/Vhdl.h"
	30	#endif
[82]	31	#include "Behavioural/include/Usage.h"
[55]	32
	33	namespace morpheo {
	34	namespace behavioural {
	35	namespace core {
	36	namespace multi_execute_loop {
	37	namespace execute_loop {
	38	namespace multi_read_unit {
	39	namespace read_unit {
	40	namespace reservation_station {
	41
	42	class Reservation_station
	43	#if SYSTEMC
	44	: public sc_module
	45	#endif
	46	{
[76]	47	// -----[ fields ]----------------------------------------------------
[55]	48	// Parameters
[82]	49	protected : const std::string _name;
[55]	50	protected : const Parameters * _param;
[82]	51	private : const Tusage_t _usage;
[55]	52
	53	#ifdef STATISTICS
[75]	54	public : Stat * _stat;
[55]	55	#endif
	56
	57	public : Component * _component;
	58	private : Interfaces * _interfaces;
	59
	60	#ifdef SYSTEMC
[76]	61	// ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	62	// Interface
	63	public : SC_CLOCK * in_CLOCK ;
	64	public : SC_IN (Tcontrol_t) * in_NRESET ;
	65
[76]	66	// ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~
[69]	67	public : SC_IN (Tcontrol_t ) * in_INSERT_VAL ;
	68	public : SC_OUT(Tcontrol_t ) * out_INSERT_ACK ;
	69	public : SC_IN (Tcontext_t ) * in_INSERT_CONTEXT_ID ;
	70	public : SC_IN (Tcontext_t ) * in_INSERT_FRONT_END_ID ;
	71	public : SC_IN (Tcontext_t ) * in_INSERT_OOO_ENGINE_ID ;
	72	public : SC_IN (Tpacket_t ) * in_INSERT_ROB_ID ;
	73	public : SC_IN (Toperation_t ) * in_INSERT_OPERATION ;
	74	public : SC_IN (Ttype_t ) * in_INSERT_TYPE ;
[76]	75	public : SC_IN (Tlsq_ptr_t ) * in_INSERT_STORE_QUEUE_PTR_WRITE;
[122]	76	public : SC_IN (Tlsq_ptr_t ) * in_INSERT_STORE_QUEUE_PTR_READ ;
	77	public : SC_IN (Tcontrol_t ) * in_INSERT_STORE_QUEUE_EMPTY ;
[76]	78	public : SC_IN (Tlsq_ptr_t ) * in_INSERT_LOAD_QUEUE_PTR_WRITE ;
[69]	79	public : SC_IN (Tcontrol_t ) * in_INSERT_HAS_IMMEDIAT ;
	80	public : SC_IN (Tgeneral_data_t ) * in_INSERT_IMMEDIAT ;
	81	//public : SC_IN (Tcontrol_t ) * in_INSERT_READ_RA ;
	82	public : SC_IN (Tgeneral_address_t) * in_INSERT_NUM_REG_RA ;
	83	public : SC_IN (Tcontrol_t ) * in_INSERT_DATA_RA_VAL ;
	84	public : SC_IN (Tgeneral_data_t ) * in_INSERT_DATA_RA ;
	85	//public : SC_IN (Tcontrol_t ) * in_INSERT_READ_RB ;
	86	public : SC_IN (Tgeneral_address_t) * in_INSERT_NUM_REG_RB ;
	87	public : SC_IN (Tcontrol_t ) * in_INSERT_DATA_RB_VAL ;
	88	public : SC_IN (Tgeneral_data_t ) * in_INSERT_DATA_RB ;
	89	//public : SC_IN (Tcontrol_t ) * in_INSERT_READ_RC ;
	90	public : SC_IN (Tspecial_address_t) * in_INSERT_NUM_REG_RC ;
	91	public : SC_IN (Tcontrol_t ) * in_INSERT_DATA_RC_VAL ;
	92	public : SC_IN (Tspecial_data_t ) * in_INSERT_DATA_RC ;
	93	public : SC_IN (Tcontrol_t ) * in_INSERT_WRITE_RD ;
	94	public : SC_IN (Tgeneral_address_t) * in_INSERT_NUM_REG_RD ;
	95	public : SC_IN (Tcontrol_t ) * in_INSERT_WRITE_RE ;
	96	public : SC_IN (Tspecial_address_t) * in_INSERT_NUM_REG_RE ;
[55]	97
[76]	98	// ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~
[69]	99	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_VAL ;
	100	public : SC_IN (Tcontrol_t ) ** in_RETIRE_ACK ;
	101	public : SC_OUT(Tcontext_t ) ** out_RETIRE_CONTEXT_ID ;
	102	public : SC_OUT(Tcontext_t ) ** out_RETIRE_FRONT_END_ID ;
	103	public : SC_OUT(Tcontext_t ) ** out_RETIRE_OOO_ENGINE_ID ;
	104	public : SC_OUT(Tpacket_t ) ** out_RETIRE_ROB_ID ;
	105	public : SC_OUT(Toperation_t ) ** out_RETIRE_OPERATION ;
	106	public : SC_OUT(Ttype_t ) ** out_RETIRE_TYPE ;
[76]	107	public : SC_OUT(Tlsq_ptr_t ) ** out_RETIRE_STORE_QUEUE_PTR_WRITE;
[122]	108	public : SC_OUT(Tlsq_ptr_t ) ** out_RETIRE_STORE_QUEUE_PTR_READ ;
	109	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_STORE_QUEUE_EMPTY ;
[76]	110	public : SC_OUT(Tlsq_ptr_t ) ** out_RETIRE_LOAD_QUEUE_PTR_WRITE ;
[69]	111	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_HAS_IMMEDIAT ;
	112	public : SC_OUT(Tgeneral_data_t ) ** out_RETIRE_IMMEDIAT ;
	113	public : SC_OUT(Tgeneral_data_t ) ** out_RETIRE_DATA_RA ;
	114	public : SC_OUT(Tgeneral_data_t ) ** out_RETIRE_DATA_RB ;
	115	public : SC_OUT(Tspecial_data_t ) ** out_RETIRE_DATA_RC ;
	116	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_WRITE_RD ;
	117	public : SC_OUT(Tgeneral_address_t) ** out_RETIRE_NUM_REG_RD ;
	118	public : SC_OUT(Tcontrol_t ) ** out_RETIRE_WRITE_RE ;
	119	public : SC_OUT(Tspecial_address_t) ** out_RETIRE_NUM_REG_RE ;
[55]	120
[76]	121	// ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	122
[69]	123	public : SC_IN (Tcontrol_t ) ** in_GPR_WRITE_VAL ; // val and ack
	124	public : SC_IN (Tcontext_t ) ** in_GPR_WRITE_OOO_ENGINE_ID;
	125	public : SC_IN (Tgeneral_address_t) ** in_GPR_WRITE_NUM_REG ;
	126	public : SC_IN (Tgeneral_data_t ) ** in_GPR_WRITE_DATA ;
[55]	127
[76]	128	// ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	129
[69]	130	public : SC_IN (Tcontrol_t ) ** in_SPR_WRITE_VAL ; // val and ack
	131	public : SC_IN (Tcontext_t ) ** in_SPR_WRITE_OOO_ENGINE_ID;
	132	public : SC_IN (Tspecial_address_t) ** in_SPR_WRITE_NUM_REG ;
	133	public : SC_IN (Tspecial_data_t ) ** in_SPR_WRITE_DATA ;
[55]	134
[76]	135	// ~~~~~[ Interface "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	136
[69]	137	public : SC_IN (Tcontext_t ) ** in_BYPASS_WRITE_OOO_ENGINE_ID ;
	138	public : SC_IN (Tcontrol_t ) ** in_BYPASS_WRITE_GPR_VAL ;
	139	public : SC_IN (Tgeneral_address_t) ** in_BYPASS_WRITE_GPR_NUM_REG ; // RD
	140	public : SC_IN (Tgeneral_data_t ) ** in_BYPASS_WRITE_GPR_DATA ;
	141	public : SC_IN (Tcontrol_t ) ** in_BYPASS_WRITE_SPR_VAL ;
	142	public : SC_IN (Tspecial_address_t) ** in_BYPASS_WRITE_SPR_NUM_REG ; // RE
	143	public : SC_IN (Tspecial_data_t ) ** in_BYPASS_WRITE_SPR_DATA ;
[55]	144
[76]	145	// ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	146
[69]	147	public : SC_IN (Tcontrol_t ) ** in_BYPASS_MEMORY_VAL ;
	148	public : SC_IN (Tcontext_t ) ** in_BYPASS_MEMORY_OOO_ENGINE_ID;
	149	public : SC_IN (Tgeneral_address_t) ** in_BYPASS_MEMORY_NUM_REG ;
	150	public : SC_IN (Tgeneral_data_t ) ** in_BYPASS_MEMORY_DATA ;
[55]	151
	152
[76]	153	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	154
[76]	155	// ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	156
[76]	157	// ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[69]	158	#ifdef SYSTEMC_VHDL_COMPATIBILITY
	159	protected : bool * _queue_valid;
	160	protected : uint32_t internal_INSERT_SLOT;
	161	#else
[56]	162	protected : morpheo::behavioural::generic::queue_control::Queue_Control * _queue_control;
[69]	163	#endif
[55]	164	protected : Treservation_station_entry_t * _queue;
	165
[69]	166	protected : Tcontrol_t internal_INSERT_ACK;
	167	protected : Tcontrol_t * internal_RETIRE_VAL;
	168	protected : uint32_t * internal_RETIRE_SLOT;
[55]	169	#endif
	170
[76]	171	// -----[ methods ]---------------------------------------------------
[55]	172
	173	#ifdef SYSTEMC
	174	SC_HAS_PROCESS (Reservation_station);
	175	#endif
	176	public : Reservation_station (
	177	#ifdef SYSTEMC
[75]	178	sc_module_name name,
[55]	179	#else
[75]	180	string name,
[55]	181	#endif
	182	#ifdef STATISTICS
[75]	183	morpheo::behavioural::Parameters_Statistics * param_statistics,
[55]	184	#endif
[82]	185	Parameters * param,
	186	morpheo::behavioural::Tusage_t usage );
	187
[55]	188	public : ~Reservation_station (void);
	189
	190	#ifdef SYSTEMC
	191	private : void allocation (void);
	192	private : void deallocation (void);
	193
	194	public : void transition (void);
	195	public : void genMoore (void);
	196	#endif
[75]	197
[55]	198	#ifdef STATISTICS
[75]	199	public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics);
[55]	200	#endif
	201
	202	#if VHDL
	203	public : void vhdl (void);
	204	private : void vhdl_declaration (Vhdl * & vhdl);
	205	private : void vhdl_body (Vhdl * & vhdl);
	206	#endif
	207
[75]	208	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
[69]	209	private : void end_cycle (void);
[75]	210	#endif
[55]	211	};
	212
	213	}; // end namespace reservation_station
	214	}; // end namespace read_unit
	215	}; // end namespace multi_read_unit
	216	}; // end namespace execute_loop
	217	}; // end namespace multi_execute_loop
	218	}; // end namespace core
	219
	220	}; // end namespace behavioural
	221	}; // end namespace morpheo
	222
	223	#endif

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