[55] | 1 | #ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_read_unit_read_unit_reservation_station_Reservation_station_h |
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| 2 | #define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_read_unit_read_unit_reservation_station_Reservation_station_h |
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| 3 | |
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| 4 | /* |
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| 5 | * $Id: Reservation_station.h 136 2009-10-20 18:52:15Z rosiere $ |
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| 6 | * |
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[76] | 7 | * [ Description ] |
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[55] | 8 | * |
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| 9 | */ |
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| 10 | |
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| 11 | #ifdef SYSTEMC |
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| 12 | #include "systemc.h" |
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| 13 | #endif |
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| 14 | |
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| 15 | #include <iostream> |
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| 16 | #include "Common/include/ToString.h" |
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| 17 | #include "Common/include/Debug.h" |
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| 18 | |
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[69] | 19 | #ifndef SYSTEMC_VHDL_COMPATIBILITY |
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[56] | 20 | #include "Behavioural/Generic/Queue_Control/include/Queue_Control.h" |
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[69] | 21 | #endif |
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[55] | 22 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Parameters.h" |
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[82] | 23 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Types.h" |
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[55] | 24 | #ifdef STATISTICS |
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[75] | 25 | #include "Behavioural/include/Stat.h" |
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[55] | 26 | #endif |
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| 27 | #include "Behavioural/include/Component.h" |
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| 28 | #ifdef VHDL |
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| 29 | #include "Behavioural/include/Vhdl.h" |
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| 30 | #endif |
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[82] | 31 | #include "Behavioural/include/Usage.h" |
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[55] | 32 | |
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| 33 | namespace morpheo { |
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| 34 | namespace behavioural { |
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| 35 | namespace core { |
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| 36 | namespace multi_execute_loop { |
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| 37 | namespace execute_loop { |
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| 38 | namespace multi_read_unit { |
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| 39 | namespace read_unit { |
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| 40 | namespace reservation_station { |
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| 41 | |
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| 42 | class Reservation_station |
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| 43 | #if SYSTEMC |
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| 44 | : public sc_module |
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| 45 | #endif |
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| 46 | { |
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[76] | 47 | // -----[ fields ]---------------------------------------------------- |
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[55] | 48 | // Parameters |
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[82] | 49 | protected : const std::string _name; |
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[55] | 50 | protected : const Parameters * _param; |
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[82] | 51 | private : const Tusage_t _usage; |
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[55] | 52 | |
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| 53 | #ifdef STATISTICS |
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[75] | 54 | public : Stat * _stat; |
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[55] | 55 | #endif |
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| 56 | |
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| 57 | public : Component * _component; |
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| 58 | private : Interfaces * _interfaces; |
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| 59 | |
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| 60 | #ifdef SYSTEMC |
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[76] | 61 | // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[55] | 62 | // Interface |
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| 63 | public : SC_CLOCK * in_CLOCK ; |
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| 64 | public : SC_IN (Tcontrol_t) * in_NRESET ; |
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| 65 | |
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[76] | 66 | // ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~ |
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[69] | 67 | public : SC_IN (Tcontrol_t ) * in_INSERT_VAL ; |
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| 68 | public : SC_OUT(Tcontrol_t ) * out_INSERT_ACK ; |
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| 69 | public : SC_IN (Tcontext_t ) * in_INSERT_CONTEXT_ID ; |
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| 70 | public : SC_IN (Tcontext_t ) * in_INSERT_FRONT_END_ID ; |
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| 71 | public : SC_IN (Tcontext_t ) * in_INSERT_OOO_ENGINE_ID ; |
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| 72 | public : SC_IN (Tpacket_t ) * in_INSERT_ROB_ID ; |
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| 73 | public : SC_IN (Toperation_t ) * in_INSERT_OPERATION ; |
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| 74 | public : SC_IN (Ttype_t ) * in_INSERT_TYPE ; |
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[136] | 75 | public : SC_IN (Tcontrol_t ) * in_INSERT_CANCEL ; |
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[76] | 76 | public : SC_IN (Tlsq_ptr_t ) * in_INSERT_STORE_QUEUE_PTR_WRITE; |
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[122] | 77 | public : SC_IN (Tlsq_ptr_t ) * in_INSERT_STORE_QUEUE_PTR_READ ; |
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| 78 | public : SC_IN (Tcontrol_t ) * in_INSERT_STORE_QUEUE_EMPTY ; |
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[76] | 79 | public : SC_IN (Tlsq_ptr_t ) * in_INSERT_LOAD_QUEUE_PTR_WRITE ; |
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[69] | 80 | public : SC_IN (Tcontrol_t ) * in_INSERT_HAS_IMMEDIAT ; |
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| 81 | public : SC_IN (Tgeneral_data_t ) * in_INSERT_IMMEDIAT ; |
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| 82 | //public : SC_IN (Tcontrol_t ) * in_INSERT_READ_RA ; |
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| 83 | public : SC_IN (Tgeneral_address_t) * in_INSERT_NUM_REG_RA ; |
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| 84 | public : SC_IN (Tcontrol_t ) * in_INSERT_DATA_RA_VAL ; |
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| 85 | public : SC_IN (Tgeneral_data_t ) * in_INSERT_DATA_RA ; |
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| 86 | //public : SC_IN (Tcontrol_t ) * in_INSERT_READ_RB ; |
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| 87 | public : SC_IN (Tgeneral_address_t) * in_INSERT_NUM_REG_RB ; |
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| 88 | public : SC_IN (Tcontrol_t ) * in_INSERT_DATA_RB_VAL ; |
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| 89 | public : SC_IN (Tgeneral_data_t ) * in_INSERT_DATA_RB ; |
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| 90 | //public : SC_IN (Tcontrol_t ) * in_INSERT_READ_RC ; |
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| 91 | public : SC_IN (Tspecial_address_t) * in_INSERT_NUM_REG_RC ; |
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| 92 | public : SC_IN (Tcontrol_t ) * in_INSERT_DATA_RC_VAL ; |
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| 93 | public : SC_IN (Tspecial_data_t ) * in_INSERT_DATA_RC ; |
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| 94 | public : SC_IN (Tcontrol_t ) * in_INSERT_WRITE_RD ; |
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| 95 | public : SC_IN (Tgeneral_address_t) * in_INSERT_NUM_REG_RD ; |
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| 96 | public : SC_IN (Tcontrol_t ) * in_INSERT_WRITE_RE ; |
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| 97 | public : SC_IN (Tspecial_address_t) * in_INSERT_NUM_REG_RE ; |
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[55] | 98 | |
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[76] | 99 | // ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~ |
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[69] | 100 | public : SC_OUT(Tcontrol_t ) ** out_RETIRE_VAL ; |
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| 101 | public : SC_IN (Tcontrol_t ) ** in_RETIRE_ACK ; |
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| 102 | public : SC_OUT(Tcontext_t ) ** out_RETIRE_CONTEXT_ID ; |
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| 103 | public : SC_OUT(Tcontext_t ) ** out_RETIRE_FRONT_END_ID ; |
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| 104 | public : SC_OUT(Tcontext_t ) ** out_RETIRE_OOO_ENGINE_ID ; |
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| 105 | public : SC_OUT(Tpacket_t ) ** out_RETIRE_ROB_ID ; |
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| 106 | public : SC_OUT(Toperation_t ) ** out_RETIRE_OPERATION ; |
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| 107 | public : SC_OUT(Ttype_t ) ** out_RETIRE_TYPE ; |
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[136] | 108 | public : SC_OUT(Tcontrol_t ) ** out_RETIRE_CANCEL ; |
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[76] | 109 | public : SC_OUT(Tlsq_ptr_t ) ** out_RETIRE_STORE_QUEUE_PTR_WRITE; |
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[122] | 110 | public : SC_OUT(Tlsq_ptr_t ) ** out_RETIRE_STORE_QUEUE_PTR_READ ; |
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| 111 | public : SC_OUT(Tcontrol_t ) ** out_RETIRE_STORE_QUEUE_EMPTY ; |
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[76] | 112 | public : SC_OUT(Tlsq_ptr_t ) ** out_RETIRE_LOAD_QUEUE_PTR_WRITE ; |
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[69] | 113 | public : SC_OUT(Tcontrol_t ) ** out_RETIRE_HAS_IMMEDIAT ; |
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| 114 | public : SC_OUT(Tgeneral_data_t ) ** out_RETIRE_IMMEDIAT ; |
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| 115 | public : SC_OUT(Tgeneral_data_t ) ** out_RETIRE_DATA_RA ; |
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| 116 | public : SC_OUT(Tgeneral_data_t ) ** out_RETIRE_DATA_RB ; |
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| 117 | public : SC_OUT(Tspecial_data_t ) ** out_RETIRE_DATA_RC ; |
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| 118 | public : SC_OUT(Tcontrol_t ) ** out_RETIRE_WRITE_RD ; |
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| 119 | public : SC_OUT(Tgeneral_address_t) ** out_RETIRE_NUM_REG_RD ; |
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| 120 | public : SC_OUT(Tcontrol_t ) ** out_RETIRE_WRITE_RE ; |
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| 121 | public : SC_OUT(Tspecial_address_t) ** out_RETIRE_NUM_REG_RE ; |
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[55] | 122 | |
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[76] | 123 | // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[55] | 124 | |
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[69] | 125 | public : SC_IN (Tcontrol_t ) ** in_GPR_WRITE_VAL ; // val and ack |
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| 126 | public : SC_IN (Tcontext_t ) ** in_GPR_WRITE_OOO_ENGINE_ID; |
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| 127 | public : SC_IN (Tgeneral_address_t) ** in_GPR_WRITE_NUM_REG ; |
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| 128 | public : SC_IN (Tgeneral_data_t ) ** in_GPR_WRITE_DATA ; |
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[55] | 129 | |
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[76] | 130 | // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[55] | 131 | |
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[69] | 132 | public : SC_IN (Tcontrol_t ) ** in_SPR_WRITE_VAL ; // val and ack |
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| 133 | public : SC_IN (Tcontext_t ) ** in_SPR_WRITE_OOO_ENGINE_ID; |
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| 134 | public : SC_IN (Tspecial_address_t) ** in_SPR_WRITE_NUM_REG ; |
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| 135 | public : SC_IN (Tspecial_data_t ) ** in_SPR_WRITE_DATA ; |
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[55] | 136 | |
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[76] | 137 | // ~~~~~[ Interface "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[55] | 138 | |
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[69] | 139 | public : SC_IN (Tcontext_t ) ** in_BYPASS_WRITE_OOO_ENGINE_ID ; |
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| 140 | public : SC_IN (Tcontrol_t ) ** in_BYPASS_WRITE_GPR_VAL ; |
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| 141 | public : SC_IN (Tgeneral_address_t) ** in_BYPASS_WRITE_GPR_NUM_REG ; // RD |
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| 142 | public : SC_IN (Tgeneral_data_t ) ** in_BYPASS_WRITE_GPR_DATA ; |
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| 143 | public : SC_IN (Tcontrol_t ) ** in_BYPASS_WRITE_SPR_VAL ; |
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| 144 | public : SC_IN (Tspecial_address_t) ** in_BYPASS_WRITE_SPR_NUM_REG ; // RE |
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| 145 | public : SC_IN (Tspecial_data_t ) ** in_BYPASS_WRITE_SPR_DATA ; |
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[55] | 146 | |
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[76] | 147 | // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[55] | 148 | |
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[69] | 149 | public : SC_IN (Tcontrol_t ) ** in_BYPASS_MEMORY_VAL ; |
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| 150 | public : SC_IN (Tcontext_t ) ** in_BYPASS_MEMORY_OOO_ENGINE_ID; |
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| 151 | public : SC_IN (Tgeneral_address_t) ** in_BYPASS_MEMORY_NUM_REG ; |
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| 152 | public : SC_IN (Tgeneral_data_t ) ** in_BYPASS_MEMORY_DATA ; |
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[55] | 153 | |
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| 154 | |
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[76] | 155 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[55] | 156 | |
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[76] | 157 | // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[55] | 158 | |
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[76] | 159 | // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[69] | 160 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 161 | protected : bool * _queue_valid; |
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| 162 | protected : uint32_t internal_INSERT_SLOT; |
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| 163 | #else |
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[56] | 164 | protected : morpheo::behavioural::generic::queue_control::Queue_Control * _queue_control; |
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[69] | 165 | #endif |
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[55] | 166 | protected : Treservation_station_entry_t * _queue; |
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| 167 | |
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[69] | 168 | protected : Tcontrol_t internal_INSERT_ACK; |
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| 169 | protected : Tcontrol_t * internal_RETIRE_VAL; |
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| 170 | protected : uint32_t * internal_RETIRE_SLOT; |
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[55] | 171 | #endif |
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| 172 | |
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[76] | 173 | // -----[ methods ]--------------------------------------------------- |
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[55] | 174 | |
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| 175 | #ifdef SYSTEMC |
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| 176 | SC_HAS_PROCESS (Reservation_station); |
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| 177 | #endif |
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| 178 | public : Reservation_station ( |
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| 179 | #ifdef SYSTEMC |
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[75] | 180 | sc_module_name name, |
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[55] | 181 | #else |
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[75] | 182 | string name, |
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[55] | 183 | #endif |
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| 184 | #ifdef STATISTICS |
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[75] | 185 | morpheo::behavioural::Parameters_Statistics * param_statistics, |
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[55] | 186 | #endif |
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[82] | 187 | Parameters * param, |
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| 188 | morpheo::behavioural::Tusage_t usage ); |
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| 189 | |
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[55] | 190 | public : ~Reservation_station (void); |
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| 191 | |
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| 192 | #ifdef SYSTEMC |
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| 193 | private : void allocation (void); |
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| 194 | private : void deallocation (void); |
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| 195 | |
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| 196 | public : void transition (void); |
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| 197 | public : void genMoore (void); |
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| 198 | #endif |
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[75] | 199 | |
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[55] | 200 | #ifdef STATISTICS |
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[75] | 201 | public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics); |
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[55] | 202 | #endif |
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| 203 | |
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| 204 | #if VHDL |
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| 205 | public : void vhdl (void); |
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| 206 | private : void vhdl_declaration (Vhdl * & vhdl); |
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| 207 | private : void vhdl_body (Vhdl * & vhdl); |
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| 208 | #endif |
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| 209 | |
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[75] | 210 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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[69] | 211 | private : void end_cycle (void); |
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[75] | 212 | #endif |
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[55] | 213 | }; |
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| 214 | |
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| 215 | }; // end namespace reservation_station |
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| 216 | }; // end namespace read_unit |
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| 217 | }; // end namespace multi_read_unit |
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| 218 | }; // end namespace execute_loop |
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| 219 | }; // end namespace multi_execute_loop |
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| 220 | }; // end namespace core |
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| 221 | |
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| 222 | }; // end namespace behavioural |
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| 223 | }; // end namespace morpheo |
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| 224 | |
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| 225 | #endif |
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