1 | #ifdef SYSTEMC |
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2 | //#if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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3 | /* |
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4 | * $Id: Reservation_station_transition.cpp 136 2009-10-20 18:52:15Z rosiere $ |
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5 | * |
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6 | * [ Description ] |
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7 | * |
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8 | */ |
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9 | |
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10 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/Reservation_station/include/Reservation_station.h" |
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11 | |
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12 | namespace morpheo { |
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13 | namespace behavioural { |
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14 | namespace core { |
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15 | namespace multi_execute_loop { |
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16 | namespace execute_loop { |
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17 | namespace multi_read_unit { |
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18 | namespace read_unit { |
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19 | namespace reservation_station { |
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20 | |
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21 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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22 | #define dump_queue() \ |
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23 | do \ |
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24 | { \ |
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25 | log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \ |
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26 | for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \ |
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27 | if (_queue_valid [it_dump]) \ |
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28 | log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d %.1d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \ |
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29 | it_dump, \ |
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30 | _queue[it_dump]._context_id , \ |
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31 | _queue[it_dump]._front_end_id , \ |
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32 | _queue[it_dump]._ooo_engine_id , \ |
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33 | _queue[it_dump]._rob_id , \ |
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34 | _queue[it_dump]._type , \ |
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35 | _queue[it_dump]._operation , \ |
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36 | _queue[it_dump]._cancel , \ |
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37 | _queue[it_dump]._store_queue_ptr_write, \ |
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38 | _queue[it_dump]._store_queue_ptr_read , \ |
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39 | _queue[it_dump]._store_queue_empty , \ |
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40 | _queue[it_dump]._load_queue_ptr_write , \ |
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41 | _queue[it_dump]._has_immediat , \ |
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42 | _queue[it_dump]._immediat , \ |
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43 | _queue[it_dump]._num_reg_ra , \ |
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44 | _queue[it_dump]._data_ra_val , \ |
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45 | _queue[it_dump]._data_ra , \ |
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46 | _queue[it_dump]._num_reg_rb , \ |
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47 | _queue[it_dump]._data_rb_val , \ |
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48 | _queue[it_dump]._data_rb , \ |
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49 | _queue[it_dump]._num_reg_rc , \ |
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50 | _queue[it_dump]._data_rc_val , \ |
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51 | _queue[it_dump]._data_rc , \ |
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52 | _queue[it_dump]._write_rd , \ |
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53 | _queue[it_dump]._num_reg_rd , \ |
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54 | _queue[it_dump]._write_re , \ |
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55 | _queue[it_dump]._num_reg_re , \ |
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56 | toString(_queue[it_dump]._type).c_str()); \ |
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57 | } while (0) |
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58 | #else |
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59 | #define dump_queue() \ |
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60 | do \ |
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61 | { \ |
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62 | log_printf(TRACE,Reservation_station,FUNCTION," * Dump Reservation Station"); \ |
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63 | log_printf(TRACE,Reservation_station,FUNCTION," * nb_elt : %d",_queue_control->nb_elt()); \ |
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64 | for (uint32_t it_dump=0;it_dump<_param->_size_queue; it_dump++) \ |
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65 | if (it_dump < _queue_control->nb_elt()) \ |
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66 | log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d] %.2d %.2d %.2d %.4d, %.2d %.3d %.1d, %.2d %.2d %.1d %.2d, %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.8x, %.4d %.1d %.2x, %.1d %.4d, %.1d %.4d (%s)", \ |
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67 | (*_queue_control)[it_dump], \ |
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68 | _queue[(*_queue_control)[it_dump]]._context_id , \ |
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69 | _queue[(*_queue_control)[it_dump]]._front_end_id , \ |
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70 | _queue[(*_queue_control)[it_dump]]._ooo_engine_id , \ |
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71 | _queue[(*_queue_control)[it_dump]]._rob_id , \ |
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72 | _queue[(*_queue_control)[it_dump]]._type , \ |
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73 | _queue[(*_queue_control)[it_dump]]._operation , \ |
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74 | _queue[(*_queue_control)[it_dump]]._cancel , \ |
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75 | _queue[(*_queue_control)[it_dump]]._store_queue_ptr_write, \ |
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76 | _queue[(*_queue_control)[it_dump]]._store_queue_ptr_read , \ |
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77 | _queue[(*_queue_control)[it_dump]]._store_queue_empty , \ |
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78 | _queue[(*_queue_control)[it_dump]]._load_queue_ptr_write , \ |
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79 | _queue[(*_queue_control)[it_dump]]._has_immediat , \ |
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80 | _queue[(*_queue_control)[it_dump]]._immediat , \ |
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81 | _queue[(*_queue_control)[it_dump]]._num_reg_ra , \ |
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82 | _queue[(*_queue_control)[it_dump]]._data_ra_val , \ |
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83 | _queue[(*_queue_control)[it_dump]]._data_ra , \ |
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84 | _queue[(*_queue_control)[it_dump]]._num_reg_rb , \ |
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85 | _queue[(*_queue_control)[it_dump]]._data_rb_val , \ |
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86 | _queue[(*_queue_control)[it_dump]]._data_rb , \ |
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87 | _queue[(*_queue_control)[it_dump]]._num_reg_rc , \ |
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88 | _queue[(*_queue_control)[it_dump]]._data_rc_val , \ |
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89 | _queue[(*_queue_control)[it_dump]]._data_rc , \ |
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90 | _queue[(*_queue_control)[it_dump]]._write_rd , \ |
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91 | _queue[(*_queue_control)[it_dump]]._num_reg_rd , \ |
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92 | _queue[(*_queue_control)[it_dump]]._write_re , \ |
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93 | _queue[(*_queue_control)[it_dump]]._num_reg_re , \ |
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94 | toString(_queue[(*_queue_control)[it_dump]]._type).c_str()); \ |
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95 | else \ |
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96 | log_printf(TRACE,Reservation_station,FUNCTION," * [%.4d]", \ |
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97 | (*_queue_control)[it_dump]); \ |
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98 | } while (0) |
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99 | #endif |
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100 | |
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101 | #undef FUNCTION |
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102 | #define FUNCTION "Reservation_station::transition" |
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103 | void Reservation_station::transition (void) |
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104 | { |
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105 | log_begin(Reservation_station,FUNCTION); |
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106 | log_function(Reservation_station,FUNCTION,_name.c_str()); |
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107 | |
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108 | if (PORT_READ(in_NRESET) == 0) |
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109 | { |
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110 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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111 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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112 | _queue_valid [i] = false; |
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113 | #else |
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114 | _queue_control->clear(); |
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115 | #endif |
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116 | |
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117 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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118 | { |
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119 | _queue[i]._context_id = 0; // not necessary |
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120 | _queue[i]._front_end_id = 0; // not necessary |
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121 | _queue[i]._ooo_engine_id = 0; // not necessary |
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122 | _queue[i]._rob_id = 0; // not necessary |
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123 | _queue[i]._operation = 0; // not necessary |
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124 | _queue[i]._type = 0; // not necessary |
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125 | _queue[i]._cancel = 0; // not necessary |
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126 | _queue[i]._store_queue_ptr_write = 0; // not necessary |
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127 | _queue[i]._store_queue_ptr_read = 0; // not necessary |
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128 | _queue[i]._store_queue_empty = 0; // not necessary |
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129 | _queue[i]._load_queue_ptr_write = 0; // not necessary |
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130 | _queue[i]._has_immediat = 0; // not necessary |
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131 | _queue[i]._immediat = 0; // not necessary |
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132 | // _queue[i]._read_ra = 0; // not necessary |
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133 | _queue[i]._num_reg_ra = 0; // not necessary |
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134 | _queue[i]._data_ra_val = 0; // not necessary |
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135 | _queue[i]._data_ra = 0; // not necessary |
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136 | // _queue[i]._read_rb = 0; // not necessary |
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137 | _queue[i]._num_reg_rb = 0; // not necessary |
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138 | _queue[i]._data_rb_val = 0; // not necessary |
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139 | _queue[i]._data_rb = 0; // not necessary |
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140 | // _queue[i]._read_rc = 0; // not necessary |
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141 | _queue[i]._num_reg_rc = 0; // not necessary |
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142 | _queue[i]._data_rc_val = 0; // not necessary |
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143 | _queue[i]._data_rc = 0; // not necessary |
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144 | _queue[i]._write_rd = 0; // not necessary |
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145 | _queue[i]._num_reg_rd = 0; // not necessary |
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146 | _queue[i]._write_re = 0; // not necessary |
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147 | _queue[i]._num_reg_re = 0; // not necessary |
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148 | } |
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149 | } |
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150 | else |
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151 | { |
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152 | // ***** POP from reservation station |
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153 | |
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154 | // scan in reverse order, because when we pop the queue there are an auto reorder |
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155 | //for (int32_t i=(static_cast<int32_t>(_queue_control->nb_elt()))-1;i>=0; i--) |
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156 | for (int32_t i=(static_cast<int32_t>(_param->_nb_inst_retire))-1;i>=0; i--) |
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157 | { |
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158 | if (( internal_RETIRE_VAL [i] == 1) and |
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159 | (PORT_READ(in_RETIRE_ACK [i]) == 1)) |
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160 | { |
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161 | //uint32_t index = (*_queue_control)[i]; |
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162 | |
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163 | log_printf(NONE,Reservation_station,FUNCTION," * POP [%d]",i); |
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164 | |
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165 | uint32_t index = internal_RETIRE_SLOT[i]; |
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166 | |
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167 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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168 | _queue_valid [index] = false; |
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169 | #else |
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170 | _queue_control->pop(index); |
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171 | #endif |
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172 | // cout << "========== Transition : " << endl |
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173 | // << " * i : " << i << endl |
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174 | // << " * index : " << index << endl; |
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175 | |
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176 | log_printf(NONE,Reservation_station,FUNCTION," * index : %d",index); |
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177 | } |
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178 | } |
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179 | |
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180 | // dump_queue(); |
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181 | |
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182 | // ***** Bypass |
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183 | // Note : we can take this sequence code before the PUSH in the queue, because read_queue make the bypass !!! |
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184 | |
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185 | // scan all entry |
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186 | for (uint32_t i=0; |
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187 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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188 | i<_param->_size_queue; |
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189 | #else |
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190 | i<_queue_control->nb_elt(); |
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191 | #endif |
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192 | i++) |
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193 | { |
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194 | uint32_t index; |
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195 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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196 | index = i; |
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197 | #else |
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198 | index = (*_queue_control)[i]; |
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199 | #endif |
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200 | |
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201 | // ***** bypass - gpr_write |
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202 | for (uint32_t j=0; j<_param->_nb_gpr_write; j++) |
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203 | { |
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204 | bool cmp; |
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205 | if (_param->_have_port_ooo_engine_id) |
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206 | cmp = (PORT_READ(in_GPR_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id); |
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207 | else |
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208 | cmp = true; |
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209 | |
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210 | if ((PORT_READ(in_GPR_WRITE_VAL [j]) == 1) and cmp) |
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211 | { |
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212 | if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_ra) |
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213 | { |
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214 | log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra); |
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215 | _queue[index]._data_ra_val = 1; |
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216 | _queue[index]._data_ra = PORT_READ(in_GPR_WRITE_DATA [j]); |
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217 | } |
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218 | if (PORT_READ(in_GPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rb) |
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219 | { |
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220 | log_printf(TRACE,Reservation_station,FUNCTION," -> GPR_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb); |
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221 | _queue[index]._data_rb_val = 1; |
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222 | _queue[index]._data_rb = PORT_READ(in_GPR_WRITE_DATA [j]); |
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223 | } |
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224 | } |
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225 | } |
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226 | // ***** bypass - spr_write |
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227 | for (uint32_t j=0; j<_param->_nb_spr_write; j++) |
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228 | { |
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229 | bool cmp; |
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230 | if (_param->_have_port_ooo_engine_id) |
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231 | cmp = (PORT_READ(in_SPR_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id); |
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232 | else |
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233 | cmp = true; |
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234 | |
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235 | if ((PORT_READ(in_SPR_WRITE_VAL [j]) == 1) and |
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236 | cmp and |
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237 | (PORT_READ(in_SPR_WRITE_NUM_REG [j]) == _queue[index]._num_reg_rc)) |
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238 | { |
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239 | log_printf(TRACE,Reservation_station,FUNCTION," -> SPR_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc); |
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240 | _queue[index]._data_rc_val = 1; |
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241 | _queue[index]._data_rc = PORT_READ(in_SPR_WRITE_DATA [j]); |
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242 | } |
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243 | } |
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244 | // ***** bypass - bypass_write |
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245 | for (uint32_t j=0; j<_param->_nb_bypass_write; j++) |
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246 | { |
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247 | bool cmp; |
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248 | if (_param->_have_port_ooo_engine_id) |
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249 | cmp = (PORT_READ(in_BYPASS_WRITE_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id); |
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250 | else |
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251 | cmp = true; |
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252 | |
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253 | if (cmp) |
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254 | { |
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255 | if (PORT_READ(in_BYPASS_WRITE_GPR_VAL [j]) == 1) |
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256 | { |
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257 | if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG[j]) == _queue[index]._num_reg_ra) |
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258 | { |
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259 | log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra); |
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260 | _queue[index]._data_ra_val = 1; |
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261 | _queue[index]._data_ra = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]); |
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262 | } |
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263 | if (PORT_READ(in_BYPASS_WRITE_GPR_NUM_REG [j]) == _queue[index]._num_reg_rb) |
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264 | { |
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265 | log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb); |
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266 | _queue[index]._data_rb_val = 1; |
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267 | _queue[index]._data_rb = PORT_READ(in_BYPASS_WRITE_GPR_DATA [j]); |
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268 | } |
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269 | } |
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270 | if ((PORT_READ(in_BYPASS_WRITE_SPR_VAL [j]) == 1) and |
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271 | (PORT_READ(in_BYPASS_WRITE_SPR_NUM_REG[j]) == _queue[index]._num_reg_rc)) |
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272 | { |
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273 | log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_WRITE [%d] - Hit queue[%d]-SPR_RC[%d]",i,index,_queue[index]._num_reg_rc); |
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274 | _queue[index]._data_rc_val = 1; |
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275 | _queue[index]._data_rc = PORT_READ(in_BYPASS_WRITE_SPR_DATA [j]); |
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276 | } |
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277 | } |
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278 | } |
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279 | // ***** bypass - bypass_memory |
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280 | for (uint32_t j=0; j<_param->_nb_bypass_memory; j++) |
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281 | { |
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282 | bool cmp; |
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283 | if (_param->_have_port_ooo_engine_id) |
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284 | cmp = (PORT_READ(in_BYPASS_MEMORY_OOO_ENGINE_ID [j]) == _queue[index]._ooo_engine_id); |
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285 | else |
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286 | cmp = true; |
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287 | |
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288 | if ((PORT_READ(in_BYPASS_MEMORY_VAL [j]) == 1) and cmp) |
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289 | { |
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290 | if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_ra) |
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291 | { |
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292 | log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RA[%d]",i,index,_queue[index]._num_reg_ra); |
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293 | _queue[index]._data_ra_val = 1; |
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294 | _queue[index]._data_ra = PORT_READ(in_BYPASS_MEMORY_DATA [j]); |
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295 | } |
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296 | if (PORT_READ(in_BYPASS_MEMORY_NUM_REG [j]) == _queue[index]._num_reg_rb) |
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297 | { |
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298 | log_printf(TRACE,Reservation_station,FUNCTION," -> BYPASS_MEMORY [%d] - Hit queue[%d]-GPR_RB[%d]",i,index,_queue[index]._num_reg_rb); |
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299 | _queue[index]._data_rb_val = 1; |
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300 | _queue[index]._data_rb = PORT_READ(in_BYPASS_MEMORY_DATA [j]); |
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301 | } |
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302 | } |
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303 | } |
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304 | } |
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305 | // ***** PUSH to reservation station |
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306 | if ((PORT_READ(in_INSERT_VAL) == 1) and |
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307 | ( internal_INSERT_ACK == 1)) |
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308 | { |
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309 | log_printf(TRACE,Reservation_station,FUNCTION," * PUSH"); |
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310 | |
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311 | // Write in reservation station |
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312 | uint32_t index; |
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313 | |
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314 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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315 | index = internal_INSERT_SLOT; |
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316 | _queue_valid [internal_INSERT_SLOT] = true; |
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317 | #else |
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318 | index = _queue_control->push(); |
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319 | #endif |
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320 | log_printf(TRACE,Reservation_station,FUNCTION," * index : %d",index); |
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321 | |
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322 | if (_param->_have_port_context_id) |
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323 | _queue[index]._context_id = PORT_READ(in_INSERT_CONTEXT_ID ); |
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324 | if (_param->_have_port_front_end_id) |
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325 | _queue[index]._front_end_id = PORT_READ(in_INSERT_FRONT_END_ID ); |
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326 | if (_param->_have_port_ooo_engine_id) |
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327 | _queue[index]._ooo_engine_id = PORT_READ(in_INSERT_OOO_ENGINE_ID ); |
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328 | if (_param->_have_port_rob_ptr) |
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329 | _queue[index]._rob_id = PORT_READ(in_INSERT_ROB_ID ); |
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330 | _queue[index]._operation = PORT_READ(in_INSERT_OPERATION ); |
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331 | _queue[index]._type = PORT_READ(in_INSERT_TYPE ); |
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332 | _queue[index]._cancel = PORT_READ(in_INSERT_CANCEL ); |
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333 | _queue[index]._store_queue_ptr_write = PORT_READ(in_INSERT_STORE_QUEUE_PTR_WRITE); |
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334 | _queue[index]._store_queue_ptr_read = PORT_READ(in_INSERT_STORE_QUEUE_PTR_READ ); |
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335 | _queue[index]._store_queue_empty = PORT_READ(in_INSERT_STORE_QUEUE_EMPTY ); |
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336 | if (_param->_have_port_load_queue_ptr) |
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337 | _queue[index]._load_queue_ptr_write = PORT_READ(in_INSERT_LOAD_QUEUE_PTR_WRITE ); |
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338 | _queue[index]._has_immediat = PORT_READ(in_INSERT_HAS_IMMEDIAT ); |
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339 | _queue[index]._immediat = PORT_READ(in_INSERT_IMMEDIAT ); |
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340 | // _queue[index]._read_ra = PORT_READ(in_INSERT_READ_RA ); |
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341 | _queue[index]._num_reg_ra = PORT_READ(in_INSERT_NUM_REG_RA ); |
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342 | _queue[index]._data_ra_val = PORT_READ(in_INSERT_DATA_RA_VAL ); |
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343 | _queue[index]._data_ra = PORT_READ(in_INSERT_DATA_RA ); |
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344 | // _queue[index]._read_rb = PORT_READ(in_INSERT_READ_RB ); |
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345 | _queue[index]._num_reg_rb = PORT_READ(in_INSERT_NUM_REG_RB ); |
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346 | _queue[index]._data_rb_val = PORT_READ(in_INSERT_DATA_RB_VAL ); |
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347 | _queue[index]._data_rb = PORT_READ(in_INSERT_DATA_RB ); |
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348 | // _queue[index]._read_rc = PORT_READ(in_INSERT_READ_RC ); |
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349 | _queue[index]._num_reg_rc = PORT_READ(in_INSERT_NUM_REG_RC ); |
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350 | _queue[index]._data_rc_val = PORT_READ(in_INSERT_DATA_RC_VAL ); |
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351 | _queue[index]._data_rc = PORT_READ(in_INSERT_DATA_RC ); |
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352 | _queue[index]._write_rd = PORT_READ(in_INSERT_WRITE_RD ); |
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353 | _queue[index]._num_reg_rd = PORT_READ(in_INSERT_NUM_REG_RD ); |
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354 | _queue[index]._write_re = PORT_READ(in_INSERT_WRITE_RE ); |
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355 | _queue[index]._num_reg_re = PORT_READ(in_INSERT_NUM_REG_RE ); |
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356 | // dump_queue(); |
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357 | } |
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358 | } |
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359 | |
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360 | dump_queue(); |
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361 | |
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362 | end_cycle (); |
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363 | |
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364 | log_end(Reservation_station,FUNCTION); |
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365 | }; |
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366 | |
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367 | }; // end namespace reservation_station |
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368 | }; // end namespace read_unit |
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369 | }; // end namespace multi_read_unit |
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370 | }; // end namespace execute_loop |
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371 | }; // end namespace multi_execute_loop |
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372 | }; // end namespace core |
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373 | |
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374 | }; // end namespace behavioural |
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375 | }; // end namespace morpheo |
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376 | #endif |
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377 | //#endif |
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