1 | /* |
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2 | * $Id: test.cpp 112 2009-03-18 22:36:26Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #define NB_ITERATION 16 |
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10 | #define CYCLE_MAX (1024*NB_ITERATION) |
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11 | |
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12 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/SelfTest/include/test.h" |
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13 | #include "Common/include/Test.h" |
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14 | #include "Common/include/BitManipulation.h" |
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15 | #include "Behavioural/include/Allocation.h" |
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16 | |
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17 | class write_req_t |
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18 | { |
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19 | public : uint32_t ooo; |
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20 | public : uint32_t reg; |
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21 | |
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22 | write_req_t (uint32_t ooo, |
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23 | uint32_t reg) |
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24 | { |
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25 | this->ooo = ooo; |
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26 | this->reg = reg; |
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27 | } |
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28 | }; |
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29 | |
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30 | void test (string name, |
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31 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::Parameters * _param) |
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32 | { |
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33 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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34 | |
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35 | #ifdef STATISTICS |
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36 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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37 | #endif |
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38 | |
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39 | Tusage_t _usage = USE_ALL; |
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40 | |
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41 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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42 | // _usage = usage_unset(_usage,USE_VHDL ); |
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43 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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44 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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45 | // _usage = usage_unset(_usage,USE_POSITION ); |
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46 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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47 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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48 | |
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49 | Read_unit * _Read_unit = new Read_unit |
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50 | (name.c_str(), |
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51 | #ifdef STATISTICS |
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52 | _parameters_statistics, |
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53 | #endif |
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54 | _param, |
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55 | _usage); |
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56 | |
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57 | #ifdef SYSTEMC |
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58 | /********************************************************************* |
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59 | * Déclarations des signaux |
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60 | *********************************************************************/ |
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61 | string rename; |
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62 | |
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63 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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64 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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65 | |
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66 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_VAL ," in_READ_UNIT_IN_VAL ",Tcontrol_t ); |
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67 | ALLOC0_SC_SIGNAL(out_READ_UNIT_IN_ACK ,"out_READ_UNIT_IN_ACK ",Tcontrol_t ); |
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68 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_CONTEXT_ID ," in_READ_UNIT_IN_CONTEXT_ID ",Tcontext_t ); |
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69 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_FRONT_END_ID ," in_READ_UNIT_IN_FRONT_END_ID ",Tcontext_t ); |
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70 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_OOO_ENGINE_ID ," in_READ_UNIT_IN_OOO_ENGINE_ID ",Tcontext_t ); |
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71 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_PACKET_ID ," in_READ_UNIT_IN_PACKET_ID ",Tpacket_t ); |
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72 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_OPERATION ," in_READ_UNIT_IN_OPERATION ",Toperation_t ); |
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73 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_TYPE ," in_READ_UNIT_IN_TYPE ",Ttype_t ); |
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74 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ," in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ",Tlsq_ptr_t ); |
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75 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ," in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ); |
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76 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_HAS_IMMEDIAT ," in_READ_UNIT_IN_HAS_IMMEDIAT ",Tcontrol_t ); |
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77 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_IMMEDIAT ," in_READ_UNIT_IN_IMMEDIAT ",Tgeneral_data_t ); |
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78 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_READ_RA ," in_READ_UNIT_IN_READ_RA ",Tcontrol_t ); |
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79 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RA ," in_READ_UNIT_IN_NUM_REG_RA ",Tgeneral_address_t); |
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80 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_READ_RB ," in_READ_UNIT_IN_READ_RB ",Tcontrol_t ); |
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81 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RB ," in_READ_UNIT_IN_NUM_REG_RB ",Tgeneral_address_t); |
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82 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_READ_RC ," in_READ_UNIT_IN_READ_RC ",Tcontrol_t ); |
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83 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RC ," in_READ_UNIT_IN_NUM_REG_RC ",Tspecial_address_t); |
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84 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_WRITE_RD ," in_READ_UNIT_IN_WRITE_RD ",Tcontrol_t ); |
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85 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RD ," in_READ_UNIT_IN_NUM_REG_RD ",Tgeneral_address_t); |
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86 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_WRITE_RE ," in_READ_UNIT_IN_WRITE_RE ",Tcontrol_t ); |
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87 | ALLOC0_SC_SIGNAL( in_READ_UNIT_IN_NUM_REG_RE ," in_READ_UNIT_IN_NUM_REG_RE ",Tspecial_address_t); |
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88 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_VAL ,"out_READ_UNIT_OUT_VAL ",Tcontrol_t ,_param->_nb_inst_retire); |
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89 | ALLOC1_SC_SIGNAL( in_READ_UNIT_OUT_ACK ," in_READ_UNIT_OUT_ACK ",Tcontrol_t ,_param->_nb_inst_retire); |
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90 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_CONTEXT_ID ,"out_READ_UNIT_OUT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_retire); |
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91 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_FRONT_END_ID ,"out_READ_UNIT_OUT_FRONT_END_ID ",Tcontext_t ,_param->_nb_inst_retire); |
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92 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_OOO_ENGINE_ID ,"out_READ_UNIT_OUT_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_inst_retire); |
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93 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_PACKET_ID ,"out_READ_UNIT_OUT_PACKET_ID ",Tpacket_t ,_param->_nb_inst_retire); |
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94 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_OPERATION ,"out_READ_UNIT_OUT_OPERATION ",Toperation_t ,_param->_nb_inst_retire); |
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95 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_TYPE ,"out_READ_UNIT_OUT_TYPE ",Ttype_t ,_param->_nb_inst_retire); |
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96 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,"out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE",Tlsq_ptr_t ,_param->_nb_inst_retire); |
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97 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,"out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ",Tlsq_ptr_t ,_param->_nb_inst_retire); |
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98 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_HAS_IMMEDIAT ,"out_READ_UNIT_OUT_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_retire); |
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99 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_IMMEDIAT ,"out_READ_UNIT_OUT_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_retire); |
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100 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_DATA_RA ,"out_READ_UNIT_OUT_DATA_RA ",Tgeneral_data_t ,_param->_nb_inst_retire); |
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101 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_DATA_RB ,"out_READ_UNIT_OUT_DATA_RB ",Tgeneral_data_t ,_param->_nb_inst_retire); |
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102 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_DATA_RC ,"out_READ_UNIT_OUT_DATA_RC ",Tspecial_data_t ,_param->_nb_inst_retire); |
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103 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_WRITE_RD ,"out_READ_UNIT_OUT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_retire); |
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104 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_NUM_REG_RD ,"out_READ_UNIT_OUT_NUM_REG_RD ",Tgeneral_address_t,_param->_nb_inst_retire); |
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105 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_WRITE_RE ,"out_READ_UNIT_OUT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_retire); |
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106 | ALLOC1_SC_SIGNAL(out_READ_UNIT_OUT_NUM_REG_RE ,"out_READ_UNIT_OUT_NUM_REG_RE ",Tspecial_address_t,_param->_nb_inst_retire); |
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107 | ALLOC1_SC_SIGNAL(out_GPR_READ_VAL ,"out_GPR_READ_VAL ",Tcontrol_t ,_param->_nb_gpr_read); |
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108 | ALLOC1_SC_SIGNAL( in_GPR_READ_ACK ," in_GPR_READ_ACK ",Tcontrol_t ,_param->_nb_gpr_read); |
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109 | ALLOC1_SC_SIGNAL(out_GPR_READ_OOO_ENGINE_ID ,"out_GPR_READ_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_gpr_read); |
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110 | ALLOC1_SC_SIGNAL(out_GPR_READ_NUM_REG ,"out_GPR_READ_NUM_REG ",Tgeneral_address_t,_param->_nb_gpr_read); |
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111 | ALLOC1_SC_SIGNAL( in_GPR_READ_DATA ," in_GPR_READ_DATA ",Tgeneral_data_t ,_param->_nb_gpr_read); |
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112 | ALLOC1_SC_SIGNAL( in_GPR_READ_DATA_VAL ," in_GPR_READ_DATA_VAL ",Tcontrol_t ,_param->_nb_gpr_read); |
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113 | ALLOC1_SC_SIGNAL(out_SPR_READ_VAL ,"out_SPR_READ_VAL ",Tcontrol_t ,_param->_nb_spr_read); |
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114 | ALLOC1_SC_SIGNAL( in_SPR_READ_ACK ," in_SPR_READ_ACK ",Tcontrol_t ,_param->_nb_spr_read); |
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115 | ALLOC1_SC_SIGNAL(out_SPR_READ_OOO_ENGINE_ID ,"out_SPR_READ_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_spr_read); |
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116 | ALLOC1_SC_SIGNAL(out_SPR_READ_NUM_REG ,"out_SPR_READ_NUM_REG ",Tspecial_address_t,_param->_nb_spr_read); |
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117 | ALLOC1_SC_SIGNAL( in_SPR_READ_DATA ," in_SPR_READ_DATA ",Tspecial_data_t ,_param->_nb_spr_read); |
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118 | ALLOC1_SC_SIGNAL( in_SPR_READ_DATA_VAL ," in_SPR_READ_DATA_VAL ",Tcontrol_t ,_param->_nb_spr_read); |
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119 | ALLOC1_SC_SIGNAL( in_GPR_WRITE_VAL ," in_GPR_WRITE_VAL ",Tcontrol_t ,_param->_nb_gpr_write); |
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120 | ALLOC1_SC_SIGNAL( in_GPR_WRITE_OOO_ENGINE_ID ," in_GPR_WRITE_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_gpr_write); |
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121 | ALLOC1_SC_SIGNAL( in_GPR_WRITE_NUM_REG ," in_GPR_WRITE_NUM_REG ",Tgeneral_address_t,_param->_nb_gpr_write); |
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122 | ALLOC1_SC_SIGNAL( in_GPR_WRITE_DATA ," in_GPR_WRITE_DATA ",Tgeneral_data_t ,_param->_nb_gpr_write); |
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123 | ALLOC1_SC_SIGNAL( in_SPR_WRITE_VAL ," in_SPR_WRITE_VAL ",Tcontrol_t ,_param->_nb_spr_write); |
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124 | ALLOC1_SC_SIGNAL( in_SPR_WRITE_OOO_ENGINE_ID ," in_SPR_WRITE_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_spr_write); |
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125 | ALLOC1_SC_SIGNAL( in_SPR_WRITE_NUM_REG ," in_SPR_WRITE_NUM_REG ",Tspecial_address_t,_param->_nb_spr_write); |
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126 | ALLOC1_SC_SIGNAL( in_SPR_WRITE_DATA ," in_SPR_WRITE_DATA ",Tspecial_data_t ,_param->_nb_spr_write); |
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127 | ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_OOO_ENGINE_ID ," in_BYPASS_WRITE_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_bypass_write); |
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128 | ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_GPR_VAL ," in_BYPASS_WRITE_GPR_VAL ",Tcontrol_t ,_param->_nb_bypass_write); |
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129 | ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_GPR_NUM_REG ," in_BYPASS_WRITE_GPR_NUM_REG ",Tgeneral_address_t,_param->_nb_bypass_write); |
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130 | ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_GPR_DATA ," in_BYPASS_WRITE_GPR_DATA ",Tgeneral_data_t ,_param->_nb_bypass_write); |
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131 | ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_SPR_VAL ," in_BYPASS_WRITE_SPR_VAL ",Tcontrol_t ,_param->_nb_bypass_write); |
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132 | ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_SPR_NUM_REG ," in_BYPASS_WRITE_SPR_NUM_REG ",Tspecial_address_t,_param->_nb_bypass_write); |
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133 | ALLOC1_SC_SIGNAL( in_BYPASS_WRITE_SPR_DATA ," in_BYPASS_WRITE_SPR_DATA ",Tspecial_data_t ,_param->_nb_bypass_write); |
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134 | ALLOC1_SC_SIGNAL( in_BYPASS_MEMORY_VAL ," in_BYPASS_MEMORY_VAL ",Tcontrol_t ,_param->_nb_bypass_memory); |
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135 | ALLOC1_SC_SIGNAL( in_BYPASS_MEMORY_OOO_ENGINE_ID ," in_BYPASS_MEMORY_OOO_ENGINE_ID ",Tcontext_t ,_param->_nb_bypass_memory); |
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136 | ALLOC1_SC_SIGNAL( in_BYPASS_MEMORY_NUM_REG ," in_BYPASS_MEMORY_NUM_REG ",Tgeneral_address_t,_param->_nb_bypass_memory); |
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137 | ALLOC1_SC_SIGNAL( in_BYPASS_MEMORY_DATA ," in_BYPASS_MEMORY_DATA ",Tgeneral_data_t ,_param->_nb_bypass_memory); |
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138 | |
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139 | /******************************************************** |
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140 | * Instanciation |
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141 | ********************************************************/ |
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142 | |
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143 | msg(_("<%s> : Instanciation of _Read_unit.\n"),name.c_str()); |
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144 | |
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145 | (*(_Read_unit->in_CLOCK)) (*(in_CLOCK)); |
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146 | (*(_Read_unit->in_NRESET)) (*(in_NRESET)); |
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147 | |
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148 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_VAL ); |
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149 | INSTANCE0_SC_SIGNAL(_Read_unit,out_READ_UNIT_IN_ACK ); |
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150 | if (_param->_have_port_context_id) |
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151 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_CONTEXT_ID ); |
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152 | if (_param->_have_port_front_end_id) |
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153 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_FRONT_END_ID ); |
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154 | if (_param->_have_port_ooo_engine_id) |
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155 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_OOO_ENGINE_ID ); |
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156 | if (_param->_have_port_rob_ptr) |
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157 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_PACKET_ID ); |
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158 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_OPERATION ); |
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159 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_TYPE ); |
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160 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE ); |
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161 | if (_param->_have_port_load_queue_ptr) |
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162 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ); |
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163 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_HAS_IMMEDIAT ); |
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164 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_IMMEDIAT ); |
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165 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_READ_RA ); |
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166 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RA ); |
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167 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_READ_RB ); |
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168 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RB ); |
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169 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_READ_RC ); |
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170 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RC ); |
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171 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_WRITE_RD ); |
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172 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RD ); |
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173 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_WRITE_RE ); |
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174 | INSTANCE0_SC_SIGNAL(_Read_unit, in_READ_UNIT_IN_NUM_REG_RE ); |
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175 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_VAL ,_param->_nb_inst_retire); |
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176 | INSTANCE1_SC_SIGNAL(_Read_unit, in_READ_UNIT_OUT_ACK ,_param->_nb_inst_retire); |
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177 | if (_param->_have_port_context_id) |
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178 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_CONTEXT_ID ,_param->_nb_inst_retire); |
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179 | if (_param->_have_port_front_end_id) |
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180 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_FRONT_END_ID ,_param->_nb_inst_retire); |
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181 | if (_param->_have_port_ooo_engine_id) |
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182 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_OOO_ENGINE_ID ,_param->_nb_inst_retire); |
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183 | if (_param->_have_port_rob_ptr) |
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184 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_PACKET_ID ,_param->_nb_inst_retire); |
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185 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_OPERATION ,_param->_nb_inst_retire); |
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186 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_TYPE ,_param->_nb_inst_retire); |
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187 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,_param->_nb_inst_retire); |
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188 | if (_param->_have_port_load_queue_ptr) |
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189 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,_param->_nb_inst_retire); |
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190 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_HAS_IMMEDIAT ,_param->_nb_inst_retire); |
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191 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_IMMEDIAT ,_param->_nb_inst_retire); |
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192 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_DATA_RA ,_param->_nb_inst_retire); |
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193 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_DATA_RB ,_param->_nb_inst_retire); |
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194 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_DATA_RC ,_param->_nb_inst_retire); |
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195 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_WRITE_RD ,_param->_nb_inst_retire); |
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196 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_NUM_REG_RD ,_param->_nb_inst_retire); |
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197 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_WRITE_RE ,_param->_nb_inst_retire); |
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198 | INSTANCE1_SC_SIGNAL(_Read_unit,out_READ_UNIT_OUT_NUM_REG_RE ,_param->_nb_inst_retire); |
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199 | INSTANCE1_SC_SIGNAL(_Read_unit,out_GPR_READ_VAL ,_param->_nb_gpr_read); |
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200 | INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_READ_ACK ,_param->_nb_gpr_read); |
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201 | if (_param->_have_port_ooo_engine_id) |
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202 | INSTANCE1_SC_SIGNAL(_Read_unit,out_GPR_READ_OOO_ENGINE_ID ,_param->_nb_gpr_read); |
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203 | INSTANCE1_SC_SIGNAL(_Read_unit,out_GPR_READ_NUM_REG ,_param->_nb_gpr_read); |
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204 | INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_READ_DATA ,_param->_nb_gpr_read); |
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205 | INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_READ_DATA_VAL ,_param->_nb_gpr_read); |
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206 | INSTANCE1_SC_SIGNAL(_Read_unit,out_SPR_READ_VAL ,_param->_nb_spr_read); |
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207 | INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_READ_ACK ,_param->_nb_spr_read); |
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208 | if (_param->_have_port_ooo_engine_id) |
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209 | INSTANCE1_SC_SIGNAL(_Read_unit,out_SPR_READ_OOO_ENGINE_ID ,_param->_nb_spr_read); |
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210 | INSTANCE1_SC_SIGNAL(_Read_unit,out_SPR_READ_NUM_REG ,_param->_nb_spr_read); |
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211 | INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_READ_DATA ,_param->_nb_spr_read); |
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212 | INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_READ_DATA_VAL ,_param->_nb_spr_read); |
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213 | INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_WRITE_VAL ,_param->_nb_gpr_write); |
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214 | if (_param->_have_port_ooo_engine_id) |
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215 | INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_WRITE_OOO_ENGINE_ID ,_param->_nb_gpr_write); |
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216 | INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_WRITE_NUM_REG ,_param->_nb_gpr_write); |
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217 | INSTANCE1_SC_SIGNAL(_Read_unit, in_GPR_WRITE_DATA ,_param->_nb_gpr_write); |
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218 | INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_WRITE_VAL ,_param->_nb_spr_write); |
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219 | if (_param->_have_port_ooo_engine_id) |
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220 | INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_WRITE_OOO_ENGINE_ID ,_param->_nb_spr_write); |
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221 | INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_WRITE_NUM_REG ,_param->_nb_spr_write); |
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222 | INSTANCE1_SC_SIGNAL(_Read_unit, in_SPR_WRITE_DATA ,_param->_nb_spr_write); |
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223 | if (_param->_have_port_ooo_engine_id) |
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224 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_OOO_ENGINE_ID ,_param->_nb_bypass_write); |
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225 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_GPR_VAL ,_param->_nb_bypass_write); |
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226 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_GPR_NUM_REG ,_param->_nb_bypass_write); |
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227 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_GPR_DATA ,_param->_nb_bypass_write); |
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228 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_SPR_VAL ,_param->_nb_bypass_write); |
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229 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_SPR_NUM_REG ,_param->_nb_bypass_write); |
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230 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_WRITE_SPR_DATA ,_param->_nb_bypass_write); |
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231 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_MEMORY_VAL ,_param->_nb_bypass_memory); |
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232 | if (_param->_have_port_ooo_engine_id) |
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233 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_MEMORY_OOO_ENGINE_ID ,_param->_nb_bypass_memory); |
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234 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_MEMORY_NUM_REG ,_param->_nb_bypass_memory); |
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235 | INSTANCE1_SC_SIGNAL(_Read_unit, in_BYPASS_MEMORY_DATA ,_param->_nb_bypass_memory); |
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236 | |
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237 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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238 | |
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239 | // Initialisation |
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240 | const uint32_t seed = 0; |
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241 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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242 | |
---|
243 | srand(seed); |
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244 | |
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245 | SC_START(0); |
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246 | |
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247 | Time * _time = new Time(); |
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248 | |
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249 | /******************************************************** |
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250 | * Simulation - Begin |
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251 | ********************************************************/ |
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252 | { |
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253 | // Initialisation |
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254 | |
---|
255 | const uint32_t nb_request = _param->_nb_packet; |
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256 | |
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257 | Tcontext_t _ooo_engine_id [nb_request]; |
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258 | Tcontrol_t _read_ra [nb_request]; |
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259 | Tgeneral_address_t _num_reg_ra [nb_request]; |
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260 | Tcontrol_t _read_rb [nb_request]; |
---|
261 | Tgeneral_address_t _num_reg_rb [nb_request]; |
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262 | Tcontrol_t _read_rc [nb_request]; |
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263 | Tspecial_address_t _num_reg_rc [nb_request]; |
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264 | |
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265 | // emulation of registerFile |
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266 | Tcontrol_t _gpr_val [_param->_nb_general_register][_param->_nb_ooo_engine]; |
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267 | Tgeneral_data_t _gpr [_param->_nb_general_register][_param->_nb_ooo_engine]; |
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268 | Tcontrol_t _spr_val [_param->_nb_special_register][_param->_nb_ooo_engine]; |
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269 | Tspecial_data_t _spr [_param->_nb_special_register][_param->_nb_ooo_engine]; |
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270 | |
---|
271 | LABEL("Initialisation"); |
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272 | in_READ_UNIT_IN_VAL ->write(0); |
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273 | for (uint32_t i=0; i<_param->_nb_inst_retire ; i++) |
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274 | in_READ_UNIT_OUT_ACK [i]->write(0); |
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275 | for (uint32_t i=0; i<_param->_nb_gpr_write ; i++) |
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276 | in_GPR_WRITE_VAL [i]->write(0); |
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277 | for (uint32_t i=0; i<_param->_nb_spr_write ; i++) |
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278 | in_SPR_WRITE_VAL [i]->write(0); |
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279 | for (uint32_t i=0; i<_param->_nb_bypass_write ; i++) |
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280 | { |
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281 | in_BYPASS_WRITE_GPR_VAL [i]->write(0); |
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282 | in_BYPASS_WRITE_SPR_VAL [i]->write(0); |
---|
283 | } |
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284 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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285 | in_BYPASS_MEMORY_VAL [i]->write(0); |
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286 | |
---|
287 | in_NRESET->write(0); |
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288 | SC_START(5); |
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289 | in_NRESET->write(1); |
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290 | |
---|
291 | LABEL("Loop of Test"); |
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292 | |
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293 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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294 | { |
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295 | LABEL("Iteration %d",iteration); |
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296 | |
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297 | int32_t percent_transaction_queue_in = (rand()%50)+25; |
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298 | int32_t percent_transaction_queue_out = (rand()%50)+25; |
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299 | int32_t percent_registerfile_valid = (rand()%50)+25; |
---|
300 | int32_t percent_transaction_registerfile = (rand()%50)+25; |
---|
301 | int32_t percent_transaction_bypass = (rand()%50)+25; |
---|
302 | |
---|
303 | LABEL("Initialisation"); |
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304 | |
---|
305 | for (uint32_t i=0; i<nb_request; i++) |
---|
306 | { |
---|
307 | _ooo_engine_id [i] = rand()% _param->_nb_ooo_engine ; |
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308 | _read_ra [i] = rand()% 2 ; |
---|
309 | _num_reg_ra [i] = rand()% _param->_nb_general_register ; |
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310 | _read_rb [i] = rand()% 2 ; |
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311 | _num_reg_rb [i] = rand()% _param->_nb_general_register ; |
---|
312 | _read_rc [i] = rand()% 2 ; |
---|
313 | _num_reg_rc [i] = rand()% _param->_nb_special_register ; |
---|
314 | } |
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315 | |
---|
316 | // emulation of registerFile |
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317 | for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
---|
318 | { |
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319 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
---|
320 | { |
---|
321 | _gpr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
---|
322 | _gpr [i][j] = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
323 | } |
---|
324 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
---|
325 | { |
---|
326 | _spr_val [i][j] = ((rand()%100) < percent_registerfile_valid); |
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327 | _spr [i][j] = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
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328 | } |
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329 | } |
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330 | // End initialisation ....... |
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331 | |
---|
332 | uint32_t request_in = 0; |
---|
333 | uint32_t request_out = 0; |
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334 | bool request_out_wait [nb_request]; |
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335 | |
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336 | for (uint32_t i=0; i<nb_request; i++) |
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337 | request_out_wait [i] = true; |
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338 | |
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339 | // bool can_gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register]; |
---|
340 | // bool can_spr_use [_param->_nb_ooo_engine][_param->_nb_special_register]; |
---|
341 | |
---|
342 | list<write_req_t> write_req_gpr; |
---|
343 | list<write_req_t> write_req_spr; |
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344 | |
---|
345 | while (request_out < nb_request) |
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346 | { |
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347 | LABEL("request_in : %d",request_in ); |
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348 | LABEL("request_out : %d",request_out); |
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349 | for (uint32_t i=0; i<nb_request; i++) |
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350 | if (request_out_wait [i]) |
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351 | LABEL("request_out_wait : %d",i); |
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352 | LABEL("write_req_gpr size : %d",write_req_gpr.size()); |
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353 | LABEL("write_req_spr size : %d",write_req_spr.size()); |
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354 | |
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355 | // for (uint32_t j=0; j<_param->_nb_ooo_engine; j++) |
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356 | // { |
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357 | // for (uint32_t i=0; i<_param->_nb_general_register; i++) |
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358 | // can_gpr_use [j][i] = true; |
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359 | // for (uint32_t i=0; i<_param->_nb_special_register; i++) |
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360 | // can_spr_use [j][i] = true; |
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361 | // } |
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362 | |
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363 | Tcontrol_t read_unit_in_val = (request_in < nb_request) and ((rand()%100) < percent_transaction_queue_in); |
---|
364 | Tcontext_t read_unit_in_ooo_engine_id; |
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365 | Tgeneral_address_t read_unit_in_num_reg_ra; |
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366 | Tgeneral_address_t read_unit_in_num_reg_rb; |
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367 | Tspecial_address_t read_unit_in_num_reg_rc; |
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368 | |
---|
369 | in_READ_UNIT_IN_VAL ->write(read_unit_in_val); |
---|
370 | if (read_unit_in_val) |
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371 | { |
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372 | bool data_val; |
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373 | read_unit_in_ooo_engine_id = _ooo_engine_id [request_in]; |
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374 | read_unit_in_num_reg_ra = _num_reg_ra [request_in]; |
---|
375 | read_unit_in_num_reg_rb = _num_reg_rb [request_in]; |
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376 | read_unit_in_num_reg_rc = _num_reg_rc [request_in]; |
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377 | |
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378 | if (_param->_have_port_context_id) |
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379 | in_READ_UNIT_IN_CONTEXT_ID ->write((2*read_unit_in_ooo_engine_id)%_param->_nb_context ); |
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380 | if (_param->_have_port_front_end_id) |
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381 | in_READ_UNIT_IN_FRONT_END_ID ->write((3*read_unit_in_ooo_engine_id)%_param->_nb_front_end); |
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382 | if (_param->_have_port_ooo_engine_id) |
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383 | in_READ_UNIT_IN_OOO_ENGINE_ID ->write(read_unit_in_ooo_engine_id); |
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384 | if (_param->_have_port_rob_ptr) |
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385 | in_READ_UNIT_IN_PACKET_ID ->write(request_in); |
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386 | in_READ_UNIT_IN_OPERATION ->write(0); |
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387 | in_READ_UNIT_IN_TYPE ->write(0); |
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388 | in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE->write(0); |
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389 | if (_param->_have_port_load_queue_ptr) |
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390 | in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ->write(0); |
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391 | in_READ_UNIT_IN_HAS_IMMEDIAT->write(0); |
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392 | in_READ_UNIT_IN_IMMEDIAT ->write(0); |
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393 | in_READ_UNIT_IN_READ_RA ->write(_read_ra[request_in]); |
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394 | data_val = not(_read_ra[request_in]) or _gpr_val[read_unit_in_num_reg_ra][read_unit_in_ooo_engine_id]; |
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395 | |
---|
396 | if (not data_val) |
---|
397 | if (rand ()%2) |
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398 | write_req_gpr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_ra)); |
---|
399 | else |
---|
400 | write_req_gpr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_ra)); |
---|
401 | |
---|
402 | |
---|
403 | in_READ_UNIT_IN_NUM_REG_RA ->write(read_unit_in_num_reg_ra); |
---|
404 | // in_READ_UNIT_IN_DATA_RA_VAL ->write(data_val); |
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405 | // in_READ_UNIT_IN_DATA_RA ->write((data_val)?_gpr[read_unit_in_num_reg_ra][read_unit_in_ooo_engine_id]:0); |
---|
406 | in_READ_UNIT_IN_READ_RB ->write(_read_rb[request_in]); |
---|
407 | data_val = not(_read_rb[request_in]) or _gpr_val[read_unit_in_num_reg_rb][read_unit_in_ooo_engine_id]; |
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408 | |
---|
409 | if (not data_val) |
---|
410 | if (rand ()%2) |
---|
411 | write_req_gpr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rb)); |
---|
412 | else |
---|
413 | write_req_gpr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rb)); |
---|
414 | |
---|
415 | |
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416 | in_READ_UNIT_IN_NUM_REG_RB ->write(read_unit_in_num_reg_rb); |
---|
417 | // in_READ_UNIT_IN_DATA_RB_VAL ->write(data_val); |
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418 | // in_READ_UNIT_IN_DATA_RB ->write((data_val)?_gpr[read_unit_in_num_reg_rb][read_unit_in_ooo_engine_id]:0); |
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419 | in_READ_UNIT_IN_READ_RC ->write(_read_rc[request_in]); |
---|
420 | data_val = not(_read_rc[request_in]) or _spr_val[read_unit_in_num_reg_rc][read_unit_in_ooo_engine_id]; |
---|
421 | |
---|
422 | if (not data_val) |
---|
423 | if (rand ()%2) |
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424 | write_req_spr.push_back (write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rc)); |
---|
425 | else |
---|
426 | write_req_spr.push_front(write_req_t(read_unit_in_ooo_engine_id,read_unit_in_num_reg_rc)); |
---|
427 | |
---|
428 | in_READ_UNIT_IN_NUM_REG_RC ->write(read_unit_in_num_reg_rc); |
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429 | // in_READ_UNIT_IN_DATA_RC_VAL ->write(data_val); |
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430 | // in_READ_UNIT_IN_DATA_RC ->write((data_val)?_spr[read_unit_in_num_reg_rc][read_unit_in_ooo_engine_id]:0); |
---|
431 | in_READ_UNIT_IN_WRITE_RD ->write(0); |
---|
432 | in_READ_UNIT_IN_NUM_REG_RD ->write(0); |
---|
433 | in_READ_UNIT_IN_WRITE_RE ->write(0); |
---|
434 | in_READ_UNIT_IN_NUM_REG_RE ->write(0); |
---|
435 | |
---|
436 | // can_gpr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_ra] = false; |
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437 | // can_gpr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_rb] = false; |
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438 | // can_spr_use [read_unit_in_ooo_engine_id][read_unit_in_num_reg_rc] = false; |
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439 | } |
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440 | |
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441 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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442 | in_READ_UNIT_OUT_ACK[i]->write((rand()%100)<percent_transaction_queue_out); |
---|
443 | |
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444 | // RegisterFile access |
---|
445 | for (uint32_t i=0; i<_param->_nb_gpr_read ; i++) |
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446 | { |
---|
447 | Tcontrol_t ack = (rand()%100) < percent_transaction_registerfile; |
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448 | in_GPR_READ_ACK [i]->write(ack); |
---|
449 | |
---|
450 | SC_START(0); |
---|
451 | |
---|
452 | if (out_GPR_READ_VAL [i]->read()) |
---|
453 | { |
---|
454 | Tgeneral_address_t num_reg = out_GPR_READ_NUM_REG [i]->read(); |
---|
455 | Tcontext_t ooo_engine = (_param->_have_port_ooo_engine_id)?out_GPR_READ_OOO_ENGINE_ID [i]->read():0; |
---|
456 | Tgeneral_data_t data = _gpr [num_reg][ooo_engine]; |
---|
457 | Tcontrol_t data_val = _gpr_val[num_reg][ooo_engine]; |
---|
458 | |
---|
459 | if (ack) |
---|
460 | LABEL(" * GPR_READ [%d] - gpr[%d][%d] -> (%d) 0x%x",i,num_reg,ooo_engine,data_val,data); |
---|
461 | |
---|
462 | in_GPR_READ_DATA [i]->write(data); |
---|
463 | in_GPR_READ_DATA_VAL [i]->write(data_val); |
---|
464 | } |
---|
465 | } |
---|
466 | |
---|
467 | for (uint32_t i=0; i<_param->_nb_spr_read ; i++) |
---|
468 | { |
---|
469 | Tcontrol_t ack = (rand()%100) < percent_transaction_registerfile; |
---|
470 | in_SPR_READ_ACK [i]->write(ack); |
---|
471 | |
---|
472 | SC_START(0); |
---|
473 | |
---|
474 | if (out_SPR_READ_VAL [i]->read()) |
---|
475 | { |
---|
476 | Tspecial_address_t num_reg = out_SPR_READ_NUM_REG [i]->read(); |
---|
477 | Tcontext_t ooo_engine = (_param->_have_port_ooo_engine_id)?out_SPR_READ_OOO_ENGINE_ID [i]->read():0; |
---|
478 | Tspecial_data_t data = _spr [num_reg][ooo_engine]; |
---|
479 | Tcontrol_t data_val = _spr_val[num_reg][ooo_engine]; |
---|
480 | |
---|
481 | if (ack) |
---|
482 | LABEL(" * SPR_READ [%d] - spr[%d][%d] -> (%d) 0x%x",i,num_reg,ooo_engine,data_val,data); |
---|
483 | |
---|
484 | in_SPR_READ_DATA [i]->write(data); |
---|
485 | in_SPR_READ_DATA_VAL [i]->write(data_val); |
---|
486 | } |
---|
487 | } |
---|
488 | |
---|
489 | list<write_req_t>::iterator it_gpr = write_req_gpr.begin(); |
---|
490 | list<write_req_t>::iterator it_spr = write_req_spr.begin(); |
---|
491 | |
---|
492 | LABEL("Bypass Network :"); |
---|
493 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
494 | { |
---|
495 | Tcontext_t ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0; |
---|
496 | Tgeneral_address_t num_reg = (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0; |
---|
497 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
498 | Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
499 | |
---|
500 | val = (val// and can_spr_use [ooo_engine][num_reg] |
---|
501 | and (it_gpr != write_req_gpr.end())); |
---|
502 | |
---|
503 | in_GPR_WRITE_VAL [i]->write(val); |
---|
504 | if (_param->_have_port_ooo_engine_id) |
---|
505 | in_GPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
506 | in_GPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
507 | in_GPR_WRITE_DATA [i]->write(data); |
---|
508 | |
---|
509 | if (val) |
---|
510 | { |
---|
511 | LABEL(" * GPR_WRITE [%d] - gpr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data); |
---|
512 | |
---|
513 | // can_gpr_use [ooo_engine][num_reg] = false; |
---|
514 | |
---|
515 | _gpr [num_reg][ooo_engine] = data; |
---|
516 | _gpr_val [num_reg][ooo_engine] = 1; |
---|
517 | } |
---|
518 | |
---|
519 | if (it_gpr != write_req_gpr.end()) |
---|
520 | it_gpr ++; |
---|
521 | } |
---|
522 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
523 | { |
---|
524 | Tcontext_t ooo_engine = (it_spr != write_req_spr.end())?(*it_spr).ooo:0; |
---|
525 | Tgeneral_address_t num_reg = (it_spr != write_req_spr.end())?(*it_spr).reg:0; |
---|
526 | |
---|
527 | Tcontrol_t val = (_spr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_registerfile):0; |
---|
528 | Tspecial_data_t data = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
529 | |
---|
530 | val = (val // and can_spr_use [ooo_engine][num_reg] |
---|
531 | and (it_spr != write_req_spr.end())); |
---|
532 | |
---|
533 | in_SPR_WRITE_VAL [i]->write(val); |
---|
534 | if (_param->_have_port_ooo_engine_id) |
---|
535 | in_SPR_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
536 | in_SPR_WRITE_NUM_REG [i]->write(num_reg); |
---|
537 | in_SPR_WRITE_DATA [i]->write(data); |
---|
538 | |
---|
539 | if (val == 1) |
---|
540 | { |
---|
541 | LABEL(" * SPR_WRITE [%d] - spr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data); |
---|
542 | |
---|
543 | // can_spr_use [ooo_engine][num_reg] = false; |
---|
544 | |
---|
545 | _spr [num_reg][ooo_engine] = data; |
---|
546 | _spr_val [num_reg][ooo_engine] = 1; |
---|
547 | } |
---|
548 | |
---|
549 | if (it_spr != write_req_spr.end()) |
---|
550 | it_spr ++; |
---|
551 | |
---|
552 | } |
---|
553 | |
---|
554 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
---|
555 | { |
---|
556 | Tcontext_t ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0; |
---|
557 | Tgeneral_address_t gpr_num_reg= (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0; |
---|
558 | |
---|
559 | if (_param->_have_port_ooo_engine_id) |
---|
560 | in_BYPASS_WRITE_OOO_ENGINE_ID [i]->write(ooo_engine); |
---|
561 | |
---|
562 | Tcontrol_t gpr_val = (_gpr_val [gpr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
563 | Tgeneral_data_t gpr_data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
---|
564 | |
---|
565 | gpr_val = (gpr_val // and can_gpr_use [ooo_engine][gpr_num_reg] |
---|
566 | and (it_gpr != write_req_gpr.end())); |
---|
567 | |
---|
568 | in_BYPASS_WRITE_GPR_VAL [i]->write(gpr_val); |
---|
569 | in_BYPASS_WRITE_GPR_NUM_REG[i]->write(gpr_num_reg); |
---|
570 | in_BYPASS_WRITE_GPR_DATA [i]->write(gpr_data); |
---|
571 | |
---|
572 | if (gpr_val) |
---|
573 | { |
---|
574 | LABEL(" * BYPASS_WRITE [%d] - gpr[%d][%d] <- 0x%x",i,gpr_num_reg,ooo_engine,gpr_data); |
---|
575 | // can_gpr_use [ooo_engine][gpr_num_reg] = false; |
---|
576 | |
---|
577 | _gpr [gpr_num_reg][ooo_engine] = gpr_data; |
---|
578 | _gpr_val [gpr_num_reg][ooo_engine] = 1; |
---|
579 | } |
---|
580 | |
---|
581 | if (it_gpr != write_req_gpr.end()) |
---|
582 | it_gpr ++; |
---|
583 | |
---|
584 | Tspecial_address_t spr_num_reg = (it_spr != write_req_spr.end())?(*it_spr).reg:0; |
---|
585 | Tcontrol_t spr_val = (_spr_val [spr_num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
---|
586 | Tspecial_data_t spr_data = range<Tspecial_data_t>(rand(),_param->_size_special_data); |
---|
587 | |
---|
588 | spr_val = (spr_val // and can_spr_use [ooo_engine][spr_num_reg] |
---|
589 | and (it_spr != write_req_spr.end()) and ((*it_spr).ooo == ooo_engine)); |
---|
590 | |
---|
591 | in_BYPASS_WRITE_SPR_VAL [i]->write(spr_val); |
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592 | in_BYPASS_WRITE_SPR_NUM_REG[i]->write(spr_num_reg); |
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593 | in_BYPASS_WRITE_SPR_DATA [i]->write(spr_data); |
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594 | |
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595 | if (spr_val) |
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596 | { |
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597 | LABEL(" * BYPASS_WRITE [%d] - spr[%d][%d] <- 0x%x",i,spr_num_reg,ooo_engine,spr_data); |
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598 | |
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599 | // can_spr_use [ooo_engine][spr_num_reg] = false; |
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600 | |
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601 | _spr [spr_num_reg][ooo_engine] = spr_data; |
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602 | _spr_val [spr_num_reg][ooo_engine] = 1; |
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603 | } |
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604 | |
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605 | if (it_spr != write_req_spr.end()) |
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606 | it_spr ++; |
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607 | } |
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608 | |
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609 | for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) |
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610 | { |
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611 | Tcontext_t ooo_engine = (it_gpr != write_req_gpr.end())?(*it_gpr).ooo:0; |
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612 | Tgeneral_address_t num_reg = (it_gpr != write_req_gpr.end())?(*it_gpr).reg:0; |
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613 | |
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614 | if (_param->_have_port_ooo_engine_id) |
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615 | in_BYPASS_MEMORY_OOO_ENGINE_ID [i]->write(ooo_engine); |
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616 | |
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617 | Tcontrol_t val = (_gpr_val [num_reg][ooo_engine]== 0)?((rand()%100) < percent_transaction_bypass):0; |
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618 | Tgeneral_data_t data = range<Tgeneral_data_t>(rand(),_param->_size_general_data); |
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619 | |
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620 | val = (val // and can_gpr_use [ooo_engine][num_reg] |
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621 | and (it_gpr != write_req_gpr.end())); |
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622 | |
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623 | in_BYPASS_MEMORY_VAL [i]->write(val); |
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624 | in_BYPASS_MEMORY_NUM_REG[i]->write(num_reg); |
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625 | in_BYPASS_MEMORY_DATA [i]->write(data); |
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626 | |
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627 | if (val) |
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628 | { |
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629 | LABEL(" * BYPASS_MEMORY [%d] - gpr[%d][%d] <- 0x%x",i,num_reg,ooo_engine,data); |
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630 | |
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631 | // can_gpr_use [ooo_engine][num_reg] = false; |
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632 | |
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633 | _gpr [num_reg][ooo_engine] = data; |
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634 | _gpr_val [num_reg][ooo_engine] = 1; |
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635 | } |
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636 | |
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637 | if (it_gpr != write_req_gpr.end()) |
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638 | it_gpr ++; |
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639 | } |
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640 | |
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641 | SC_START(0); // to mealy function |
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642 | |
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643 | // LABEL("Test READ_UNIT_IN : "+toString(in_READ_UNIT_IN_VAL->read())+","+toString(out_READ_UNIT_IN_ACK->read())); |
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644 | if (( in_READ_UNIT_IN_VAL->read() == 1) and |
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645 | (out_READ_UNIT_IN_ACK->read() == 1)) |
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646 | { |
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647 | LABEL("Accepted READ_UNIT_IN number : %d",request_in); |
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648 | request_in ++; |
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649 | } |
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650 | |
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651 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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652 | { |
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653 | LABEL("Test READ_UNIT_OUT %d : %d,%d",i,out_READ_UNIT_OUT_VAL[i]->read(),in_READ_UNIT_OUT_ACK[i]->read()); |
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654 | if ((out_READ_UNIT_OUT_VAL [i]->read() == 1) and |
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655 | ( in_READ_UNIT_OUT_ACK [i]->read() == 1)) |
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656 | { |
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657 | Tpacket_t packet_id; |
---|
658 | if (_param->_have_port_rob_ptr) |
---|
659 | packet_id = out_READ_UNIT_OUT_PACKET_ID [i]->read(); |
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660 | else |
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661 | packet_id = 0; |
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662 | LABEL("Accepted READ_UNIT_OUT [%d] number : %d, request number : %d",i,packet_id,request_out); |
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663 | TEST(bool, request_out_wait [packet_id] , true); |
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664 | |
---|
665 | request_out ++; |
---|
666 | request_out_wait [packet_id] = false; |
---|
667 | |
---|
668 | Tcontext_t ooo_engine_id = _ooo_engine_id [packet_id]; |
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669 | |
---|
670 | if (_param->_have_port_context_id) |
---|
671 | TEST(Tcontext_t ,out_READ_UNIT_OUT_CONTEXT_ID [i]->read(),(2*ooo_engine_id)%_param->_nb_context ); |
---|
672 | if (_param->_have_port_front_end_id) |
---|
673 | TEST(Tcontext_t ,out_READ_UNIT_OUT_FRONT_END_ID [i]->read(),(3*ooo_engine_id)%_param->_nb_front_end); |
---|
674 | if (_param->_have_port_ooo_engine_id) |
---|
675 | TEST(Tcontext_t ,out_READ_UNIT_OUT_OOO_ENGINE_ID[i]->read(),ooo_engine_id); |
---|
676 | |
---|
677 | if (_read_ra [packet_id]) |
---|
678 | TEST(Tgeneral_data_t ,out_READ_UNIT_OUT_DATA_RA [i]->read(),_gpr[_num_reg_ra[packet_id]][ooo_engine_id]); |
---|
679 | |
---|
680 | if (_read_rb [packet_id]) |
---|
681 | TEST(Tgeneral_data_t ,out_READ_UNIT_OUT_DATA_RB [i]->read(),_gpr[_num_reg_rb[packet_id]][ooo_engine_id]); |
---|
682 | |
---|
683 | if (_read_rc [packet_id]) |
---|
684 | TEST(Tspecial_data_t ,out_READ_UNIT_OUT_DATA_RC [i]->read(),_spr[_num_reg_rc[packet_id]][ooo_engine_id]); |
---|
685 | } |
---|
686 | } |
---|
687 | |
---|
688 | SC_START(1); |
---|
689 | |
---|
690 | for (list<write_req_t>::iterator it = write_req_gpr.begin(); |
---|
691 | it != write_req_gpr.end(); |
---|
692 | ) |
---|
693 | { |
---|
694 | if (_gpr_val [(*it).reg][(*it).ooo] == 1) |
---|
695 | it = write_req_gpr.erase(it); |
---|
696 | else |
---|
697 | it ++; |
---|
698 | } |
---|
699 | |
---|
700 | for (list<write_req_t>::iterator it = write_req_spr.begin(); |
---|
701 | it != write_req_spr.end(); |
---|
702 | ) |
---|
703 | { |
---|
704 | if (_spr_val [(*it).reg][(*it).ooo] == 1) |
---|
705 | it = write_req_spr.erase(it); |
---|
706 | else |
---|
707 | it ++; |
---|
708 | } |
---|
709 | } |
---|
710 | |
---|
711 | for (uint32_t i=0; i<nb_request; i++) |
---|
712 | TEST(bool, request_out_wait [i] , false); |
---|
713 | } |
---|
714 | } |
---|
715 | |
---|
716 | /******************************************************** |
---|
717 | * Simulation - End |
---|
718 | ********************************************************/ |
---|
719 | |
---|
720 | TEST_OK ("End of Simulation"); |
---|
721 | delete _time; |
---|
722 | |
---|
723 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
---|
724 | |
---|
725 | delete in_CLOCK; |
---|
726 | delete in_NRESET; |
---|
727 | #endif |
---|
728 | |
---|
729 | delete _Read_unit; |
---|
730 | #ifdef STATISTICS |
---|
731 | delete _parameters_statistics; |
---|
732 | #endif |
---|
733 | } |
---|