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Read_unit_allocation.cpp @ 78

Last change on this file since 78 was 78, checked in by rosiere, 16 years ago

Add :

Execute_loop (must be test systemC)
Prediction
- Direction : predifined scheme
- Branch Target Buffer
iFetch_unit
- ifetch_queue
- pc management
Decod_unit
- coming soon : support for custom operation
Rename_unit
- RAT
- Free_list
- Dependence RAW check
- Load store unit pointer
New Environnement (hierarchy_memory will remove in a next version)

Modif :

Manage Custom Operation
All component in execute_loop to use the new statistics management

Not Finish :

Return Address Stack
Environnement

File size: 34.1 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/include/Read_unit.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_execute_loop {
15	namespace execute_loop {
16	namespace multi_read_unit {
17	namespace read_unit {
18
19
20
21	#undef FUNCTION
22	#define FUNCTION "Read_unit::allocation"
23	void Read_unit::allocation (
24	#ifdef STATISTICS
25	morpheo::behavioural::Parameters_Statistics * param_statistics
26	#else
27	void
28	#endif
29	)
30	{
31	log_printf(FUNC,Read_unit,FUNCTION,"Begin");
32
33	_component = new Component (_usage);
34
35	Entity * entity = _component->set_entity (_name
36	,"Read_unit"
37	#ifdef POSITION
38	,COMBINATORY
39	#endif
40	);
41
42	_interfaces = entity->set_interfaces();
43
44	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
45
46	Interface * interface = _interfaces->set_interface(""
47	#ifdef POSITION
48	,IN
49	,SOUTH,
50	"Generalist interface"
51	#endif
52	);
53
54	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
55	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
56
57	// ~~~~~[ Interface "read_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58	{
59	ALLOC_INTERFACE("read_unit_in", IN, WEST, "Enter of new operation");
60
61	ALLOC_VALACK_IN ( in_READ_UNIT_IN_VAL,VAL);
62	ALLOC_VALACK_OUT (out_READ_UNIT_IN_ACK,ACK);
63	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );
64	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id );
65	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id);
66	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id );
67	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation );
68	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type );
69	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,log2(_param->_size_store_queue));
70	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,log2(_param->_size_load_queue));
71	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1);
72	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data);
73	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_READ_RA ,"read_ra" ,Tcontrol_t ,1);
74	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register);
75	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_READ_RB ,"read_rb" ,Tcontrol_t ,1);
76	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register);
77	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_READ_RC ,"read_rc" ,Tcontrol_t ,1);
78	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register);
79	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1);
80	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register);
81	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1);
82	ALLOC_SIGNAL_IN ( in_READ_UNIT_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register);
83	}
84
85	// ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
86	{
87	ALLOC1_INTERFACE("read_unit_out", OUT, EAST, "Output of operation. All operand is valid.", _param->_nb_inst_retire);
88
89	ALLOC1_VALACK_OUT (out_READ_UNIT_OUT_VAL,VAL);
90	ALLOC1_VALACK_IN ( in_READ_UNIT_OUT_ACK,ACK);
91	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );
92	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id );
93	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id );
94	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id );
95	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation );
96	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type );
97	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,log2(_param->_size_store_queue));
98	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,log2(_param->_size_load_queue ));
99	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 );
100	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data );
101	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data );
102	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data );
103	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data );
104	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 );
105	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register);
106	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 );
107	ALLOC1_SIGNAL_OUT(out_READ_UNIT_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register);
108	}
109
110	// ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
111	{
112	ALLOC1_INTERFACE("gpr_read", OUT, SOUTH, "Read port.", _param->_nb_gpr_read);
113
114	ALLOC1_VALACK_OUT (out_GPR_READ_VAL,VAL);
115	ALLOC1_VALACK_IN ( in_GPR_READ_ACK,ACK);
116	ALLOC1_SIGNAL_OUT(out_GPR_READ_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
117	ALLOC1_SIGNAL_OUT(out_GPR_READ_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_data );
118	ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_register);
119	ALLOC1_SIGNAL_IN ( in_GPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1);
120	}
121
122	// ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
123	{
124	ALLOC1_INTERFACE("spr_read", OUT, SOUTH, "Read port.", _param->_nb_spr_read);
125
126	ALLOC1_VALACK_OUT (out_SPR_READ_VAL,VAL);
127	ALLOC1_VALACK_IN ( in_SPR_READ_ACK,ACK);
128	ALLOC1_SIGNAL_OUT(out_SPR_READ_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
129	ALLOC1_SIGNAL_OUT(out_SPR_READ_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_data );
130	ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_register);
131	ALLOC1_SIGNAL_IN ( in_SPR_READ_DATA_VAL ,"data_val" ,Tcontrol_t ,1);
132	}
133
134	// ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
135	{
136	ALLOC1_INTERFACE("gpr_write", IN , SOUTH, "Write port.", _param->_nb_gpr_write);
137
138	ALLOC1_VALACK_IN ( in_GPR_WRITE_VAL,VAL);
139	ALLOC1_SIGNAL_IN ( in_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
140	ALLOC1_SIGNAL_IN ( in_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_data );
141	ALLOC1_SIGNAL_IN ( in_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_register);
142	}
143
144	// ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
145	{
146	ALLOC1_INTERFACE("spr_write", IN , SOUTH, "Write port.", _param->_nb_spr_write);
147
148	ALLOC1_VALACK_IN ( in_SPR_WRITE_VAL,VAL);
149	ALLOC1_SIGNAL_IN ( in_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
150	ALLOC1_SIGNAL_IN ( in_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_data );
151	ALLOC1_SIGNAL_IN ( in_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_register);
152	}
153
154	// ~~~~~[ Interface "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
155	{
156	ALLOC1_INTERFACE("bypass_write", IN , NORTH, "Output of write_queue.", _param->_nb_bypass_write);
157
158	ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
159	ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1);
160	ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_data );
161	ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_register);
162	ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1);
163	ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_data );
164	ALLOC1_SIGNAL_IN ( in_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_register);
165	}
166
167	// ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
168	{
169	ALLOC1_INTERFACE("bypass_memory", IN , NORTH, "Output of write_queue.", _param->_nb_bypass_memory);
170
171	ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_VAL ,"val" ,Tcontrol_t ,1);
172	ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
173	ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_data );
174	ALLOC1_SIGNAL_IN ( in_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_register);
175	}
176
177	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
178
179	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
180
181	std::string name;
182
183	{
184	name = _name+"_read_queue";
185
186	_component_read_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::read_queue::Read_queue (name.c_str()
187	#ifdef STATISTICS
188	,param_statistics
189	#endif
190	,_param->_param_read_queue);
191
192	_component->set_component (_component_read_queue->_component
193	#ifdef POSITION
194	, 50, 50, 10, 10
195	#endif
196	);
197	}
198	{
199	name = _name+"_reservation_station";
200
201	_component_reservation_station = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::reservation_station::Reservation_station (name.c_str()
202	#ifdef STATISTICS
203	,param_statistics
204	#endif
205	,_param->_param_reservation_station);
206
207	_component->set_component (_component_reservation_station->_component
208	#ifdef POSITION
209	, 50, 50, 10, 10
210	#endif
211	);
212	}
213
214	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
215	{
216	name = _name+"_read_queue";
217	std::cout << "Instance : " << name << std::endl;
218	{
219	#ifdef POSITION
220	_component->interface_map (name ,"",
221	_name,"");
222	#endif
223
224	_component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
225	_component->port_map(name,"in_NRESET", _name, "in_NRESET");
226	}
227
228	// ~~~~~[ Interface "read_queue_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
229	{
230	std::string dest = _name;
231	#ifdef POSITION
232	_component->interface_map (name,"read_queue_in",
233	dest,"read_unit_in");
234	#endif
235
236	_component->port_map(name, "in_READ_QUEUE_IN_VAL" ,dest, "in_READ_UNIT_IN_VAL" );
237	_component->port_map(name,"out_READ_QUEUE_IN_ACK" ,dest,"out_READ_UNIT_IN_ACK" );
238	if (_param->_have_port_context_id)
239	_component->port_map(name, "in_READ_QUEUE_IN_CONTEXT_ID" ,dest, "in_READ_UNIT_IN_CONTEXT_ID" );
240	if (_param->_have_port_front_end_id)
241	_component->port_map(name, "in_READ_QUEUE_IN_FRONT_END_ID" ,dest, "in_READ_UNIT_IN_FRONT_END_ID" );
242	if (_param->_have_port_ooo_engine_id)
243	_component->port_map(name, "in_READ_QUEUE_IN_OOO_ENGINE_ID" ,dest, "in_READ_UNIT_IN_OOO_ENGINE_ID" );
244	if (_param->_have_port_packet_id)
245	_component->port_map(name, "in_READ_QUEUE_IN_ROB_ID" ,dest, "in_READ_UNIT_IN_PACKET_ID" );
246	_component->port_map(name, "in_READ_QUEUE_IN_OPERATION" ,dest, "in_READ_UNIT_IN_OPERATION" );
247	_component->port_map(name, "in_READ_QUEUE_IN_TYPE" ,dest, "in_READ_UNIT_IN_TYPE" );
248	_component->port_map(name, "in_READ_QUEUE_IN_STORE_QUEUE_PTR_WRITE",dest, "in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE");
249	if (_param->_have_port_load_queue_ptr)
250	_component->port_map(name, "in_READ_QUEUE_IN_LOAD_QUEUE_PTR_WRITE" ,dest, "in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE" );
251	_component->port_map(name, "in_READ_QUEUE_IN_HAS_IMMEDIAT" ,dest, "in_READ_UNIT_IN_HAS_IMMEDIAT" );
252	_component->port_map(name, "in_READ_QUEUE_IN_IMMEDIAT" ,dest, "in_READ_UNIT_IN_IMMEDIAT" );
253	_component->port_map(name, "in_READ_QUEUE_IN_READ_RA" ,dest, "in_READ_UNIT_IN_READ_RA" );
254	_component->port_map(name, "in_READ_QUEUE_IN_NUM_REG_RA" ,dest, "in_READ_UNIT_IN_NUM_REG_RA" );
255	_component->port_map(name, "in_READ_QUEUE_IN_READ_RB" ,dest, "in_READ_UNIT_IN_READ_RB" );
256	_component->port_map(name, "in_READ_QUEUE_IN_NUM_REG_RB" ,dest, "in_READ_UNIT_IN_NUM_REG_RB" );
257	_component->port_map(name, "in_READ_QUEUE_IN_READ_RC" ,dest, "in_READ_UNIT_IN_READ_RC" );
258	_component->port_map(name, "in_READ_QUEUE_IN_NUM_REG_RC" ,dest, "in_READ_UNIT_IN_NUM_REG_RC" );
259	_component->port_map(name, "in_READ_QUEUE_IN_WRITE_RD" ,dest, "in_READ_UNIT_IN_WRITE_RD" );
260	_component->port_map(name, "in_READ_QUEUE_IN_NUM_REG_RD" ,dest, "in_READ_UNIT_IN_NUM_REG_RD" );
261	_component->port_map(name, "in_READ_QUEUE_IN_WRITE_RE" ,dest, "in_READ_UNIT_IN_WRITE_RE" );
262	_component->port_map(name, "in_READ_QUEUE_IN_NUM_REG_RE" ,dest, "in_READ_UNIT_IN_NUM_REG_RE" );
263	}
264	// ~~~~~[ Interface "read_queue_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
265	{
266	std::string dest = _name+"_reservation_station";
267
268	#ifdef POSITION
269	_component->interface_map (name,"read_queue_in",
270	dest,"insert");
271	#endif
272
273	_component->port_map(name,"out_READ_QUEUE_OUT_VAL" ,dest, "in_INSERT_VAL" );
274	_component->port_map(name, "in_READ_QUEUE_OUT_ACK" ,dest,"out_INSERT_ACK" );
275	if (_param->_have_port_context_id)
276	_component->port_map(name,"out_READ_QUEUE_OUT_CONTEXT_ID" ,dest, "in_INSERT_CONTEXT_ID" );
277	if (_param->_have_port_front_end_id)
278	_component->port_map(name,"out_READ_QUEUE_OUT_FRONT_END_ID" ,dest, "in_INSERT_FRONT_END_ID" );
279	if (_param->_have_port_ooo_engine_id)
280	_component->port_map(name,"out_READ_QUEUE_OUT_OOO_ENGINE_ID" ,dest, "in_INSERT_OOO_ENGINE_ID" );
281	if (_param->_have_port_packet_id)
282	_component->port_map(name,"out_READ_QUEUE_OUT_ROB_ID" ,dest, "in_INSERT_ROB_ID" );
283	_component->port_map(name,"out_READ_QUEUE_OUT_OPERATION" ,dest, "in_INSERT_OPERATION" );
284	_component->port_map(name,"out_READ_QUEUE_OUT_TYPE" ,dest, "in_INSERT_TYPE" );
285	_component->port_map(name,"out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE",dest, "in_INSERT_STORE_QUEUE_PTR_WRITE");
286	if (_param->_have_port_load_queue_ptr)
287	_component->port_map(name,"out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE" ,dest, "in_INSERT_LOAD_QUEUE_PTR_WRITE" );
288	_component->port_map(name,"out_READ_QUEUE_OUT_HAS_IMMEDIAT" ,dest, "in_INSERT_HAS_IMMEDIAT" );
289	_component->port_map(name,"out_READ_QUEUE_OUT_IMMEDIAT" ,dest, "in_INSERT_IMMEDIAT" );
290	// _component->port_map(name,"out_READ_QUEUE_OUT_READ_RA" ,dest, "in_INSERT_READ_RA" );
291	_component->port_map(name,"out_READ_QUEUE_OUT_NUM_REG_RA" ,dest, "in_INSERT_NUM_REG_RA" );
292	_component->port_map(name,"out_READ_QUEUE_OUT_DATA_RA_VAL" ,dest, "in_INSERT_DATA_RA_VAL" );
293	_component->port_map(name,"out_READ_QUEUE_OUT_DATA_RA" ,dest, "in_INSERT_DATA_RA" );
294	// _component->port_map(name,"out_READ_QUEUE_OUT_READ_RB" ,dest, "in_INSERT_READ_RB" );
295	_component->port_map(name,"out_READ_QUEUE_OUT_NUM_REG_RB" ,dest, "in_INSERT_NUM_REG_RB" );
296	_component->port_map(name,"out_READ_QUEUE_OUT_DATA_RB_VAL" ,dest, "in_INSERT_DATA_RB_VAL" );
297	_component->port_map(name,"out_READ_QUEUE_OUT_DATA_RB" ,dest, "in_INSERT_DATA_RB" );
298	// _component->port_map(name,"out_READ_QUEUE_OUT_READ_RC" ,dest, "in_INSERT_READ_RC" );
299	_component->port_map(name,"out_READ_QUEUE_OUT_NUM_REG_RC" ,dest, "in_INSERT_NUM_REG_RC" );
300	_component->port_map(name,"out_READ_QUEUE_OUT_DATA_RC_VAL" ,dest, "in_INSERT_DATA_RC_VAL" );
301	_component->port_map(name,"out_READ_QUEUE_OUT_DATA_RC" ,dest, "in_INSERT_DATA_RC" );
302	_component->port_map(name,"out_READ_QUEUE_OUT_WRITE_RD" ,dest, "in_INSERT_WRITE_RD" );
303	_component->port_map(name,"out_READ_QUEUE_OUT_NUM_REG_RD" ,dest, "in_INSERT_NUM_REG_RD" );
304	_component->port_map(name,"out_READ_QUEUE_OUT_WRITE_RE" ,dest, "in_INSERT_WRITE_RE" );
305	_component->port_map(name,"out_READ_QUEUE_OUT_NUM_REG_RE" ,dest, "in_INSERT_NUM_REG_RE" );
306	}
307	// ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
308	for (uint32_t i=0; i<_param->_nb_gpr_read; i++)
309	{
310	std::string dest = _name;
311	#ifdef POSITION
312	_component->interface_map (name,"gpr_read_"+toString(i),
313	dest,"gpr_read_"+toString(i));
314	#endif
315
316	_component->port_map(name,"out_GPR_READ_"+toString(i)+"_VAL" ,dest,"out_GPR_READ_"+toString(i)+"_VAL" );
317	_component->port_map(name, "in_GPR_READ_"+toString(i)+"_ACK" ,dest, "in_GPR_READ_"+toString(i)+"_ACK" );
318	if (_param->_have_port_ooo_engine_id)
319	_component->port_map(name,"out_GPR_READ_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_GPR_READ_"+toString(i)+"_OOO_ENGINE_ID");
320	_component->port_map(name,"out_GPR_READ_"+toString(i)+"_NUM_REG" ,dest,"out_GPR_READ_"+toString(i)+"_NUM_REG" );
321	_component->port_map(name, "in_GPR_READ_"+toString(i)+"_DATA" ,dest, "in_GPR_READ_"+toString(i)+"_DATA" );
322	_component->port_map(name, "in_GPR_READ_"+toString(i)+"_DATA_VAL" ,dest, "in_GPR_READ_"+toString(i)+"_DATA_VAL" );
323	}
324
325	// ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
326	for (uint32_t i=0; i<_param->_nb_spr_read; i++)
327	{
328	std::string dest = _name;
329	#ifdef POSITION
330	_component->interface_map (name,"spr_read_"+toString(i),
331	dest,"spr_read_"+toString(i));
332	#endif
333
334	_component->port_map(name,"out_SPR_READ_"+toString(i)+"_VAL" ,dest,"out_SPR_READ_"+toString(i)+"_VAL" );
335	_component->port_map(name, "in_SPR_READ_"+toString(i)+"_ACK" ,dest, "in_SPR_READ_"+toString(i)+"_ACK" );
336	if (_param->_have_port_ooo_engine_id)
337	_component->port_map(name,"out_SPR_READ_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_SPR_READ_"+toString(i)+"_OOO_ENGINE_ID");
338	_component->port_map(name,"out_SPR_READ_"+toString(i)+"_NUM_REG" ,dest,"out_SPR_READ_"+toString(i)+"_NUM_REG" );
339	_component->port_map(name, "in_SPR_READ_"+toString(i)+"_DATA" ,dest, "in_SPR_READ_"+toString(i)+"_DATA" );
340	_component->port_map(name, "in_SPR_READ_"+toString(i)+"_DATA_VAL" ,dest, "in_SPR_READ_"+toString(i)+"_DATA_VAL" );
341	}
342
343	// ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
344	for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
345	{
346	std::string dest = _name;
347	#ifdef POSITION
348	_component->interface_map (name,"gpr_write_"+toString(i),
349	dest,"gpr_write_"+toString(i));
350	#endif
351
352	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_VAL" ,dest, "in_GPR_WRITE_"+toString(i)+"_VAL" );
353	if (_param->_have_port_ooo_engine_id)
354	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest, "in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
355	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_NUM_REG" ,dest, "in_GPR_WRITE_"+toString(i)+"_NUM_REG" );
356	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_DATA" ,dest, "in_GPR_WRITE_"+toString(i)+"_DATA" );
357	}
358	// ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
359	for (uint32_t i=0; i<_param->_nb_spr_write; i++)
360	{
361	std::string dest = _name;
362	#ifdef POSITION
363	_component->interface_map (name,"spr_write_"+toString(i),
364	dest,"spr_write_"+toString(i));
365	#endif
366
367	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_VAL" ,dest, "in_SPR_WRITE_"+toString(i)+"_VAL" );
368	if (_param->_have_port_ooo_engine_id)
369	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest, "in_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
370	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_NUM_REG" ,dest, "in_SPR_WRITE_"+toString(i)+"_NUM_REG" );
371	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_DATA" ,dest, "in_SPR_WRITE_"+toString(i)+"_DATA" );
372	}
373	}
374
375	{
376	name = _name+"_reservation_station";
377	std::cout << "Instance : " << name << std::endl;
378	{
379	#ifdef POSITION
380	_component->interface_map (name ,"",
381	_name,"");
382	#endif
383
384	_component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
385	_component->port_map(name,"in_NRESET", _name, "in_NRESET");
386	}
387
388	// ~~~~~[ Interface "insert" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
389	{
390	std::string dest = _name+"_read_queue";
391
392	#ifdef POSITION
393	_component->interface_map (name,"insert",
394	dest,"read_queue_in");
395	#endif
396
397	_component->port_map(name, "in_INSERT_VAL" ,dest,"out_READ_QUEUE_OUT_VAL" );
398	_component->port_map(name,"out_INSERT_ACK" ,dest, "in_READ_QUEUE_OUT_ACK" );
399	if (_param->_have_port_context_id)
400	_component->port_map(name, "in_INSERT_CONTEXT_ID" ,dest,"out_READ_QUEUE_OUT_CONTEXT_ID" );
401	if (_param->_have_port_front_end_id)
402	_component->port_map(name, "in_INSERT_FRONT_END_ID" ,dest,"out_READ_QUEUE_OUT_FRONT_END_ID" );
403	if (_param->_have_port_ooo_engine_id)
404	_component->port_map(name, "in_INSERT_OOO_ENGINE_ID" ,dest,"out_READ_QUEUE_OUT_OOO_ENGINE_ID" );
405	if (_param->_have_port_packet_id)
406	_component->port_map(name, "in_INSERT_ROB_ID" ,dest,"out_READ_QUEUE_OUT_ROB_ID" );
407	_component->port_map(name, "in_INSERT_OPERATION" ,dest,"out_READ_QUEUE_OUT_OPERATION" );
408	_component->port_map(name, "in_INSERT_TYPE" ,dest,"out_READ_QUEUE_OUT_TYPE" );
409	_component->port_map(name, "in_INSERT_STORE_QUEUE_PTR_WRITE",dest,"out_READ_QUEUE_OUT_STORE_QUEUE_PTR_WRITE");
410	if (_param->_have_port_load_queue_ptr)
411	_component->port_map(name, "in_INSERT_LOAD_QUEUE_PTR_WRITE" ,dest,"out_READ_QUEUE_OUT_LOAD_QUEUE_PTR_WRITE" );
412	_component->port_map(name, "in_INSERT_HAS_IMMEDIAT" ,dest,"out_READ_QUEUE_OUT_HAS_IMMEDIAT" );
413	_component->port_map(name, "in_INSERT_IMMEDIAT" ,dest,"out_READ_QUEUE_OUT_IMMEDIAT" );
414	// _component->port_map(name, "in_INSERT_READ_RA" ,dest,"out_READ_QUEUE_OUT_READ_RA" );
415	_component->port_map(name, "in_INSERT_NUM_REG_RA" ,dest,"out_READ_QUEUE_OUT_NUM_REG_RA" );
416	_component->port_map(name, "in_INSERT_DATA_RA_VAL" ,dest,"out_READ_QUEUE_OUT_DATA_RA_VAL" );
417	_component->port_map(name, "in_INSERT_DATA_RA" ,dest,"out_READ_QUEUE_OUT_DATA_RA" );
418	// _component->port_map(name, "in_INSERT_READ_RB" ,dest,"out_READ_QUEUE_OUT_READ_RB" );
419	_component->port_map(name, "in_INSERT_NUM_REG_RB" ,dest,"out_READ_QUEUE_OUT_NUM_REG_RB" );
420	_component->port_map(name, "in_INSERT_DATA_RB_VAL" ,dest,"out_READ_QUEUE_OUT_DATA_RB_VAL" );
421	_component->port_map(name, "in_INSERT_DATA_RB" ,dest,"out_READ_QUEUE_OUT_DATA_RB" );
422	// _component->port_map(name, "in_INSERT_READ_RC" ,dest,"out_READ_QUEUE_OUT_READ_RC" );
423	_component->port_map(name, "in_INSERT_NUM_REG_RC" ,dest,"out_READ_QUEUE_OUT_NUM_REG_RC" );
424	_component->port_map(name, "in_INSERT_DATA_RC_VAL" ,dest,"out_READ_QUEUE_OUT_DATA_RC_VAL" );
425	_component->port_map(name, "in_INSERT_DATA_RC" ,dest,"out_READ_QUEUE_OUT_DATA_RC" );
426	_component->port_map(name, "in_INSERT_WRITE_RD" ,dest,"out_READ_QUEUE_OUT_WRITE_RD" );
427	_component->port_map(name, "in_INSERT_NUM_REG_RD" ,dest,"out_READ_QUEUE_OUT_NUM_REG_RD" );
428	_component->port_map(name, "in_INSERT_WRITE_RE" ,dest,"out_READ_QUEUE_OUT_WRITE_RE" );
429	_component->port_map(name, "in_INSERT_NUM_REG_RE" ,dest,"out_READ_QUEUE_OUT_NUM_REG_RE" );
430	}
431
432	// ~~~~~[ Interface "retire" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
433	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
434	{
435	std::string dest = _name;
436
437	#ifdef POSITION
438	_component->interface_map (name,"retire_"+toString(i),
439	dest,"read_unit_out_"+toString(i));
440	#endif
441
442	_component->port_map(name,"out_RETIRE_"+toString(i)+"_VAL" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_VAL" );
443	_component->port_map(name, "in_RETIRE_"+toString(i)+"_ACK" ,dest, "in_READ_UNIT_OUT_"+toString(i)+"_ACK" );
444	if (_param->_have_port_context_id)
445	_component->port_map(name,"out_RETIRE_"+toString(i)+"_CONTEXT_ID" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" );
446	if (_param->_have_port_front_end_id)
447	_component->port_map(name,"out_RETIRE_"+toString(i)+"_FRONT_END_ID" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" );
448	if (_param->_have_port_ooo_engine_id)
449	_component->port_map(name,"out_RETIRE_"+toString(i)+"_OOO_ENGINE_ID" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID" );
450	if (_param->_have_port_packet_id)
451	_component->port_map(name,"out_RETIRE_"+toString(i)+"_ROB_ID" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_PACKET_ID" );
452	_component->port_map(name,"out_RETIRE_"+toString(i)+"_OPERATION" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_OPERATION" );
453	_component->port_map(name,"out_RETIRE_"+toString(i)+"_TYPE" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_TYPE" );
454	_component->port_map(name,"out_RETIRE_"+toString(i)+"_STORE_QUEUE_PTR_WRITE",dest,"out_READ_UNIT_OUT_"+toString(i)+"_STORE_QUEUE_PTR_WRITE");
455	if (_param->_have_port_load_queue_ptr)
456	_component->port_map(name,"out_RETIRE_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" );
457	_component->port_map(name,"out_RETIRE_"+toString(i)+"_HAS_IMMEDIAT" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_HAS_IMMEDIAT" );
458	_component->port_map(name,"out_RETIRE_"+toString(i)+"_IMMEDIAT" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_IMMEDIAT" );
459	_component->port_map(name,"out_RETIRE_"+toString(i)+"_DATA_RA" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_DATA_RA" );
460	_component->port_map(name,"out_RETIRE_"+toString(i)+"_DATA_RB" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_DATA_RB" );
461	_component->port_map(name,"out_RETIRE_"+toString(i)+"_DATA_RC" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_DATA_RC" );
462	_component->port_map(name,"out_RETIRE_"+toString(i)+"_WRITE_RD" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_WRITE_RD" );
463	_component->port_map(name,"out_RETIRE_"+toString(i)+"_NUM_REG_RD" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" );
464	_component->port_map(name,"out_RETIRE_"+toString(i)+"_WRITE_RE" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_WRITE_RE" );
465	_component->port_map(name,"out_RETIRE_"+toString(i)+"_NUM_REG_RE" ,dest,"out_READ_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" );
466	}
467
468	// ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
469	for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
470	{
471	std::string dest = _name;
472	#ifdef POSITION
473	_component->interface_map (name,"gpr_write_"+toString(i),
474	dest,"gpr_write_"+toString(i));
475	#endif
476
477	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_VAL" ,dest, "in_GPR_WRITE_"+toString(i)+"_VAL" );
478	if (_param->_have_port_ooo_engine_id)
479	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest, "in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
480	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_NUM_REG" ,dest, "in_GPR_WRITE_"+toString(i)+"_NUM_REG" );
481	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_DATA" ,dest, "in_GPR_WRITE_"+toString(i)+"_DATA" );
482	}
483	// ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
484	for (uint32_t i=0; i<_param->_nb_spr_write; i++)
485	{
486	std::string dest = _name;
487	#ifdef POSITION
488	_component->interface_map (name,"spr_write_"+toString(i),
489	dest,"spr_write_"+toString(i));
490	#endif
491
492	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_VAL" ,dest, "in_SPR_WRITE_"+toString(i)+"_VAL" );
493	if (_param->_have_port_ooo_engine_id)
494	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest, "in_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
495	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_NUM_REG" ,dest, "in_SPR_WRITE_"+toString(i)+"_NUM_REG" );
496	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_DATA" ,dest, "in_SPR_WRITE_"+toString(i)+"_DATA" );
497	}
498	// ~~~~~[ Interface "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
499	for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
500	{
501	std::string dest = _name;
502	#ifdef POSITION
503	_component->interface_map (name,"bypass_write_"+toString(i),
504	dest,"bypass_write_"+toString(i));
505	#endif
506
507	if (_param->_have_port_ooo_engine_id)
508	_component->port_map(name, "in_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest, "in_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
509	_component->port_map(name, "in_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" ,dest, "in_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" );
510	_component->port_map(name, "in_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" ,dest, "in_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" );
511	_component->port_map(name, "in_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" ,dest, "in_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" );
512	_component->port_map(name, "in_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" ,dest, "in_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" );
513	_component->port_map(name, "in_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" ,dest, "in_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" );
514	_component->port_map(name, "in_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" ,dest, "in_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" );
515	}
516	// ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
517	for (uint32_t i=0; i<_param->_nb_bypass_memory; i++)
518	{
519	std::string dest = _name;
520	#ifdef POSITION
521	_component->interface_map (name,"bypass_memory_"+toString(i),
522	dest,"bypass_memory_"+toString(i));
523	#endif
524
525	if (_param->_have_port_ooo_engine_id)
526	_component->port_map(name, "in_BYPASS_MEMORY_"+toString(i)+"_OOO_ENGINE_ID",dest, "in_BYPASS_MEMORY_"+toString(i)+"_OOO_ENGINE_ID");
527	_component->port_map(name, "in_BYPASS_MEMORY_"+toString(i)+"_VAL" ,dest, "in_BYPASS_MEMORY_"+toString(i)+"_VAL" );
528	_component->port_map(name, "in_BYPASS_MEMORY_"+toString(i)+"_NUM_REG" ,dest, "in_BYPASS_MEMORY_"+toString(i)+"_NUM_REG" );
529	_component->port_map(name, "in_BYPASS_MEMORY_"+toString(i)+"_DATA" ,dest, "in_BYPASS_MEMORY_"+toString(i)+"_DATA" );
530	}
531	}
532
533
534	#ifdef POSITION
535	_component->generate_file();
536	#endif
537
538	log_printf(FUNC,Read_unit,FUNCTION,"End");
539	};
540
541	}; // end namespace read_unit
542	}; // end namespace multi_read_unit
543	}; // end namespace execute_loop
544	}; // end namespace multi_execute_loop
545	}; // end namespace core
546
547	}; // end namespace behavioural
548	}; // end namespace morpheo

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Read_unit/Read_unit/src/Read_unit_allocation.cpp @ 78

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