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top_allocation.cpp @ 113

Last change on this file since 113 was 113, checked in by rosiere, 15 years ago
1) Add modelsim simulation systemC 2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit) 3) Add multi architecture 5) Add template for comparator, multiplier and divider 6) Change Message Warning) Various test macro have change, many selftest can't compile
Property svn:keywords set to `Id`
File size: 11.9 KB

Line
1	/*
2	* $Id: top_allocation.cpp 113 2009-04-14 18:39:12Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/include/top.h"
10	#include "Behavioural/include/Allocation.h"
11	#include "Behavioural/include/Simulation.h"
12
13	void top::allocation (void)
14	{
15	if (setlocale (LC_ALL, "") == NULL)
16	msgWarning(_("setlocale ko.\n"));
17
18	try
19	{
20	_param->test();
21	}
22	catch (morpheo::ErrorMorpheo & error)
23	{
24	msgError(_("<%s> : %s"),name.c_str(),error.what());
25	return;
26	}
27	catch (...)
28	{
29	msgError(_("<%s> : This test must generate a error"),name.c_str());
30	exit (EXIT_FAILURE);
31	}
32
33	_usage = USE_ALL;
34	// _usage = usage_unset(_usage,USE_SYSTEMC );
35	// _usage = usage_unset(_usage,USE_VHDL );
36	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
37	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
38	// _usage = usage_unset(_usage,USE_POSITION );
39	// _usage = usage_unset(_usage,USE_STATISTICS );
40	// _usage = usage_unset(_usage,USE_INFORMATION );
41
42	_model.set_model("Write_unit" ,MODEL_SYSTEMC, DEBUG_NONE);
43	_model.set_model("Write_queue" ,MODEL_SYSTEMC, DEBUG_NONE);
44	_model.set_model("Execute_queue",MODEL_VHDL , DEBUG_NONE);
45	_model.print();
46
47	#ifdef STATISTICS
48	if (usage_is_set(_usage,USE_STATISTICS))
49	_param_stat = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
50	#endif
51
52	try
53	{
54	component = new Write_unit
55	(name.c_str(),
56	#ifdef STATISTICS
57	_param_stat,
58	#endif
59	_param,
60	_usage
61	);
62	}
63	catch (morpheo::ErrorMorpheo & error)
64	{
65	msgError(_("<%s> : %s"),name.c_str(),error.what());
66	throw error;
67	}
68
69	#ifdef SYSTEMC
70	if (usage_is_set(_usage,USE_SYSTEMC))
71	{
72	/*********************************************************************
73	* Déclarations des signaux
74	*********************************************************************/
75	msgInformation(_("<%s> : Create signal.\n"),name.c_str());
76
77	in_CLOCK = new sc_clock ("clock", TIME_PERIOD, TIME_UNIT, 0.5); //name,period,time_unit,duty_cycle
78
79	ALLOC0_SC_SIGNAL( in_NRESET ," in_NRESET ",Tcontrol_t);
80
81	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_VAL ," in_WRITE_UNIT_IN_VAL" , Tcontrol_t );
82	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_IN_ACK ,"out_WRITE_UNIT_IN_ACK" , Tcontrol_t );
83	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_CONTEXT_ID ," in_WRITE_UNIT_IN_CONTEXT_ID" , Tcontext_t );
84	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_FRONT_END_ID ," in_WRITE_UNIT_IN_FRONT_END_ID" , Tcontext_t );
85	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_OOO_ENGINE_ID ," in_WRITE_UNIT_IN_OOO_ENGINE_ID" , Tcontext_t );
86	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_PACKET_ID ," in_WRITE_UNIT_IN_PACKET_ID" , Tpacket_t );
87	//ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_OPERATION ," in_WRITE_UNIT_IN_OPERATION" , Toperation_t );
88	//ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_TYPE ," in_WRITE_UNIT_IN_TYPE" , Ttype_t );
89	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_WRITE_RD ," in_WRITE_UNIT_IN_WRITE_RD" , Tcontrol_t );
90	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_NUM_REG_RD ," in_WRITE_UNIT_IN_NUM_REG_RD" , Tgeneral_address_t);
91	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_DATA_RD ," in_WRITE_UNIT_IN_DATA_RD" , Tgeneral_data_t );
92	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_WRITE_RE ," in_WRITE_UNIT_IN_WRITE_RE" , Tcontrol_t );
93	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_NUM_REG_RE ," in_WRITE_UNIT_IN_NUM_REG_RE" , Tspecial_address_t);
94	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_DATA_RE ," in_WRITE_UNIT_IN_DATA_RE" , Tspecial_data_t );
95	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_EXCEPTION ," in_WRITE_UNIT_IN_EXCEPTION" , Texception_t );
96	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_NO_SEQUENCE ," in_WRITE_UNIT_IN_NO_SEQUENCE" , Tcontrol_t );
97	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_IN_ADDRESS ," in_WRITE_UNIT_IN_ADDRESS" , Taddress_t );
98	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_VAL ,"out_WRITE_UNIT_OUT_VAL" , Tcontrol_t );
99	ALLOC0_SC_SIGNAL( in_WRITE_UNIT_OUT_ACK ," in_WRITE_UNIT_OUT_ACK" , Tcontrol_t );
100	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_CONTEXT_ID ,"out_WRITE_UNIT_OUT_CONTEXT_ID" , Tcontext_t );
101	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_FRONT_END_ID ,"out_WRITE_UNIT_OUT_FRONT_END_ID" , Tcontext_t );
102	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID", Tcontext_t );
103	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_PACKET_ID ,"out_WRITE_UNIT_OUT_PACKET_ID" , Tpacket_t );
104	//ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_OPERATION ,"out_WRITE_UNIT_OUT_OPERATION" , Toperation_t );
105	//ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_TYPE ,"out_WRITE_UNIT_OUT_TYPE" , Ttype_t );
106	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_FLAGS ,"out_WRITE_UNIT_OUT_FLAGS" , Tspecial_data_t );
107	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_EXCEPTION ,"out_WRITE_UNIT_OUT_EXCEPTION" , Texception_t );
108	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"out_WRITE_UNIT_OUT_NO_SEQUENCE" , Tcontrol_t );
109	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_ADDRESS ,"out_WRITE_UNIT_OUT_ADDRESS" , Taddress_t );
110	ALLOC0_SC_SIGNAL(out_WRITE_UNIT_OUT_DATA ,"out_WRITE_UNIT_OUT_DATA" , Tgeneral_data_t );
111	ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write);
112	ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write);
113	ALLOC1_SC_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID ,"out_GPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_gpr_write);
114	ALLOC1_SC_SIGNAL(out_GPR_WRITE_NUM_REG ,"out_GPR_WRITE_NUM_REG" , Tgeneral_address_t, _param->_nb_gpr_write);
115	ALLOC1_SC_SIGNAL(out_GPR_WRITE_DATA ,"out_GPR_WRITE_DATA" , Tgeneral_data_t , _param->_nb_gpr_write);
116	ALLOC1_SC_SIGNAL(out_SPR_WRITE_VAL ,"out_SPR_WRITE_VAL" , Tcontrol_t , _param->_nb_spr_write);
117	ALLOC1_SC_SIGNAL( in_SPR_WRITE_ACK ," in_SPR_WRITE_ACK" , Tcontrol_t , _param->_nb_spr_write);
118	ALLOC1_SC_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID ,"out_SPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_spr_write);
119	ALLOC1_SC_SIGNAL(out_SPR_WRITE_NUM_REG ,"out_SPR_WRITE_NUM_REG" , Tspecial_address_t, _param->_nb_spr_write);
120	ALLOC1_SC_SIGNAL(out_SPR_WRITE_DATA ,"out_SPR_WRITE_DATA" , Tspecial_data_t , _param->_nb_spr_write);
121	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID ,"out_BYPASS_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_bypass_write);
122	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_VAL ,"out_BYPASS_WRITE_GPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
123	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG ,"out_BYPASS_WRITE_GPR_NUM_REG" , Tgeneral_address_t, _param->_nb_bypass_write);
124	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_DATA ,"out_BYPASS_WRITE_GPR_DATA" , Tgeneral_data_t , _param->_nb_bypass_write);
125	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_VAL ,"out_BYPASS_WRITE_SPR_VAL" , Tcontrol_t , _param->_nb_bypass_write);
126	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG ,"out_BYPASS_WRITE_SPR_NUM_REG" , Tspecial_address_t, _param->_nb_bypass_write);
127	ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_DATA ,"out_BYPASS_WRITE_SPR_DATA" , Tspecial_data_t , _param->_nb_bypass_write);
128
129	/********************************************************
130	* Instanciation
131	********************************************************/
132
133	msgInformation(_("<%s> : Instanciation of _Write_unit.\n"),name.c_str());
134
135	INSTANCE0_SC_SIGNAL(component, in_CLOCK );
136	INSTANCE0_SC_SIGNAL(component, in_NRESET );
137
138	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_VAL );
139	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_IN_ACK );
140	if (_param->_have_port_context_id)
141	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_CONTEXT_ID );
142	if (_param->_have_port_front_end_id)
143	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_FRONT_END_ID );
144	if (_param->_have_port_ooo_engine_id)
145	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_OOO_ENGINE_ID );
146	if (_param->_have_port_rob_ptr)
147	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_PACKET_ID );
148	//INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_OPERATION );
149	//INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_TYPE );
150	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_WRITE_RD );
151	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_NUM_REG_RD );
152	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_DATA_RD );
153	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_WRITE_RE );
154	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_NUM_REG_RE );
155	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_DATA_RE );
156	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_EXCEPTION );
157	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_NO_SEQUENCE );
158	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_IN_ADDRESS );
159	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_VAL );
160	INSTANCE0_SC_SIGNAL(component, in_WRITE_UNIT_OUT_ACK );
161	if (_param->_have_port_context_id)
162	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_CONTEXT_ID );
163	if (_param->_have_port_front_end_id)
164	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_FRONT_END_ID );
165	if (_param->_have_port_ooo_engine_id)
166	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_OOO_ENGINE_ID);
167	if (_param->_have_port_rob_ptr)
168	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_PACKET_ID );
169	//INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_OPERATION );
170	//INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_TYPE );
171	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_FLAGS );
172	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_EXCEPTION );
173	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_NO_SEQUENCE );
174	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_ADDRESS );
175	INSTANCE0_SC_SIGNAL(component, out_WRITE_UNIT_OUT_DATA );
176	INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_VAL , _param->_nb_gpr_write);
177	INSTANCE1_SC_SIGNAL(component, in_GPR_WRITE_ACK , _param->_nb_gpr_write);
178	if (_param->_have_port_ooo_engine_id)
179	INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_OOO_ENGINE_ID , _param->_nb_gpr_write);
180	INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write);
181	INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_DATA , _param->_nb_gpr_write);
182	INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_VAL , _param->_nb_spr_write);
183	INSTANCE1_SC_SIGNAL(component, in_SPR_WRITE_ACK , _param->_nb_spr_write);
184	if (_param->_have_port_ooo_engine_id)
185	INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_OOO_ENGINE_ID , _param->_nb_spr_write);
186	INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_NUM_REG , _param->_nb_spr_write);
187	INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_DATA , _param->_nb_spr_write);
188	if (_param->_have_port_ooo_engine_id)
189	INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_OOO_ENGINE_ID , _param->_nb_bypass_write);
190	INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write);
191	INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write);
192	INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write);
193	INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write);
194	INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write);
195	INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write);
196	}
197	#endif
198	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/SelfTest/src/top_allocation.cpp @ 113

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