[73] | 1 | /* |
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| 2 | * $Id: test.cpp 81 2008-04-15 18:40:01Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/include/test.h" |
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| 10 | #include "Common/include/Test.h" |
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| 11 | #include "Common/include/BitManipulation.h" |
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| 12 | #include "Behavioural/include/Allocation.h" |
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| 13 | |
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| 14 | #define NB_ITERATION 1 |
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| 15 | #define CYCLE_MAX (128*NB_ITERATION) |
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| 16 | |
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| 17 | #define LABEL(str...) \ |
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| 18 | { \ |
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| 19 | msg (_("{%d} "),static_cast<uint32_t>(sc_simulation_time())); \ |
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| 20 | msg (str); \ |
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| 21 | msg (_("\n")); \ |
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| 22 | } while(0) |
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| 23 | |
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| 24 | #define SC_START(cycle_offset) \ |
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| 25 | do \ |
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| 26 | { \ |
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| 27 | /*cout << "SC_START (begin)" << endl;*/ \ |
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| 28 | \ |
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| 29 | uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ |
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| 30 | if (cycle_offset != 0) \ |
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| 31 | { \ |
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| 32 | cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \ |
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| 33 | } \ |
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| 34 | \ |
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| 35 | if (cycle_current > CYCLE_MAX) \ |
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| 36 | { \ |
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| 37 | TEST_KO("Maximal cycles Reached"); \ |
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| 38 | } \ |
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| 39 | \ |
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| 40 | sc_start(cycle_offset); \ |
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| 41 | \ |
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| 42 | /*cout << "SC_START (end )" << endl;*/ \ |
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| 43 | } while(0) |
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| 44 | |
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| 45 | class entry_t |
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| 46 | { |
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| 47 | public : Tcontext_t _context_id ; |
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| 48 | public : Tcontext_t _front_end_id ; |
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| 49 | public : Tcontext_t _ooo_engine_id; |
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| 50 | public : Tpacket_t _packet_id ; |
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| 51 | //public : Toperation_t _operation ; |
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[77] | 52 | public : Ttype_t _type ; |
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[73] | 53 | public : Tcontrol_t _write_rd ; |
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| 54 | public : Tgeneral_address_t _num_reg_rd ; |
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| 55 | public : Tgeneral_data_t _data_rd ; |
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| 56 | public : Tcontrol_t _write_re ; |
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| 57 | public : Tspecial_address_t _num_reg_re ; |
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| 58 | public : Tspecial_data_t _data_re ; |
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| 59 | public : Texception_t _exception ; |
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| 60 | public : Tcontrol_t _no_sequence ; |
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| 61 | public : Tgeneral_data_t _address ; |
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| 62 | |
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| 63 | public : entry_t (Tcontext_t context_id , |
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| 64 | Tcontext_t front_end_id , |
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| 65 | Tcontext_t ooo_engine_id, |
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| 66 | Tpacket_t packet_id , |
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| 67 | //Toperation_t operation , |
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[77] | 68 | Ttype_t type , |
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[73] | 69 | Tcontrol_t write_rd , |
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| 70 | Tgeneral_address_t num_reg_rd , |
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| 71 | Tgeneral_data_t data_rd , |
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| 72 | Tcontrol_t write_re , |
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| 73 | Tspecial_address_t num_reg_re , |
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| 74 | Tspecial_data_t data_re , |
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| 75 | Texception_t exception , |
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| 76 | Tcontrol_t no_sequence , |
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| 77 | Tgeneral_data_t address ) |
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| 78 | { |
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| 79 | _context_id = context_id ; |
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| 80 | _front_end_id = front_end_id ; |
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| 81 | _ooo_engine_id = ooo_engine_id; |
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| 82 | _packet_id = packet_id ; |
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| 83 | //_operation = operation ; |
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[77] | 84 | _type = type ; |
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[73] | 85 | _write_rd = write_rd ; |
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| 86 | _num_reg_rd = num_reg_rd ; |
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| 87 | _data_rd = data_rd ; |
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| 88 | _write_re = write_re ; |
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| 89 | _num_reg_re = num_reg_re ; |
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| 90 | _data_re = data_re ; |
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| 91 | _exception = exception ; |
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| 92 | _no_sequence = no_sequence ; |
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| 93 | _address = address ; |
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| 94 | }; |
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| 95 | |
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| 96 | friend std::ostream& operator<< (std::ostream& output_stream, |
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| 97 | entry_t & x) |
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| 98 | { |
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| 99 | output_stream << " * _context_id : " << toString(x._context_id ) << std::endl |
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| 100 | << " * _front_end_id : " << toString(x._front_end_id ) << std::endl |
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| 101 | << " * _ooo_engine_id : " << toString(x._ooo_engine_id) << std::endl |
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| 102 | << " * _packet_id : " << toString(x._packet_id ) << std::endl |
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| 103 | //<< " * _operation : " << toString(x._operation ) << std::endl |
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[77] | 104 | << " * _type : " << toString(x._type ) << std::endl |
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[73] | 105 | << " * _write_rd : " << toString(x._write_rd ) << std::endl |
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| 106 | << " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl |
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| 107 | << " * _data_rd : " << toString(x._data_rd ) << std::endl |
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| 108 | << " * _write_re : " << toString(x._write_re ) << std::endl |
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| 109 | << " * _num_reg_re : " << toString(x._num_reg_re ) << std::endl |
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| 110 | << " * _data_re : " << toString(x._data_re ) << std::endl |
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| 111 | << " * _exception : " << toString(x._exception ) << std::endl |
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| 112 | << " * _no_sequence : " << toString(x._no_sequence ) << std::endl |
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| 113 | << " * _address : " << toString(x._address ) << std::endl; |
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| 114 | |
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| 115 | return output_stream; |
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| 116 | } |
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| 117 | }; |
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| 118 | |
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| 119 | void test (string name, |
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| 120 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Parameters * _param) |
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| 121 | { |
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| 122 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 123 | |
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| 124 | #ifdef STATISTICS |
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| 125 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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| 126 | #endif |
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| 127 | |
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| 128 | |
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| 129 | Write_queue * _Write_queue = new Write_queue (name.c_str(), |
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| 130 | #ifdef STATISTICS |
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| 131 | _parameters_statistics, |
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| 132 | #endif |
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| 133 | _param); |
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| 134 | |
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| 135 | #ifdef SYSTEMC |
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| 136 | /********************************************************************* |
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| 137 | * Déclarations des signaux |
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| 138 | *********************************************************************/ |
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| 139 | string rename; |
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| 140 | |
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| 141 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 142 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 143 | |
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| 144 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_VAL ," in_WRITE_QUEUE_IN_VAL" , Tcontrol_t ); |
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| 145 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_IN_ACK ,"out_WRITE_QUEUE_IN_ACK" , Tcontrol_t ); |
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| 146 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_CONTEXT_ID ," in_WRITE_QUEUE_IN_CONTEXT_ID" , Tcontext_t ); |
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| 147 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_FRONT_END_ID ," in_WRITE_QUEUE_IN_FRONT_END_ID" , Tcontext_t ); |
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| 148 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OOO_ENGINE_ID ," in_WRITE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t ); |
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| 149 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t ); |
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| 150 | //ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t ); |
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[77] | 151 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t ); |
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[73] | 152 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t ); |
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| 153 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t); |
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| 154 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_DATA_RD ," in_WRITE_QUEUE_IN_DATA_RD" , Tgeneral_data_t ); |
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| 155 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_WRITE_RE ," in_WRITE_QUEUE_IN_WRITE_RE" , Tcontrol_t ); |
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| 156 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NUM_REG_RE ," in_WRITE_QUEUE_IN_NUM_REG_RE" , Tspecial_address_t); |
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| 157 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_DATA_RE ," in_WRITE_QUEUE_IN_DATA_RE" , Tspecial_data_t ); |
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| 158 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t ); |
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| 159 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); |
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| 160 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Tgeneral_data_t ); |
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| 161 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t ); |
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| 162 | ALLOC_SC_SIGNAL ( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t ); |
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| 163 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_CONTEXT_ID ,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , Tcontext_t ); |
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| 164 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_FRONT_END_ID ,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t ); |
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| 165 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t ); |
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| 166 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_PACKET_ID ,"out_WRITE_QUEUE_OUT_PACKET_ID" , Tpacket_t ); |
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| 167 | //ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_OPERATION ,"out_WRITE_QUEUE_OUT_OPERATION" , Toperation_t ); |
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| 168 | //ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_TYPE ,"out_WRITE_QUEUE_OUT_TYPE" , Ttype_t ); |
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| 169 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_FLAGS ,"out_WRITE_QUEUE_OUT_FLAGS" , Tspecial_data_t ); |
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| 170 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_EXCEPTION ,"out_WRITE_QUEUE_OUT_EXCEPTION" , Texception_t ); |
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| 171 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); |
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| 172 | ALLOC_SC_SIGNAL (out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); |
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| 173 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); |
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| 174 | ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); |
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| 175 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID ,"out_GPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_gpr_write); |
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| 176 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_NUM_REG ,"out_GPR_WRITE_NUM_REG" , Tgeneral_address_t, _param->_nb_gpr_write); |
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| 177 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_DATA ,"out_GPR_WRITE_DATA" , Tgeneral_data_t , _param->_nb_gpr_write); |
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| 178 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_VAL ,"out_SPR_WRITE_VAL" , Tcontrol_t , _param->_nb_spr_write); |
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| 179 | ALLOC1_SC_SIGNAL( in_SPR_WRITE_ACK ," in_SPR_WRITE_ACK" , Tcontrol_t , _param->_nb_spr_write); |
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| 180 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID ,"out_SPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_spr_write); |
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| 181 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_NUM_REG ,"out_SPR_WRITE_NUM_REG" , Tspecial_address_t, _param->_nb_spr_write); |
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| 182 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_DATA ,"out_SPR_WRITE_DATA" , Tspecial_data_t , _param->_nb_spr_write); |
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| 183 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID ,"out_BYPASS_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_bypass_write); |
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| 184 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_VAL ,"out_BYPASS_WRITE_GPR_VAL" , Tcontrol_t , _param->_nb_bypass_write); |
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| 185 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG ,"out_BYPASS_WRITE_GPR_NUM_REG" , Tgeneral_address_t, _param->_nb_bypass_write); |
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| 186 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_DATA ,"out_BYPASS_WRITE_GPR_DATA" , Tgeneral_data_t , _param->_nb_bypass_write); |
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| 187 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_VAL ,"out_BYPASS_WRITE_SPR_VAL" , Tcontrol_t , _param->_nb_bypass_write); |
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| 188 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG ,"out_BYPASS_WRITE_SPR_NUM_REG" , Tspecial_address_t, _param->_nb_bypass_write); |
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| 189 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_DATA ,"out_BYPASS_WRITE_SPR_DATA" , Tspecial_data_t , _param->_nb_bypass_write); |
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| 190 | |
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| 191 | /******************************************************** |
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| 192 | * Instanciation |
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| 193 | ********************************************************/ |
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| 194 | |
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| 195 | msg(_("<%s> : Instanciation of _Write_queue.\n"),name.c_str()); |
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| 196 | |
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| 197 | (*(_Write_queue->in_CLOCK)) (*(in_CLOCK)); |
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| 198 | (*(_Write_queue->in_NRESET)) (*(in_NRESET)); |
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| 199 | |
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| 200 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_VAL ); |
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| 201 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_IN_ACK ); |
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| 202 | if (_param->_have_port_context_id) |
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| 203 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_CONTEXT_ID ); |
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| 204 | if (_param->_have_port_front_end_id) |
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| 205 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_FRONT_END_ID ); |
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| 206 | if (_param->_have_port_ooo_engine_id) |
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| 207 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OOO_ENGINE_ID ); |
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| 208 | if (_param->_have_port_packet_id) |
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| 209 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID ); |
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| 210 | //INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_OPERATION ); |
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[77] | 211 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_TYPE ); |
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[73] | 212 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RD ); |
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| 213 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RD ); |
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| 214 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_DATA_RD ); |
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| 215 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_WRITE_RE ); |
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| 216 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RE ); |
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| 217 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_DATA_RE ); |
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| 218 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_EXCEPTION ); |
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| 219 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_NO_SEQUENCE ); |
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| 220 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_IN_ADDRESS ); |
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| 221 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_VAL ); |
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| 222 | INSTANCE_SC_SIGNAL (_Write_queue, in_WRITE_QUEUE_OUT_ACK ); |
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| 223 | if (_param->_have_port_context_id) |
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| 224 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_CONTEXT_ID ); |
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| 225 | if (_param->_have_port_front_end_id) |
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| 226 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_FRONT_END_ID ); |
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| 227 | if (_param->_have_port_ooo_engine_id) |
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| 228 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OOO_ENGINE_ID); |
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| 229 | if (_param->_have_port_packet_id) |
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| 230 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_PACKET_ID ); |
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| 231 | //INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_OPERATION ); |
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| 232 | //INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_TYPE ); |
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| 233 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_FLAGS ); |
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| 234 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_EXCEPTION ); |
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| 235 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_NO_SEQUENCE ); |
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| 236 | INSTANCE_SC_SIGNAL (_Write_queue, out_WRITE_QUEUE_OUT_ADDRESS ); |
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| 237 | INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_VAL , _param->_nb_gpr_write); |
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| 238 | INSTANCE1_SC_SIGNAL(_Write_queue, in_GPR_WRITE_ACK , _param->_nb_gpr_write); |
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| 239 | if (_param->_have_port_ooo_engine_id) |
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| 240 | INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_OOO_ENGINE_ID , _param->_nb_gpr_write); |
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| 241 | INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write); |
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| 242 | INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_DATA , _param->_nb_gpr_write); |
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| 243 | INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_VAL , _param->_nb_spr_write); |
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| 244 | INSTANCE1_SC_SIGNAL(_Write_queue, in_SPR_WRITE_ACK , _param->_nb_spr_write); |
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| 245 | if (_param->_have_port_ooo_engine_id) |
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| 246 | INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_OOO_ENGINE_ID , _param->_nb_spr_write); |
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| 247 | INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_NUM_REG , _param->_nb_spr_write); |
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| 248 | INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_DATA , _param->_nb_spr_write); |
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| 249 | if (_param->_have_port_ooo_engine_id) |
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| 250 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_OOO_ENGINE_ID , _param->_nb_bypass_write); |
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| 251 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write); |
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| 252 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write); |
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| 253 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write); |
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| 254 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write); |
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| 255 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write); |
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| 256 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write); |
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| 257 | |
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| 258 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 259 | |
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| 260 | Time * _time = new Time(); |
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| 261 | |
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| 262 | /******************************************************** |
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| 263 | * Simulation - Begin |
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| 264 | ********************************************************/ |
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| 265 | |
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| 266 | // Initialisation |
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| 267 | |
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| 268 | const uint32_t seed = 0; |
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| 269 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 270 | |
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| 271 | srand(seed); |
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| 272 | |
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| 273 | const int32_t percent_transaction_write_queue_in = 75; |
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| 274 | const int32_t percent_transaction_write_queue_out = 75; |
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| 275 | const int32_t percent_transaction_gpr = 75; |
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| 276 | const int32_t percent_transaction_spr = 75; |
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| 277 | |
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| 278 | bool gpr_val [_param->_nb_ooo_engine][_param->_nb_general_register]; |
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| 279 | bool gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register]; |
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| 280 | Tgeneral_data_t gpr [_param->_nb_ooo_engine][_param->_nb_general_register]; |
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| 281 | bool spr_val [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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| 282 | bool spr_use [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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| 283 | Tgeneral_data_t spr [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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| 284 | |
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| 285 | entry_t * request [_param->_nb_packet]; |
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| 286 | |
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| 287 | SC_START(0); |
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| 288 | LABEL("Initialisation"); |
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| 289 | |
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| 290 | LABEL("Reset"); |
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| 291 | in_NRESET->write(0); |
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| 292 | SC_START(5); |
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| 293 | in_NRESET->write(1); |
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| 294 | |
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| 295 | LABEL("Loop of Test"); |
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| 296 | |
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| 297 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 298 | { |
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| 299 | LABEL("Iteration %d",iteration); |
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| 300 | |
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| 301 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
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| 302 | { |
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| 303 | for (uint32_t j=0; j<_param->_nb_general_register; j++) |
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| 304 | { |
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| 305 | gpr_val [i][j] = 0; |
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| 306 | gpr_use [i][j] = 0; |
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| 307 | gpr [i][j] = rand(); |
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| 308 | } |
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| 309 | for (uint32_t j=0; j<_param->_nb_special_register; j++) |
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| 310 | { |
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| 311 | spr_val [i][j] = 0; |
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| 312 | spr_use [i][j] = 0; |
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| 313 | spr [i][j] = rand(); |
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| 314 | } |
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| 315 | } |
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| 316 | |
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| 317 | for (uint32_t i=0; i<_param->_nb_packet; i++) |
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| 318 | { |
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| 319 | request [i] = new entry_t (range<Tcontext_t >(rand(),_param->_size_context_id ), |
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| 320 | range<Tcontext_t >(rand(),_param->_size_front_end_id ), |
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| 321 | range<Tcontext_t >(rand(),_param->_size_ooo_engine_id ), |
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| 322 | i, |
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| 323 | //range<Toperation_t >(rand(),_param->_size_operation ), |
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[77] | 324 | range<Ttype_t >(rand(),_param->_size_type ), |
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[73] | 325 | range<Tcontrol_t >(rand(),1 ), |
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| 326 | range<Tgeneral_address_t>(rand(),_param->_size_general_register), |
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| 327 | range<Tgeneral_data_t >(rand(),_param->_size_general_data ), |
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| 328 | range<Tcontrol_t >(rand(),1 ), |
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| 329 | range<Tspecial_address_t>(rand(),_param->_size_special_register), |
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| 330 | range<Tspecial_data_t >(rand(),_param->_size_special_data ), |
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| 331 | range<Texception_t >(rand(),_param->_size_exception ), |
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| 332 | range<Tcontrol_t >(rand(),1 ), |
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| 333 | range<Tgeneral_data_t >(rand(),_param->_size_general_data )); |
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| 334 | } |
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| 335 | |
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| 336 | uint32_t nb_request_in = 0; |
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| 337 | uint32_t nb_request_out = 0; |
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| 338 | |
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| 339 | while (nb_request_out < _param->_nb_packet) |
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| 340 | { |
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| 341 | bool val = (((rand()%100)<percent_transaction_write_queue_in) and |
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| 342 | (nb_request_in < _param->_nb_packet) and |
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| 343 | not (request [nb_request_in]->_write_rd and |
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| 344 | gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd]) and |
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| 345 | not (request [nb_request_in]->_write_re and |
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| 346 | spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re])); |
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| 347 | |
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| 348 | in_WRITE_QUEUE_IN_VAL ->write(val); |
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| 349 | if (val) |
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| 350 | { |
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| 351 | in_WRITE_QUEUE_IN_CONTEXT_ID ->write(request [nb_request_in]->_context_id ); |
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| 352 | in_WRITE_QUEUE_IN_FRONT_END_ID ->write(request [nb_request_in]->_front_end_id ); |
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| 353 | in_WRITE_QUEUE_IN_OOO_ENGINE_ID->write(request [nb_request_in]->_ooo_engine_id); |
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| 354 | in_WRITE_QUEUE_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id ); |
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| 355 | //in_WRITE_QUEUE_IN_OPERATION ->write(request [nb_request_in]->_operation ); |
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[77] | 356 | in_WRITE_QUEUE_IN_TYPE ->write(request [nb_request_in]->_type ); |
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[73] | 357 | in_WRITE_QUEUE_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd ); |
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| 358 | in_WRITE_QUEUE_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd ); |
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| 359 | in_WRITE_QUEUE_IN_DATA_RD ->write(request [nb_request_in]->_data_rd ); |
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| 360 | in_WRITE_QUEUE_IN_WRITE_RE ->write(request [nb_request_in]->_write_re ); |
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| 361 | in_WRITE_QUEUE_IN_NUM_REG_RE ->write(request [nb_request_in]->_num_reg_re ); |
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| 362 | in_WRITE_QUEUE_IN_DATA_RE ->write(request [nb_request_in]->_data_re ); |
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| 363 | in_WRITE_QUEUE_IN_EXCEPTION ->write(request [nb_request_in]->_exception ); |
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| 364 | in_WRITE_QUEUE_IN_NO_SEQUENCE ->write(request [nb_request_in]->_no_sequence ); |
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| 365 | in_WRITE_QUEUE_IN_ADDRESS ->write(request [nb_request_in]->_address ); |
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| 366 | } |
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| 367 | in_WRITE_QUEUE_OUT_ACK ->write((rand()%100)<percent_transaction_write_queue_out); |
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| 368 | in_GPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_gpr); |
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| 369 | in_SPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_spr); |
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| 370 | |
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| 371 | SC_START(0); |
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| 372 | |
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| 373 | // ====================================================================== |
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| 374 | // ====================================================================== |
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| 375 | // ====================================================================== |
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| 376 | if (out_GPR_WRITE_VAL [0]->read() and |
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| 377 | in_GPR_WRITE_ACK [0]->read()) |
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| 378 | { |
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| 379 | Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_GPR_WRITE_OOO_ENGINE_ID[0]->read():0; |
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| 380 | Tgeneral_address_t num_reg = out_GPR_WRITE_NUM_REG [0]->read(); |
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| 381 | Tgeneral_data_t data = out_GPR_WRITE_DATA [0]->read(); |
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| 382 | |
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| 383 | LABEL(" * Accepted GPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg); |
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| 384 | |
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| 385 | TEST(bool , gpr_val [ooo_engine_id][num_reg], 0); |
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| 386 | TEST(bool , gpr_use [ooo_engine_id][num_reg], 1); |
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| 387 | TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data); |
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| 388 | |
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| 389 | gpr_val [ooo_engine_id][num_reg] = 1; |
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| 390 | } |
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| 391 | |
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| 392 | // ====================================================================== |
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| 393 | // ====================================================================== |
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| 394 | // ====================================================================== |
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| 395 | if (out_SPR_WRITE_VAL [0]->read() and |
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| 396 | in_SPR_WRITE_ACK [0]->read()) |
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| 397 | { |
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| 398 | Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_SPR_WRITE_OOO_ENGINE_ID[0]->read():0; |
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| 399 | Tspecial_address_t num_reg = out_SPR_WRITE_NUM_REG [0]->read(); |
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| 400 | Tspecial_data_t data = out_SPR_WRITE_DATA [0]->read(); |
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| 401 | |
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| 402 | LABEL(" * Accepted SPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg); |
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| 403 | |
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| 404 | TEST(bool , spr_val [ooo_engine_id][num_reg], 0); |
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| 405 | TEST(bool , spr_use [ooo_engine_id][num_reg], 1); |
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| 406 | TEST(Tgeneral_data_t, spr [ooo_engine_id][num_reg], data); |
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| 407 | |
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| 408 | spr_val [ooo_engine_id][num_reg] = 1; |
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| 409 | } |
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| 410 | |
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| 411 | // ====================================================================== |
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| 412 | // ====================================================================== |
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| 413 | // ====================================================================== |
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| 414 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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| 415 | { |
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| 416 | Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_BYPASS_WRITE_OOO_ENGINE_ID[i]->read():0; |
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| 417 | |
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| 418 | if (out_BYPASS_WRITE_GPR_VAL [i]->read()) |
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| 419 | { |
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| 420 | Tgeneral_address_t num_reg = out_BYPASS_WRITE_GPR_NUM_REG [i]->read(); // RD |
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| 421 | Tgeneral_data_t data = out_BYPASS_WRITE_GPR_DATA [i]->read(); |
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| 422 | |
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| 423 | LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (GPR)", ooo_engine_id,num_reg); |
---|
| 424 | |
---|
| 425 | |
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| 426 | TEST(bool , gpr_use [ooo_engine_id][num_reg], 1); |
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| 427 | TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data); |
---|
| 428 | } |
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| 429 | if (out_BYPASS_WRITE_SPR_VAL [i]->read()) |
---|
| 430 | { |
---|
| 431 | Tspecial_address_t num_reg = out_BYPASS_WRITE_SPR_NUM_REG [i]->read(); // RE |
---|
| 432 | Tspecial_data_t data = out_BYPASS_WRITE_SPR_DATA [i]->read(); |
---|
| 433 | |
---|
| 434 | LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (SPR)", ooo_engine_id,num_reg); |
---|
| 435 | |
---|
| 436 | TEST(bool , spr_use [ooo_engine_id][num_reg], 1); |
---|
| 437 | TEST(Tspecial_data_t, spr [ooo_engine_id][num_reg], data); |
---|
| 438 | } |
---|
| 439 | } |
---|
| 440 | |
---|
| 441 | // ====================================================================== |
---|
| 442 | // ====================================================================== |
---|
| 443 | // ====================================================================== |
---|
| 444 | if ( in_WRITE_QUEUE_IN_VAL->read() and |
---|
| 445 | out_WRITE_QUEUE_IN_ACK->read()) |
---|
| 446 | { |
---|
| 447 | LABEL(" * Accepted WRITE_QUEUE_IN [%d]",nb_request_in); |
---|
| 448 | // std::cout << *request [nb_request_in] << std::endl; |
---|
| 449 | |
---|
| 450 | if (request [nb_request_in]->_write_rd) |
---|
| 451 | { |
---|
| 452 | gpr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 0; |
---|
| 453 | gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 1; |
---|
| 454 | gpr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = request [nb_request_in]->_data_rd; |
---|
| 455 | } |
---|
| 456 | if (request [nb_request_in]->_write_re) |
---|
| 457 | { |
---|
| 458 | spr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 0; |
---|
| 459 | spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 1; |
---|
| 460 | spr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = request [nb_request_in]->_data_re; |
---|
| 461 | } |
---|
| 462 | nb_request_in ++; |
---|
| 463 | } |
---|
| 464 | |
---|
| 465 | // ====================================================================== |
---|
| 466 | // ====================================================================== |
---|
| 467 | // ====================================================================== |
---|
| 468 | if (out_WRITE_QUEUE_OUT_VAL->read() and |
---|
| 469 | in_WRITE_QUEUE_OUT_ACK->read()) |
---|
| 470 | { |
---|
| 471 | Tcontext_t packet; |
---|
| 472 | if (_param->_have_port_packet_id) |
---|
| 473 | packet = out_WRITE_QUEUE_OUT_PACKET_ID->read(); |
---|
| 474 | else |
---|
| 475 | packet = 0; |
---|
| 476 | |
---|
| 477 | LABEL(" * Accepted WRITE_QUEUE_OUT [%d]",packet); |
---|
| 478 | // std::cout << *request [packet] << std::endl; |
---|
| 479 | |
---|
| 480 | if (request [packet]->_write_rd) |
---|
| 481 | { |
---|
| 482 | TEST(bool, gpr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1); |
---|
| 483 | TEST(bool, gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1); |
---|
| 484 | gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd] = 0; |
---|
| 485 | } |
---|
| 486 | if (request [packet]->_write_re) |
---|
| 487 | { |
---|
| 488 | TEST(bool, spr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1); |
---|
| 489 | TEST(bool, spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1); |
---|
| 490 | spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re] = 0; |
---|
| 491 | } |
---|
| 492 | |
---|
| 493 | if (_param->_have_port_context_id) |
---|
| 494 | TEST(Tcontext_t , out_WRITE_QUEUE_OUT_CONTEXT_ID ->read(), request [packet]->_context_id ); |
---|
| 495 | if (_param->_have_port_front_end_id) |
---|
| 496 | TEST(Tcontext_t , out_WRITE_QUEUE_OUT_FRONT_END_ID ->read(), request [packet]->_front_end_id ); |
---|
| 497 | if (_param->_have_port_ooo_engine_id) |
---|
| 498 | TEST(Tcontext_t , out_WRITE_QUEUE_OUT_OOO_ENGINE_ID->read(), request [packet]->_ooo_engine_id); |
---|
| 499 | |
---|
| 500 | //TEST(Toperation_t , out_WRITE_QUEUE_OUT_OPERATION ->read(), request [packet]->_operation ); |
---|
| 501 | //TEST(Ttype_t , out_WRITE_QUEUE_OUT_TYPE ->read(), request [packet]->_type ); |
---|
| 502 | TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_FLAGS ->read(), request [packet]->_data_re ); |
---|
| 503 | TEST(Texception_t , out_WRITE_QUEUE_OUT_EXCEPTION ->read(), request [packet]->_exception ); |
---|
| 504 | TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence ); |
---|
| 505 | TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_ADDRESS ->read(), request [packet]->_address ); |
---|
| 506 | |
---|
| 507 | nb_request_out ++; |
---|
| 508 | } |
---|
| 509 | |
---|
| 510 | SC_START(1); |
---|
| 511 | } |
---|
| 512 | |
---|
| 513 | for (uint32_t i=0; i<_param->_nb_packet; i++) |
---|
| 514 | delete request [i]; |
---|
| 515 | |
---|
| 516 | } |
---|
| 517 | |
---|
| 518 | /******************************************************** |
---|
| 519 | * Simulation - End |
---|
| 520 | ********************************************************/ |
---|
| 521 | |
---|
| 522 | TEST_OK ("End of Simulation"); |
---|
| 523 | delete _time; |
---|
| 524 | |
---|
| 525 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
---|
| 526 | |
---|
| 527 | delete in_CLOCK; |
---|
| 528 | delete in_NRESET; |
---|
| 529 | |
---|
| 530 | delete in_WRITE_QUEUE_IN_VAL ; |
---|
| 531 | delete out_WRITE_QUEUE_IN_ACK ; |
---|
| 532 | delete in_WRITE_QUEUE_IN_CONTEXT_ID ; |
---|
| 533 | delete in_WRITE_QUEUE_IN_FRONT_END_ID ; |
---|
| 534 | delete in_WRITE_QUEUE_IN_OOO_ENGINE_ID ; |
---|
| 535 | delete in_WRITE_QUEUE_IN_PACKET_ID ; |
---|
| 536 | //delete in_WRITE_QUEUE_IN_OPERATION ; |
---|
| 537 | //delete in_WRITE_QUEUE_IN_TYPE ; |
---|
| 538 | delete in_WRITE_QUEUE_IN_WRITE_RD ; |
---|
| 539 | delete in_WRITE_QUEUE_IN_NUM_REG_RD ; |
---|
| 540 | delete in_WRITE_QUEUE_IN_DATA_RD ; |
---|
| 541 | delete in_WRITE_QUEUE_IN_WRITE_RE ; |
---|
| 542 | delete in_WRITE_QUEUE_IN_NUM_REG_RE ; |
---|
| 543 | delete in_WRITE_QUEUE_IN_DATA_RE ; |
---|
| 544 | delete in_WRITE_QUEUE_IN_EXCEPTION ; |
---|
| 545 | delete in_WRITE_QUEUE_IN_NO_SEQUENCE ; |
---|
| 546 | delete in_WRITE_QUEUE_IN_ADDRESS ; |
---|
| 547 | delete out_WRITE_QUEUE_OUT_VAL ; |
---|
| 548 | delete in_WRITE_QUEUE_OUT_ACK ; |
---|
| 549 | delete out_WRITE_QUEUE_OUT_CONTEXT_ID ; |
---|
| 550 | delete out_WRITE_QUEUE_OUT_FRONT_END_ID ; |
---|
| 551 | delete out_WRITE_QUEUE_OUT_OOO_ENGINE_ID; |
---|
| 552 | delete out_WRITE_QUEUE_OUT_PACKET_ID ; |
---|
| 553 | //delete out_WRITE_QUEUE_OUT_OPERATION ; |
---|
| 554 | //delete out_WRITE_QUEUE_OUT_TYPE ; |
---|
| 555 | delete out_WRITE_QUEUE_OUT_FLAGS ; |
---|
| 556 | delete out_WRITE_QUEUE_OUT_EXCEPTION ; |
---|
| 557 | delete out_WRITE_QUEUE_OUT_NO_SEQUENCE ; |
---|
| 558 | delete out_WRITE_QUEUE_OUT_ADDRESS ; |
---|
| 559 | delete [] out_GPR_WRITE_VAL ; |
---|
| 560 | delete [] in_GPR_WRITE_ACK ; |
---|
| 561 | delete [] out_GPR_WRITE_OOO_ENGINE_ID ; |
---|
| 562 | delete [] out_GPR_WRITE_NUM_REG ; |
---|
| 563 | delete [] out_GPR_WRITE_DATA ; |
---|
| 564 | delete [] out_SPR_WRITE_VAL ; |
---|
| 565 | delete [] in_SPR_WRITE_ACK ; |
---|
| 566 | delete [] out_SPR_WRITE_OOO_ENGINE_ID ; |
---|
| 567 | delete [] out_SPR_WRITE_NUM_REG ; |
---|
| 568 | delete [] out_SPR_WRITE_DATA ; |
---|
| 569 | delete [] out_BYPASS_WRITE_OOO_ENGINE_ID ; |
---|
| 570 | delete [] out_BYPASS_WRITE_GPR_VAL ; |
---|
| 571 | delete [] out_BYPASS_WRITE_GPR_NUM_REG ; |
---|
| 572 | delete [] out_BYPASS_WRITE_GPR_DATA ; |
---|
| 573 | delete [] out_BYPASS_WRITE_SPR_VAL ; |
---|
| 574 | delete [] out_BYPASS_WRITE_SPR_NUM_REG ; |
---|
| 575 | delete [] out_BYPASS_WRITE_SPR_DATA ; |
---|
| 576 | |
---|
| 577 | #endif |
---|
| 578 | |
---|
| 579 | delete _Write_queue; |
---|
| 580 | #ifdef STATISTICS |
---|
| 581 | delete _parameters_statistics; |
---|
| 582 | #endif |
---|
| 583 | } |
---|