1 | /* |
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2 | * $Id: test.cpp 112 2009-03-18 22:36:26Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #define NB_ITERATION 1 |
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10 | #define CYCLE_MAX (1024*NB_ITERATION) |
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11 | |
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12 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/include/test.h" |
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13 | #include "Common/include/Test.h" |
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14 | #include "Common/include/BitManipulation.h" |
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15 | #include "Behavioural/include/Allocation.h" |
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16 | |
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17 | class entry_t |
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18 | { |
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19 | public : Tcontext_t _context_id ; |
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20 | public : Tcontext_t _front_end_id ; |
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21 | public : Tcontext_t _ooo_engine_id; |
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22 | public : Tpacket_t _packet_id ; |
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23 | //public : Toperation_t _operation ; |
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24 | //public : Ttype_t _type ; |
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25 | public : Tcontrol_t _write_rd ; |
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26 | public : Tgeneral_address_t _num_reg_rd ; |
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27 | public : Tgeneral_data_t _data_rd ; |
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28 | public : Tcontrol_t _write_re ; |
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29 | public : Tspecial_address_t _num_reg_re ; |
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30 | public : Tspecial_data_t _data_re ; |
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31 | public : Texception_t _exception ; |
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32 | public : Tcontrol_t _no_sequence ; |
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33 | public : Tgeneral_data_t _address ; |
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34 | |
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35 | public : entry_t (Tcontext_t context_id , |
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36 | Tcontext_t front_end_id , |
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37 | Tcontext_t ooo_engine_id, |
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38 | Tpacket_t packet_id , |
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39 | // Toperation_t operation , |
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40 | // Ttype_t type , |
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41 | Tcontrol_t write_rd , |
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42 | Tgeneral_address_t num_reg_rd , |
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43 | Tgeneral_data_t data_rd , |
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44 | Tcontrol_t write_re , |
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45 | Tspecial_address_t num_reg_re , |
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46 | Tspecial_data_t data_re , |
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47 | Texception_t exception , |
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48 | Tcontrol_t no_sequence , |
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49 | Tgeneral_data_t address ) |
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50 | { |
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51 | _context_id = context_id ; |
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52 | _front_end_id = front_end_id ; |
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53 | _ooo_engine_id = ooo_engine_id; |
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54 | _packet_id = packet_id ; |
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55 | //_operation = operation ; |
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56 | //_type = type ; |
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57 | _write_rd = write_rd ; |
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58 | _num_reg_rd = num_reg_rd ; |
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59 | _data_rd = data_rd ; |
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60 | _write_re = write_re ; |
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61 | _num_reg_re = num_reg_re ; |
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62 | _data_re = data_re ; |
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63 | _exception = exception ; |
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64 | _no_sequence = no_sequence ; |
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65 | _address = address ; |
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66 | }; |
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67 | |
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68 | friend std::ostream& operator<< (std::ostream& output_stream, |
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69 | entry_t & x) |
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70 | { |
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71 | output_stream << " * _context_id : " << toString(x._context_id ) << std::endl |
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72 | << " * _front_end_id : " << toString(x._front_end_id ) << std::endl |
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73 | << " * _ooo_engine_id : " << toString(x._ooo_engine_id) << std::endl |
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74 | << " * _packet_id : " << toString(x._packet_id ) << std::endl |
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75 | //<< " * _operation : " << toString(x._operation ) << std::endl |
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76 | //<< " * _type : " << toString(x._type ) << std::endl |
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77 | << " * _write_rd : " << toString(x._write_rd ) << std::endl |
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78 | << " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl |
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79 | << " * _data_rd : " << toString(x._data_rd ) << std::endl |
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80 | << " * _write_re : " << toString(x._write_re ) << std::endl |
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81 | << " * _num_reg_re : " << toString(x._num_reg_re ) << std::endl |
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82 | << " * _data_re : " << toString(x._data_re ) << std::endl |
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83 | << " * _exception : " << toString(x._exception ) << std::endl |
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84 | << " * _no_sequence : " << toString(x._no_sequence ) << std::endl |
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85 | << " * _address : " << toString(x._address ) << std::endl; |
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86 | |
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87 | return output_stream; |
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88 | } |
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89 | }; |
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90 | |
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91 | void test (string name, |
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92 | morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Parameters * _param) |
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93 | { |
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94 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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95 | |
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96 | #ifdef STATISTICS |
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97 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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98 | #endif |
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99 | |
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100 | Tusage_t _usage = USE_ALL; |
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101 | |
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102 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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103 | // _usage = usage_unset(_usage,USE_VHDL ); |
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104 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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105 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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106 | // _usage = usage_unset(_usage,USE_POSITION ); |
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107 | _usage = usage_unset(_usage,USE_STATISTICS ); |
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108 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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109 | |
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110 | Write_queue * _Write_queue = new Write_queue |
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111 | (name.c_str(), |
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112 | #ifdef STATISTICS |
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113 | _parameters_statistics, |
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114 | #endif |
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115 | _param, |
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116 | _usage); |
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117 | |
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118 | #ifdef SYSTEMC |
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119 | /********************************************************************* |
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120 | * Déclarations des signaux |
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121 | *********************************************************************/ |
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122 | string rename; |
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123 | |
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124 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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125 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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126 | |
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127 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_VAL ," in_WRITE_QUEUE_IN_VAL" , Tcontrol_t ); |
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128 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_IN_ACK ,"out_WRITE_QUEUE_IN_ACK" , Tcontrol_t ); |
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129 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_CONTEXT_ID ," in_WRITE_QUEUE_IN_CONTEXT_ID" , Tcontext_t ); |
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130 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_FRONT_END_ID ," in_WRITE_QUEUE_IN_FRONT_END_ID" , Tcontext_t ); |
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131 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_OOO_ENGINE_ID ," in_WRITE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t ); |
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132 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t ); |
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133 | //ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t ); |
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134 | //ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t ); |
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135 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t ); |
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136 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t); |
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137 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_DATA_RD ," in_WRITE_QUEUE_IN_DATA_RD" , Tgeneral_data_t ); |
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138 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RE ," in_WRITE_QUEUE_IN_WRITE_RE" , Tcontrol_t ); |
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139 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RE ," in_WRITE_QUEUE_IN_NUM_REG_RE" , Tspecial_address_t); |
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140 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_DATA_RE ," in_WRITE_QUEUE_IN_DATA_RE" , Tspecial_data_t ); |
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141 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t ); |
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142 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); |
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143 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Taddress_t ); |
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144 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t ); |
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145 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t ); |
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146 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_CONTEXT_ID ,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , Tcontext_t ); |
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147 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_FRONT_END_ID ,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t ); |
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148 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t ); |
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149 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_PACKET_ID ,"out_WRITE_QUEUE_OUT_PACKET_ID" , Tpacket_t ); |
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150 | //ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_OPERATION ,"out_WRITE_QUEUE_OUT_OPERATION" , Toperation_t ); |
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151 | //ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_TYPE ,"out_WRITE_QUEUE_OUT_TYPE" , Ttype_t ); |
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152 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_FLAGS ,"out_WRITE_QUEUE_OUT_FLAGS" , Tspecial_data_t ); |
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153 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_EXCEPTION ,"out_WRITE_QUEUE_OUT_EXCEPTION" , Texception_t ); |
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154 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); |
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155 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); |
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156 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Taddress_t ); |
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157 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); |
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158 | ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); |
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159 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID ,"out_GPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_gpr_write); |
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160 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_NUM_REG ,"out_GPR_WRITE_NUM_REG" , Tgeneral_address_t, _param->_nb_gpr_write); |
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161 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_DATA ,"out_GPR_WRITE_DATA" , Tgeneral_data_t , _param->_nb_gpr_write); |
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162 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_VAL ,"out_SPR_WRITE_VAL" , Tcontrol_t , _param->_nb_spr_write); |
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163 | ALLOC1_SC_SIGNAL( in_SPR_WRITE_ACK ," in_SPR_WRITE_ACK" , Tcontrol_t , _param->_nb_spr_write); |
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164 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID ,"out_SPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_spr_write); |
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165 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_NUM_REG ,"out_SPR_WRITE_NUM_REG" , Tspecial_address_t, _param->_nb_spr_write); |
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166 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_DATA ,"out_SPR_WRITE_DATA" , Tspecial_data_t , _param->_nb_spr_write); |
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167 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID ,"out_BYPASS_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_bypass_write); |
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168 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_VAL ,"out_BYPASS_WRITE_GPR_VAL" , Tcontrol_t , _param->_nb_bypass_write); |
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169 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG ,"out_BYPASS_WRITE_GPR_NUM_REG" , Tgeneral_address_t, _param->_nb_bypass_write); |
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170 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_DATA ,"out_BYPASS_WRITE_GPR_DATA" , Tgeneral_data_t , _param->_nb_bypass_write); |
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171 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_VAL ,"out_BYPASS_WRITE_SPR_VAL" , Tcontrol_t , _param->_nb_bypass_write); |
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172 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG ,"out_BYPASS_WRITE_SPR_NUM_REG" , Tspecial_address_t, _param->_nb_bypass_write); |
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173 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_DATA ,"out_BYPASS_WRITE_SPR_DATA" , Tspecial_data_t , _param->_nb_bypass_write); |
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174 | |
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175 | /******************************************************** |
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176 | * Instanciation |
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177 | ********************************************************/ |
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178 | |
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179 | msg(_("<%s> : Instanciation of _Write_queue.\n"),name.c_str()); |
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180 | |
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181 | (*(_Write_queue->in_CLOCK)) (*(in_CLOCK)); |
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182 | (*(_Write_queue->in_NRESET)) (*(in_NRESET)); |
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183 | |
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184 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_VAL ); |
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185 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_IN_ACK ); |
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186 | if (_param->_have_port_context_id) |
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187 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_CONTEXT_ID ); |
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188 | if (_param->_have_port_front_end_id) |
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189 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_FRONT_END_ID ); |
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190 | if (_param->_have_port_ooo_engine_id) |
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191 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_OOO_ENGINE_ID ); |
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192 | if (_param->_have_port_rob_ptr ) |
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193 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_PACKET_ID ); |
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194 | //INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_OPERATION ); |
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195 | //INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_TYPE ); |
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196 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_WRITE_RD ); |
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197 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RD ); |
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198 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_DATA_RD ); |
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199 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_WRITE_RE ); |
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200 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_NUM_REG_RE ); |
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201 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_DATA_RE ); |
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202 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_EXCEPTION ); |
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203 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_NO_SEQUENCE ); |
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204 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_IN_ADDRESS ); |
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205 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_VAL ); |
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206 | INSTANCE0_SC_SIGNAL(_Write_queue, in_WRITE_QUEUE_OUT_ACK ); |
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207 | if (_param->_have_port_context_id) |
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208 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_CONTEXT_ID ); |
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209 | if (_param->_have_port_front_end_id) |
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210 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_FRONT_END_ID ); |
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211 | if (_param->_have_port_ooo_engine_id) |
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212 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_OOO_ENGINE_ID); |
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213 | if (_param->_have_port_rob_ptr ) |
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214 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_PACKET_ID ); |
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215 | //INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_OPERATION ); |
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216 | //INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_TYPE ); |
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217 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_FLAGS ); |
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218 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_EXCEPTION ); |
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219 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_NO_SEQUENCE ); |
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220 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_ADDRESS ); |
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221 | INSTANCE0_SC_SIGNAL(_Write_queue, out_WRITE_QUEUE_OUT_DATA ); |
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222 | INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_VAL , _param->_nb_gpr_write); |
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223 | INSTANCE1_SC_SIGNAL(_Write_queue, in_GPR_WRITE_ACK , _param->_nb_gpr_write); |
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224 | if (_param->_have_port_ooo_engine_id) |
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225 | INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_OOO_ENGINE_ID , _param->_nb_gpr_write); |
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226 | INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write); |
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227 | INSTANCE1_SC_SIGNAL(_Write_queue, out_GPR_WRITE_DATA , _param->_nb_gpr_write); |
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228 | INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_VAL , _param->_nb_spr_write); |
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229 | INSTANCE1_SC_SIGNAL(_Write_queue, in_SPR_WRITE_ACK , _param->_nb_spr_write); |
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230 | if (_param->_have_port_ooo_engine_id) |
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231 | INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_OOO_ENGINE_ID , _param->_nb_spr_write); |
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232 | INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_NUM_REG , _param->_nb_spr_write); |
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233 | INSTANCE1_SC_SIGNAL(_Write_queue, out_SPR_WRITE_DATA , _param->_nb_spr_write); |
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234 | if (_param->_have_port_ooo_engine_id) |
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235 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_OOO_ENGINE_ID , _param->_nb_bypass_write); |
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236 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write); |
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237 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write); |
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238 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write); |
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239 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write); |
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240 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write); |
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241 | INSTANCE1_SC_SIGNAL(_Write_queue, out_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write); |
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242 | |
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243 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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244 | |
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245 | Time * _time = new Time(); |
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246 | |
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247 | /******************************************************** |
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248 | * Simulation - Begin |
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249 | ********************************************************/ |
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250 | |
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251 | // Initialisation |
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252 | |
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253 | const uint32_t seed = 0; |
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254 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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255 | |
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256 | srand(seed); |
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257 | |
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258 | const int32_t percent_transaction_write_queue_in = 75; |
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259 | const int32_t percent_transaction_write_queue_out = 75; |
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260 | const int32_t percent_transaction_gpr = 75; |
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261 | const int32_t percent_transaction_spr = 75; |
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262 | |
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263 | bool gpr_val [_param->_nb_ooo_engine][_param->_nb_general_register]; |
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264 | bool gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register]; |
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265 | Tgeneral_data_t gpr [_param->_nb_ooo_engine][_param->_nb_general_register]; |
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266 | bool spr_val [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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267 | bool spr_use [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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268 | Tgeneral_data_t spr [_param->_nb_ooo_engine][_param->_nb_special_register]; |
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269 | |
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270 | entry_t * request [_param->_nb_packet]; |
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271 | |
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272 | SC_START(0); |
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273 | LABEL("Initialisation"); |
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274 | |
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275 | LABEL("Reset"); |
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276 | in_NRESET->write(0); |
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277 | SC_START(5); |
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278 | in_NRESET->write(1); |
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279 | |
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280 | LABEL("Loop of Test"); |
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281 | |
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282 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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283 | { |
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284 | LABEL("Iteration %d",iteration); |
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285 | |
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286 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
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287 | { |
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288 | for (uint32_t j=0; j<_param->_nb_general_register; j++) |
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289 | { |
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290 | gpr_val [i][j] = 0; |
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291 | gpr_use [i][j] = 0; |
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292 | gpr [i][j] = rand(); |
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293 | } |
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294 | for (uint32_t j=0; j<_param->_nb_special_register; j++) |
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295 | { |
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296 | spr_val [i][j] = 0; |
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297 | spr_use [i][j] = 0; |
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298 | spr [i][j] = rand(); |
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299 | } |
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300 | } |
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301 | |
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302 | for (uint32_t i=0; i<_param->_nb_packet; i++) |
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303 | { |
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304 | request [i] = new entry_t (range<Tcontext_t >(rand(),_param->_size_context_id ), |
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305 | range<Tcontext_t >(rand(),_param->_size_front_end_id ), |
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306 | range<Tcontext_t >(rand(),_param->_size_ooo_engine_id ), |
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307 | i, |
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308 | //range<Toperation_t >(rand(),_param->_size_operation ), |
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309 | //range<Ttype_t >(rand(),_param->_size_type ), |
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310 | range<Tcontrol_t >(rand(),1 ), |
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311 | range<Tgeneral_address_t>(rand(),_param->_size_general_register), |
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312 | range<Tgeneral_data_t >(rand(),_param->_size_general_data ), |
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313 | range<Tcontrol_t >(rand(),1 ), |
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314 | range<Tspecial_address_t>(rand(),_param->_size_special_register), |
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315 | range<Tspecial_data_t >(rand(),_param->_size_special_data ), |
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316 | range<Texception_t >(rand(),0 ), |
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317 | range<Tcontrol_t >(rand(),1 ), |
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318 | range<Tgeneral_data_t >(rand(),_param->_size_general_data )); |
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319 | } |
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320 | |
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321 | uint32_t nb_request_in = 0; |
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322 | uint32_t nb_request_out = 0; |
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323 | |
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324 | while (nb_request_out < _param->_nb_packet) |
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325 | { |
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326 | bool val = (((rand()%100)<percent_transaction_write_queue_in) and |
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327 | (nb_request_in < _param->_nb_packet) and |
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328 | not (request [nb_request_in]->_write_rd and |
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329 | gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd]) and |
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330 | not (request [nb_request_in]->_write_re and |
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331 | spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re])); |
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332 | |
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333 | in_WRITE_QUEUE_IN_VAL ->write(val); |
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334 | if (val) |
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335 | { |
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336 | in_WRITE_QUEUE_IN_CONTEXT_ID ->write(request [nb_request_in]->_context_id ); |
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337 | in_WRITE_QUEUE_IN_FRONT_END_ID ->write(request [nb_request_in]->_front_end_id ); |
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338 | in_WRITE_QUEUE_IN_OOO_ENGINE_ID->write(request [nb_request_in]->_ooo_engine_id); |
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339 | in_WRITE_QUEUE_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id ); |
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340 | //in_WRITE_QUEUE_IN_OPERATION ->write(request [nb_request_in]->_operation ); |
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341 | //in_WRITE_QUEUE_IN_TYPE ->write(request [nb_request_in]->_type ); |
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342 | in_WRITE_QUEUE_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd ); |
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343 | in_WRITE_QUEUE_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd ); |
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344 | in_WRITE_QUEUE_IN_DATA_RD ->write(request [nb_request_in]->_data_rd ); |
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345 | in_WRITE_QUEUE_IN_WRITE_RE ->write(request [nb_request_in]->_write_re ); |
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346 | in_WRITE_QUEUE_IN_NUM_REG_RE ->write(request [nb_request_in]->_num_reg_re ); |
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347 | in_WRITE_QUEUE_IN_DATA_RE ->write(request [nb_request_in]->_data_re ); |
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348 | in_WRITE_QUEUE_IN_EXCEPTION ->write(request [nb_request_in]->_exception ); |
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349 | in_WRITE_QUEUE_IN_NO_SEQUENCE ->write(request [nb_request_in]->_no_sequence ); |
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350 | in_WRITE_QUEUE_IN_ADDRESS ->write(request [nb_request_in]->_address ); |
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351 | } |
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352 | in_WRITE_QUEUE_OUT_ACK ->write((rand()%100)<percent_transaction_write_queue_out); |
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353 | in_GPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_gpr); |
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354 | in_SPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_spr); |
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355 | |
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356 | SC_START(0); |
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357 | |
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358 | // ====================================================================== |
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359 | // ====================================================================== |
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360 | // ====================================================================== |
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361 | if (out_GPR_WRITE_VAL [0]->read() and |
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362 | in_GPR_WRITE_ACK [0]->read()) |
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363 | { |
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364 | Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_GPR_WRITE_OOO_ENGINE_ID[0]->read():0; |
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365 | Tgeneral_address_t num_reg = out_GPR_WRITE_NUM_REG [0]->read(); |
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366 | Tgeneral_data_t data = out_GPR_WRITE_DATA [0]->read(); |
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367 | |
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368 | LABEL(" * Accepted GPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg); |
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369 | |
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370 | TEST(bool , gpr_val [ooo_engine_id][num_reg], 0); |
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371 | TEST(bool , gpr_use [ooo_engine_id][num_reg], 1); |
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372 | TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data); |
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373 | |
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374 | gpr_val [ooo_engine_id][num_reg] = 1; |
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375 | } |
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376 | |
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377 | // ====================================================================== |
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378 | // ====================================================================== |
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379 | // ====================================================================== |
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380 | if (out_SPR_WRITE_VAL [0]->read() and |
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381 | in_SPR_WRITE_ACK [0]->read()) |
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382 | { |
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383 | Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_SPR_WRITE_OOO_ENGINE_ID[0]->read():0; |
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384 | Tspecial_address_t num_reg = out_SPR_WRITE_NUM_REG [0]->read(); |
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385 | Tspecial_data_t data = out_SPR_WRITE_DATA [0]->read(); |
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386 | |
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387 | LABEL(" * Accepted SPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg); |
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388 | |
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389 | TEST(bool , spr_val [ooo_engine_id][num_reg], 0); |
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390 | TEST(bool , spr_use [ooo_engine_id][num_reg], 1); |
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391 | TEST(Tgeneral_data_t, spr [ooo_engine_id][num_reg], data); |
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392 | |
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393 | spr_val [ooo_engine_id][num_reg] = 1; |
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394 | } |
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395 | |
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396 | // ====================================================================== |
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397 | // ====================================================================== |
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398 | // ====================================================================== |
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399 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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400 | { |
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401 | Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_BYPASS_WRITE_OOO_ENGINE_ID[i]->read():0; |
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402 | |
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403 | if (out_BYPASS_WRITE_GPR_VAL [i]->read()) |
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404 | { |
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405 | Tgeneral_address_t num_reg = out_BYPASS_WRITE_GPR_NUM_REG [i]->read(); // RD |
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406 | Tgeneral_data_t data = out_BYPASS_WRITE_GPR_DATA [i]->read(); |
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407 | |
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408 | LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (GPR)", ooo_engine_id,num_reg); |
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409 | |
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410 | |
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411 | TEST(bool , gpr_use [ooo_engine_id][num_reg], 1); |
---|
412 | TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data); |
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413 | } |
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414 | if (out_BYPASS_WRITE_SPR_VAL [i]->read()) |
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415 | { |
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416 | Tspecial_address_t num_reg = out_BYPASS_WRITE_SPR_NUM_REG [i]->read(); // RE |
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417 | Tspecial_data_t data = out_BYPASS_WRITE_SPR_DATA [i]->read(); |
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418 | |
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419 | LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (SPR)", ooo_engine_id,num_reg); |
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420 | |
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421 | TEST(bool , spr_use [ooo_engine_id][num_reg], 1); |
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422 | TEST(Tspecial_data_t, spr [ooo_engine_id][num_reg], data); |
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423 | } |
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424 | } |
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425 | |
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426 | // ====================================================================== |
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427 | // ====================================================================== |
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428 | // ====================================================================== |
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429 | if ( in_WRITE_QUEUE_IN_VAL->read() and |
---|
430 | out_WRITE_QUEUE_IN_ACK->read()) |
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431 | { |
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432 | LABEL(" * Accepted WRITE_QUEUE_IN [%d]",nb_request_in); |
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433 | // std::cout << *request [nb_request_in] << std::endl; |
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434 | |
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435 | if (request [nb_request_in]->_write_rd) |
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436 | { |
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437 | gpr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 0; |
---|
438 | gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 1; |
---|
439 | gpr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = request [nb_request_in]->_data_rd; |
---|
440 | } |
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441 | if (request [nb_request_in]->_write_re) |
---|
442 | { |
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443 | spr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 0; |
---|
444 | spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 1; |
---|
445 | spr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = request [nb_request_in]->_data_re; |
---|
446 | } |
---|
447 | nb_request_in ++; |
---|
448 | } |
---|
449 | |
---|
450 | // ====================================================================== |
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451 | // ====================================================================== |
---|
452 | // ====================================================================== |
---|
453 | if (out_WRITE_QUEUE_OUT_VAL->read() and |
---|
454 | in_WRITE_QUEUE_OUT_ACK->read()) |
---|
455 | { |
---|
456 | Tcontext_t packet; |
---|
457 | if (_param->_have_port_rob_ptr) |
---|
458 | packet = out_WRITE_QUEUE_OUT_PACKET_ID->read(); |
---|
459 | else |
---|
460 | packet = 0; |
---|
461 | |
---|
462 | LABEL(" * Accepted WRITE_QUEUE_OUT [%d]",packet); |
---|
463 | // std::cout << *request [packet] << std::endl; |
---|
464 | |
---|
465 | if (request [packet]->_write_rd) |
---|
466 | { |
---|
467 | TEST(bool, gpr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1); |
---|
468 | TEST(bool, gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1); |
---|
469 | gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd] = 0; |
---|
470 | } |
---|
471 | if (request [packet]->_write_re) |
---|
472 | { |
---|
473 | TEST(bool, spr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1); |
---|
474 | TEST(bool, spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1); |
---|
475 | spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re] = 0; |
---|
476 | } |
---|
477 | |
---|
478 | if (_param->_have_port_context_id) |
---|
479 | TEST(Tcontext_t , out_WRITE_QUEUE_OUT_CONTEXT_ID ->read(), request [packet]->_context_id ); |
---|
480 | if (_param->_have_port_front_end_id) |
---|
481 | TEST(Tcontext_t , out_WRITE_QUEUE_OUT_FRONT_END_ID ->read(), request [packet]->_front_end_id ); |
---|
482 | if (_param->_have_port_ooo_engine_id) |
---|
483 | TEST(Tcontext_t , out_WRITE_QUEUE_OUT_OOO_ENGINE_ID->read(), request [packet]->_ooo_engine_id); |
---|
484 | |
---|
485 | //TEST(Toperation_t , out_WRITE_QUEUE_OUT_OPERATION ->read(), request [packet]->_operation ); |
---|
486 | //TEST(Ttype_t , out_WRITE_QUEUE_OUT_TYPE ->read(), request [packet]->_type ); |
---|
487 | TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_FLAGS ->read(), request [packet]->_data_re ); |
---|
488 | TEST(Texception_t , out_WRITE_QUEUE_OUT_EXCEPTION ->read(), request [packet]->_exception ); |
---|
489 | TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence ); |
---|
490 | TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_ADDRESS ->read(), request [packet]->_address ); |
---|
491 | TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_DATA ->read(), request [packet]->_data_rd ); |
---|
492 | |
---|
493 | nb_request_out ++; |
---|
494 | } |
---|
495 | |
---|
496 | SC_START(1); |
---|
497 | } |
---|
498 | |
---|
499 | for (uint32_t i=0; i<_param->_nb_packet; i++) |
---|
500 | delete request [i]; |
---|
501 | |
---|
502 | } |
---|
503 | |
---|
504 | /******************************************************** |
---|
505 | * Simulation - End |
---|
506 | ********************************************************/ |
---|
507 | |
---|
508 | TEST_OK ("End of Simulation"); |
---|
509 | delete _time; |
---|
510 | |
---|
511 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
---|
512 | |
---|
513 | delete in_CLOCK; |
---|
514 | delete in_NRESET; |
---|
515 | |
---|
516 | delete in_WRITE_QUEUE_IN_VAL ; |
---|
517 | delete out_WRITE_QUEUE_IN_ACK ; |
---|
518 | delete in_WRITE_QUEUE_IN_CONTEXT_ID ; |
---|
519 | delete in_WRITE_QUEUE_IN_FRONT_END_ID ; |
---|
520 | delete in_WRITE_QUEUE_IN_OOO_ENGINE_ID ; |
---|
521 | delete in_WRITE_QUEUE_IN_PACKET_ID ; |
---|
522 | //delete in_WRITE_QUEUE_IN_OPERATION ; |
---|
523 | //delete in_WRITE_QUEUE_IN_TYPE ; |
---|
524 | delete in_WRITE_QUEUE_IN_WRITE_RD ; |
---|
525 | delete in_WRITE_QUEUE_IN_NUM_REG_RD ; |
---|
526 | delete in_WRITE_QUEUE_IN_DATA_RD ; |
---|
527 | delete in_WRITE_QUEUE_IN_WRITE_RE ; |
---|
528 | delete in_WRITE_QUEUE_IN_NUM_REG_RE ; |
---|
529 | delete in_WRITE_QUEUE_IN_DATA_RE ; |
---|
530 | delete in_WRITE_QUEUE_IN_EXCEPTION ; |
---|
531 | delete in_WRITE_QUEUE_IN_NO_SEQUENCE ; |
---|
532 | delete in_WRITE_QUEUE_IN_ADDRESS ; |
---|
533 | delete out_WRITE_QUEUE_OUT_VAL ; |
---|
534 | delete in_WRITE_QUEUE_OUT_ACK ; |
---|
535 | delete out_WRITE_QUEUE_OUT_CONTEXT_ID ; |
---|
536 | delete out_WRITE_QUEUE_OUT_FRONT_END_ID ; |
---|
537 | delete out_WRITE_QUEUE_OUT_OOO_ENGINE_ID; |
---|
538 | delete out_WRITE_QUEUE_OUT_PACKET_ID ; |
---|
539 | //delete out_WRITE_QUEUE_OUT_OPERATION ; |
---|
540 | //delete out_WRITE_QUEUE_OUT_TYPE ; |
---|
541 | delete out_WRITE_QUEUE_OUT_FLAGS ; |
---|
542 | delete out_WRITE_QUEUE_OUT_EXCEPTION ; |
---|
543 | delete out_WRITE_QUEUE_OUT_NO_SEQUENCE ; |
---|
544 | delete out_WRITE_QUEUE_OUT_ADDRESS ; |
---|
545 | delete out_WRITE_QUEUE_OUT_DATA ; |
---|
546 | delete [] out_GPR_WRITE_VAL ; |
---|
547 | delete [] in_GPR_WRITE_ACK ; |
---|
548 | delete [] out_GPR_WRITE_OOO_ENGINE_ID ; |
---|
549 | delete [] out_GPR_WRITE_NUM_REG ; |
---|
550 | delete [] out_GPR_WRITE_DATA ; |
---|
551 | delete [] out_SPR_WRITE_VAL ; |
---|
552 | delete [] in_SPR_WRITE_ACK ; |
---|
553 | delete [] out_SPR_WRITE_OOO_ENGINE_ID ; |
---|
554 | delete [] out_SPR_WRITE_NUM_REG ; |
---|
555 | delete [] out_SPR_WRITE_DATA ; |
---|
556 | delete [] out_BYPASS_WRITE_OOO_ENGINE_ID ; |
---|
557 | delete [] out_BYPASS_WRITE_GPR_VAL ; |
---|
558 | delete [] out_BYPASS_WRITE_GPR_NUM_REG ; |
---|
559 | delete [] out_BYPASS_WRITE_GPR_DATA ; |
---|
560 | delete [] out_BYPASS_WRITE_SPR_VAL ; |
---|
561 | delete [] out_BYPASS_WRITE_SPR_NUM_REG ; |
---|
562 | delete [] out_BYPASS_WRITE_SPR_DATA ; |
---|
563 | |
---|
564 | #endif |
---|
565 | |
---|
566 | delete _Write_queue; |
---|
567 | #ifdef STATISTICS |
---|
568 | delete _parameters_statistics; |
---|
569 | #endif |
---|
570 | } |
---|