source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/top_allocation.cpp @ 113

Last change on this file since 113 was 113, checked in by rosiere, 15 years ago

1) Add modelsim simulation systemC
2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit)
3) Add multi architecture
5) Add template for comparator, multiplier and divider
6) Change Message
Warning) Various test macro have change, many selftest can't compile
  • Property svn:keywords set to Id
File size: 11.6 KB
Line 
1/*
2 * $Id: top_allocation.cpp 113 2009-04-14 18:39:12Z rosiere $
3 *
4 * [ Description ]
5 *
6 * Test
7 */
8
9#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/include/top.h"
10#include "Behavioural/include/Allocation.h"
11
12void top::allocation (void)
13{
14  if (setlocale (LC_ALL, "") == NULL)
15    msgWarning(_("setlocale ko.\n"));
16
17  try 
18    {
19      _param->test();
20    }
21  catch (morpheo::ErrorMorpheo & error)
22    {
23      msgError(_("<%s> : %s"),name.c_str(),error.what());
24      return;
25    }
26  catch (...)
27    {
28      msgError(_("<%s> : This test must generate a error"),name.c_str());
29      exit (EXIT_FAILURE);
30    }
31
32  _usage = USE_ALL;
33//   _usage = usage_unset(_usage,USE_SYSTEMC              );
34//   _usage = usage_unset(_usage,USE_VHDL                 );
35//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
36//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
37//   _usage = usage_unset(_usage,USE_POSITION             );
38//   _usage = usage_unset(_usage,USE_STATISTICS           );
39//   _usage = usage_unset(_usage,USE_INFORMATION          );
40
41#ifdef STATISTICS
42  if (usage_is_set(_usage,USE_STATISTICS))
43  _param_stat = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
44#endif
45
46  component = new Write_queue
47    (name.c_str(),
48#ifdef STATISTICS
49     _param_stat,
50#endif
51     _param,
52     _usage
53     );
54 
55#ifdef SYSTEMC
56  if (usage_is_set(_usage,USE_SYSTEMC))
57    {
58  /*********************************************************************
59   * Déclarations des signaux
60   *********************************************************************/
61  msgInformation(_("<%s> : Create signal.\n"),name.c_str());
62
63  in_CLOCK  = new sc_clock ("clock", TIME_PERIOD, TIME_UNIT, 0.5); //name,period,time_unit,duty_cycle
64
65  ALLOC0_SC_SIGNAL( in_NRESET        ," in_NRESET        ",Tcontrol_t);
66
67  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_VAL           ," in_WRITE_QUEUE_IN_VAL"           , Tcontrol_t        );
68  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_IN_ACK           ,"out_WRITE_QUEUE_IN_ACK"           , Tcontrol_t        );
69  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_CONTEXT_ID    ," in_WRITE_QUEUE_IN_CONTEXT_ID"    , Tcontext_t        );
70  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_FRONT_END_ID  ," in_WRITE_QUEUE_IN_FRONT_END_ID"  , Tcontext_t        );
71  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_OOO_ENGINE_ID ," in_WRITE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t        );
72  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_PACKET_ID     ," in_WRITE_QUEUE_IN_PACKET_ID"     , Tpacket_t         );
73//ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_OPERATION     ," in_WRITE_QUEUE_IN_OPERATION"     , Toperation_t      );
74//ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_TYPE          ," in_WRITE_QUEUE_IN_TYPE"          , Ttype_t           );
75  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RD      ," in_WRITE_QUEUE_IN_WRITE_RD"      , Tcontrol_t        );
76  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RD    ," in_WRITE_QUEUE_IN_NUM_REG_RD"    , Tgeneral_address_t);
77  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_DATA_RD       ," in_WRITE_QUEUE_IN_DATA_RD"       , Tgeneral_data_t   );
78  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RE      ," in_WRITE_QUEUE_IN_WRITE_RE"      , Tcontrol_t        );
79  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RE    ," in_WRITE_QUEUE_IN_NUM_REG_RE"    , Tspecial_address_t);
80  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_DATA_RE       ," in_WRITE_QUEUE_IN_DATA_RE"       , Tspecial_data_t   );
81  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_EXCEPTION     ," in_WRITE_QUEUE_IN_EXCEPTION"     , Texception_t      );
82  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NO_SEQUENCE   ," in_WRITE_QUEUE_IN_NO_SEQUENCE"   , Tcontrol_t        );
83  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_ADDRESS       ," in_WRITE_QUEUE_IN_ADDRESS"       , Taddress_t        );
84  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_VAL          ,"out_WRITE_QUEUE_OUT_VAL"          , Tcontrol_t        );
85  ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_OUT_ACK          ," in_WRITE_QUEUE_OUT_ACK"          , Tcontrol_t        );
86  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_CONTEXT_ID   ,"out_WRITE_QUEUE_OUT_CONTEXT_ID"   , Tcontext_t        );
87  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_FRONT_END_ID ,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t        );
88  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t        );
89  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_PACKET_ID    ,"out_WRITE_QUEUE_OUT_PACKET_ID"    , Tpacket_t         );
90//ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_OPERATION    ,"out_WRITE_QUEUE_OUT_OPERATION"    , Toperation_t      );
91//ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_TYPE         ,"out_WRITE_QUEUE_OUT_TYPE"         , Ttype_t           );
92  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_FLAGS        ,"out_WRITE_QUEUE_OUT_FLAGS"        , Tspecial_data_t   );
93  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_EXCEPTION    ,"out_WRITE_QUEUE_OUT_EXCEPTION"    , Texception_t      );
94  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_NO_SEQUENCE  ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE"  , Tcontrol_t        );
95  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_ADDRESS      ,"out_WRITE_QUEUE_OUT_ADDRESS"      , Tgeneral_data_t   );
96  ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_DATA         ,"out_WRITE_QUEUE_OUT_DATA"         , Taddress_t        );
97  ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL                ,"out_GPR_WRITE_VAL"                , Tcontrol_t        , _param->_nb_gpr_write);
98  ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK                ," in_GPR_WRITE_ACK"                , Tcontrol_t        , _param->_nb_gpr_write);
99  ALLOC1_SC_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID      ,"out_GPR_WRITE_OOO_ENGINE_ID"      , Tcontext_t        , _param->_nb_gpr_write);
100  ALLOC1_SC_SIGNAL(out_GPR_WRITE_NUM_REG            ,"out_GPR_WRITE_NUM_REG"            , Tgeneral_address_t, _param->_nb_gpr_write);
101  ALLOC1_SC_SIGNAL(out_GPR_WRITE_DATA               ,"out_GPR_WRITE_DATA"               , Tgeneral_data_t   , _param->_nb_gpr_write);
102  ALLOC1_SC_SIGNAL(out_SPR_WRITE_VAL                ,"out_SPR_WRITE_VAL"                , Tcontrol_t        , _param->_nb_spr_write);
103  ALLOC1_SC_SIGNAL( in_SPR_WRITE_ACK                ," in_SPR_WRITE_ACK"                , Tcontrol_t        , _param->_nb_spr_write);
104  ALLOC1_SC_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID      ,"out_SPR_WRITE_OOO_ENGINE_ID"      , Tcontext_t        , _param->_nb_spr_write);
105  ALLOC1_SC_SIGNAL(out_SPR_WRITE_NUM_REG            ,"out_SPR_WRITE_NUM_REG"            , Tspecial_address_t, _param->_nb_spr_write);
106  ALLOC1_SC_SIGNAL(out_SPR_WRITE_DATA               ,"out_SPR_WRITE_DATA"               , Tspecial_data_t   , _param->_nb_spr_write);
107  ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID   ,"out_BYPASS_WRITE_OOO_ENGINE_ID"   , Tcontext_t        , _param->_nb_bypass_write);
108  ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_VAL         ,"out_BYPASS_WRITE_GPR_VAL"         , Tcontrol_t        , _param->_nb_bypass_write);
109  ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG     ,"out_BYPASS_WRITE_GPR_NUM_REG"     , Tgeneral_address_t, _param->_nb_bypass_write);
110  ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_DATA        ,"out_BYPASS_WRITE_GPR_DATA"        , Tgeneral_data_t   , _param->_nb_bypass_write);
111  ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_VAL         ,"out_BYPASS_WRITE_SPR_VAL"         , Tcontrol_t        , _param->_nb_bypass_write);
112  ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG     ,"out_BYPASS_WRITE_SPR_NUM_REG"     , Tspecial_address_t, _param->_nb_bypass_write);
113  ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_DATA        ,"out_BYPASS_WRITE_SPR_DATA"        , Tspecial_data_t   , _param->_nb_bypass_write);
114 
115  /********************************************************
116   * Instanciation
117   ********************************************************/
118 
119  msgInformation(_("<%s> : Instanciation of _Write_queue.\n"),name.c_str());
120
121  INSTANCE0_SC_SIGNAL(component, in_CLOCK         );
122  INSTANCE0_SC_SIGNAL(component, in_NRESET        );
123
124  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_VAL           );
125  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_IN_ACK           );
126  if (_param->_have_port_context_id)
127  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_CONTEXT_ID    );
128  if (_param->_have_port_front_end_id)
129  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_FRONT_END_ID  );
130  if (_param->_have_port_ooo_engine_id)
131  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_OOO_ENGINE_ID );
132  if (_param->_have_port_rob_ptr  )
133  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_PACKET_ID     );
134//INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_OPERATION     );
135//INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_TYPE          );
136  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_WRITE_RD      );
137  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_NUM_REG_RD    );
138  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_DATA_RD       );
139  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_WRITE_RE      );
140  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_NUM_REG_RE    );
141  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_DATA_RE       );
142  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_EXCEPTION     );
143  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_NO_SEQUENCE   );
144  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_IN_ADDRESS       );
145  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_VAL          );
146  INSTANCE0_SC_SIGNAL(component,  in_WRITE_QUEUE_OUT_ACK          );
147  if (_param->_have_port_context_id)
148  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_CONTEXT_ID   );
149  if (_param->_have_port_front_end_id)
150  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_FRONT_END_ID );
151  if (_param->_have_port_ooo_engine_id)
152  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_OOO_ENGINE_ID);
153  if (_param->_have_port_rob_ptr  )
154  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_PACKET_ID    );
155//INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_OPERATION    );
156//INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_TYPE         );
157  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_FLAGS        );
158  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_EXCEPTION    );
159  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_NO_SEQUENCE  );
160  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_ADDRESS      );
161  INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_DATA         );
162  INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_VAL                , _param->_nb_gpr_write);
163  INSTANCE1_SC_SIGNAL(component,  in_GPR_WRITE_ACK                , _param->_nb_gpr_write);
164  if (_param->_have_port_ooo_engine_id)
165  INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_OOO_ENGINE_ID      , _param->_nb_gpr_write);
166  INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_NUM_REG            , _param->_nb_gpr_write);
167  INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_DATA               , _param->_nb_gpr_write);
168  INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_VAL                , _param->_nb_spr_write);
169  INSTANCE1_SC_SIGNAL(component,  in_SPR_WRITE_ACK                , _param->_nb_spr_write);
170  if (_param->_have_port_ooo_engine_id)
171  INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_OOO_ENGINE_ID      , _param->_nb_spr_write);
172  INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_NUM_REG            , _param->_nb_spr_write);
173  INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_DATA               , _param->_nb_spr_write);
174  if (_param->_have_port_ooo_engine_id)
175  INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_OOO_ENGINE_ID   , _param->_nb_bypass_write);
176  INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_GPR_VAL         , _param->_nb_bypass_write);
177  INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_GPR_NUM_REG     , _param->_nb_bypass_write);
178  INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_GPR_DATA        , _param->_nb_bypass_write);
179  INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_SPR_VAL         , _param->_nb_bypass_write);
180  INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_SPR_NUM_REG     , _param->_nb_bypass_write);
181  INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_SPR_DATA        , _param->_nb_bypass_write);
182    }
183#endif
184}
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