1 | /* |
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2 | * $Id: top_allocation.cpp 113 2009-04-14 18:39:12Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/include/top.h" |
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10 | #include "Behavioural/include/Allocation.h" |
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11 | |
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12 | void top::allocation (void) |
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13 | { |
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14 | if (setlocale (LC_ALL, "") == NULL) |
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15 | msgWarning(_("setlocale ko.\n")); |
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16 | |
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17 | try |
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18 | { |
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19 | _param->test(); |
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20 | } |
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21 | catch (morpheo::ErrorMorpheo & error) |
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22 | { |
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23 | msgError(_("<%s> : %s"),name.c_str(),error.what()); |
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24 | return; |
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25 | } |
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26 | catch (...) |
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27 | { |
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28 | msgError(_("<%s> : This test must generate a error"),name.c_str()); |
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29 | exit (EXIT_FAILURE); |
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30 | } |
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31 | |
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32 | _usage = USE_ALL; |
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33 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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34 | // _usage = usage_unset(_usage,USE_VHDL ); |
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35 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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36 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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37 | // _usage = usage_unset(_usage,USE_POSITION ); |
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38 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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39 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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40 | |
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41 | #ifdef STATISTICS |
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42 | if (usage_is_set(_usage,USE_STATISTICS)) |
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43 | _param_stat = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX); |
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44 | #endif |
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45 | |
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46 | component = new Write_queue |
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47 | (name.c_str(), |
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48 | #ifdef STATISTICS |
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49 | _param_stat, |
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50 | #endif |
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51 | _param, |
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52 | _usage |
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53 | ); |
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54 | |
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55 | #ifdef SYSTEMC |
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56 | if (usage_is_set(_usage,USE_SYSTEMC)) |
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57 | { |
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58 | /********************************************************************* |
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59 | * Déclarations des signaux |
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60 | *********************************************************************/ |
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61 | msgInformation(_("<%s> : Create signal.\n"),name.c_str()); |
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62 | |
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63 | in_CLOCK = new sc_clock ("clock", TIME_PERIOD, TIME_UNIT, 0.5); //name,period,time_unit,duty_cycle |
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64 | |
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65 | ALLOC0_SC_SIGNAL( in_NRESET ," in_NRESET ",Tcontrol_t); |
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66 | |
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67 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_VAL ," in_WRITE_QUEUE_IN_VAL" , Tcontrol_t ); |
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68 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_IN_ACK ,"out_WRITE_QUEUE_IN_ACK" , Tcontrol_t ); |
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69 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_CONTEXT_ID ," in_WRITE_QUEUE_IN_CONTEXT_ID" , Tcontext_t ); |
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70 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_FRONT_END_ID ," in_WRITE_QUEUE_IN_FRONT_END_ID" , Tcontext_t ); |
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71 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_OOO_ENGINE_ID ," in_WRITE_QUEUE_IN_OOO_ENGINE_ID" , Tcontext_t ); |
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72 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_PACKET_ID ," in_WRITE_QUEUE_IN_PACKET_ID" , Tpacket_t ); |
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73 | //ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_OPERATION ," in_WRITE_QUEUE_IN_OPERATION" , Toperation_t ); |
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74 | //ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_TYPE ," in_WRITE_QUEUE_IN_TYPE" , Ttype_t ); |
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75 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RD ," in_WRITE_QUEUE_IN_WRITE_RD" , Tcontrol_t ); |
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76 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RD ," in_WRITE_QUEUE_IN_NUM_REG_RD" , Tgeneral_address_t); |
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77 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_DATA_RD ," in_WRITE_QUEUE_IN_DATA_RD" , Tgeneral_data_t ); |
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78 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_WRITE_RE ," in_WRITE_QUEUE_IN_WRITE_RE" , Tcontrol_t ); |
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79 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NUM_REG_RE ," in_WRITE_QUEUE_IN_NUM_REG_RE" , Tspecial_address_t); |
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80 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_DATA_RE ," in_WRITE_QUEUE_IN_DATA_RE" , Tspecial_data_t ); |
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81 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_EXCEPTION ," in_WRITE_QUEUE_IN_EXCEPTION" , Texception_t ); |
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82 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_NO_SEQUENCE ," in_WRITE_QUEUE_IN_NO_SEQUENCE" , Tcontrol_t ); |
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83 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_IN_ADDRESS ," in_WRITE_QUEUE_IN_ADDRESS" , Taddress_t ); |
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84 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_VAL ,"out_WRITE_QUEUE_OUT_VAL" , Tcontrol_t ); |
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85 | ALLOC0_SC_SIGNAL( in_WRITE_QUEUE_OUT_ACK ," in_WRITE_QUEUE_OUT_ACK" , Tcontrol_t ); |
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86 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_CONTEXT_ID ,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , Tcontext_t ); |
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87 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_FRONT_END_ID ,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , Tcontext_t ); |
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88 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", Tcontext_t ); |
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89 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_PACKET_ID ,"out_WRITE_QUEUE_OUT_PACKET_ID" , Tpacket_t ); |
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90 | //ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_OPERATION ,"out_WRITE_QUEUE_OUT_OPERATION" , Toperation_t ); |
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91 | //ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_TYPE ,"out_WRITE_QUEUE_OUT_TYPE" , Ttype_t ); |
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92 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_FLAGS ,"out_WRITE_QUEUE_OUT_FLAGS" , Tspecial_data_t ); |
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93 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_EXCEPTION ,"out_WRITE_QUEUE_OUT_EXCEPTION" , Texception_t ); |
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94 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , Tcontrol_t ); |
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95 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_ADDRESS ,"out_WRITE_QUEUE_OUT_ADDRESS" , Tgeneral_data_t ); |
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96 | ALLOC0_SC_SIGNAL(out_WRITE_QUEUE_OUT_DATA ,"out_WRITE_QUEUE_OUT_DATA" , Taddress_t ); |
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97 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_VAL ,"out_GPR_WRITE_VAL" , Tcontrol_t , _param->_nb_gpr_write); |
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98 | ALLOC1_SC_SIGNAL( in_GPR_WRITE_ACK ," in_GPR_WRITE_ACK" , Tcontrol_t , _param->_nb_gpr_write); |
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99 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_OOO_ENGINE_ID ,"out_GPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_gpr_write); |
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100 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_NUM_REG ,"out_GPR_WRITE_NUM_REG" , Tgeneral_address_t, _param->_nb_gpr_write); |
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101 | ALLOC1_SC_SIGNAL(out_GPR_WRITE_DATA ,"out_GPR_WRITE_DATA" , Tgeneral_data_t , _param->_nb_gpr_write); |
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102 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_VAL ,"out_SPR_WRITE_VAL" , Tcontrol_t , _param->_nb_spr_write); |
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103 | ALLOC1_SC_SIGNAL( in_SPR_WRITE_ACK ," in_SPR_WRITE_ACK" , Tcontrol_t , _param->_nb_spr_write); |
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104 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_OOO_ENGINE_ID ,"out_SPR_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_spr_write); |
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105 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_NUM_REG ,"out_SPR_WRITE_NUM_REG" , Tspecial_address_t, _param->_nb_spr_write); |
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106 | ALLOC1_SC_SIGNAL(out_SPR_WRITE_DATA ,"out_SPR_WRITE_DATA" , Tspecial_data_t , _param->_nb_spr_write); |
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107 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_OOO_ENGINE_ID ,"out_BYPASS_WRITE_OOO_ENGINE_ID" , Tcontext_t , _param->_nb_bypass_write); |
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108 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_VAL ,"out_BYPASS_WRITE_GPR_VAL" , Tcontrol_t , _param->_nb_bypass_write); |
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109 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_NUM_REG ,"out_BYPASS_WRITE_GPR_NUM_REG" , Tgeneral_address_t, _param->_nb_bypass_write); |
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110 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_GPR_DATA ,"out_BYPASS_WRITE_GPR_DATA" , Tgeneral_data_t , _param->_nb_bypass_write); |
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111 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_VAL ,"out_BYPASS_WRITE_SPR_VAL" , Tcontrol_t , _param->_nb_bypass_write); |
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112 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_NUM_REG ,"out_BYPASS_WRITE_SPR_NUM_REG" , Tspecial_address_t, _param->_nb_bypass_write); |
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113 | ALLOC1_SC_SIGNAL(out_BYPASS_WRITE_SPR_DATA ,"out_BYPASS_WRITE_SPR_DATA" , Tspecial_data_t , _param->_nb_bypass_write); |
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114 | |
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115 | /******************************************************** |
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116 | * Instanciation |
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117 | ********************************************************/ |
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118 | |
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119 | msgInformation(_("<%s> : Instanciation of _Write_queue.\n"),name.c_str()); |
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120 | |
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121 | INSTANCE0_SC_SIGNAL(component, in_CLOCK ); |
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122 | INSTANCE0_SC_SIGNAL(component, in_NRESET ); |
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123 | |
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124 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_VAL ); |
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125 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_IN_ACK ); |
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126 | if (_param->_have_port_context_id) |
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127 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_CONTEXT_ID ); |
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128 | if (_param->_have_port_front_end_id) |
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129 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_FRONT_END_ID ); |
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130 | if (_param->_have_port_ooo_engine_id) |
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131 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_OOO_ENGINE_ID ); |
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132 | if (_param->_have_port_rob_ptr ) |
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133 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_PACKET_ID ); |
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134 | //INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_OPERATION ); |
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135 | //INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_TYPE ); |
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136 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_WRITE_RD ); |
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137 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_NUM_REG_RD ); |
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138 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_DATA_RD ); |
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139 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_WRITE_RE ); |
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140 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_NUM_REG_RE ); |
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141 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_DATA_RE ); |
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142 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_EXCEPTION ); |
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143 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_NO_SEQUENCE ); |
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144 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_IN_ADDRESS ); |
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145 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_VAL ); |
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146 | INSTANCE0_SC_SIGNAL(component, in_WRITE_QUEUE_OUT_ACK ); |
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147 | if (_param->_have_port_context_id) |
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148 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_CONTEXT_ID ); |
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149 | if (_param->_have_port_front_end_id) |
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150 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_FRONT_END_ID ); |
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151 | if (_param->_have_port_ooo_engine_id) |
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152 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_OOO_ENGINE_ID); |
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153 | if (_param->_have_port_rob_ptr ) |
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154 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_PACKET_ID ); |
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155 | //INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_OPERATION ); |
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156 | //INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_TYPE ); |
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157 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_FLAGS ); |
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158 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_EXCEPTION ); |
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159 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_NO_SEQUENCE ); |
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160 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_ADDRESS ); |
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161 | INSTANCE0_SC_SIGNAL(component, out_WRITE_QUEUE_OUT_DATA ); |
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162 | INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_VAL , _param->_nb_gpr_write); |
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163 | INSTANCE1_SC_SIGNAL(component, in_GPR_WRITE_ACK , _param->_nb_gpr_write); |
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164 | if (_param->_have_port_ooo_engine_id) |
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165 | INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_OOO_ENGINE_ID , _param->_nb_gpr_write); |
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166 | INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_NUM_REG , _param->_nb_gpr_write); |
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167 | INSTANCE1_SC_SIGNAL(component, out_GPR_WRITE_DATA , _param->_nb_gpr_write); |
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168 | INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_VAL , _param->_nb_spr_write); |
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169 | INSTANCE1_SC_SIGNAL(component, in_SPR_WRITE_ACK , _param->_nb_spr_write); |
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170 | if (_param->_have_port_ooo_engine_id) |
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171 | INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_OOO_ENGINE_ID , _param->_nb_spr_write); |
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172 | INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_NUM_REG , _param->_nb_spr_write); |
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173 | INSTANCE1_SC_SIGNAL(component, out_SPR_WRITE_DATA , _param->_nb_spr_write); |
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174 | if (_param->_have_port_ooo_engine_id) |
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175 | INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_OOO_ENGINE_ID , _param->_nb_bypass_write); |
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176 | INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_GPR_VAL , _param->_nb_bypass_write); |
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177 | INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_GPR_NUM_REG , _param->_nb_bypass_write); |
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178 | INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_GPR_DATA , _param->_nb_bypass_write); |
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179 | INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_SPR_VAL , _param->_nb_bypass_write); |
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180 | INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_SPR_NUM_REG , _param->_nb_bypass_write); |
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181 | INSTANCE1_SC_SIGNAL(component, out_BYPASS_WRITE_SPR_DATA , _param->_nb_bypass_write); |
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182 | } |
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183 | #endif |
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184 | } |
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