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top_test.cpp @ 113

Last change on this file since 113 was 113, checked in by rosiere, 15 years ago
1) Add modelsim simulation systemC 2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit) 3) Add multi architecture 5) Add template for comparator, multiplier and divider 6) Change Message Warning) Various test macro have change, many selftest can't compile
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File size: 15.6 KB

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1	/*
2	* $Id: top_test.cpp 113 2009-04-14 18:39:12Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/include/top.h"
10	#include "Behavioural/include/Allocation.h"
11	#include "Common/include/BitManipulation.h"
12
13	class entry_t
14	{
15	public : Tcontext_t _context_id ;
16	public : Tcontext_t _front_end_id ;
17	public : Tcontext_t _ooo_engine_id;
18	public : Tpacket_t _packet_id ;
19	//public : Toperation_t _operation ;
20	//public : Ttype_t _type ;
21	public : Tcontrol_t _write_rd ;
22	public : Tgeneral_address_t _num_reg_rd ;
23	public : Tgeneral_data_t _data_rd ;
24	public : Tcontrol_t _write_re ;
25	public : Tspecial_address_t _num_reg_re ;
26	public : Tspecial_data_t _data_re ;
27	public : Texception_t _exception ;
28	public : Tcontrol_t _no_sequence ;
29	public : Tgeneral_data_t _address ;
30
31	public : entry_t (Tcontext_t context_id ,
32	Tcontext_t front_end_id ,
33	Tcontext_t ooo_engine_id,
34	Tpacket_t packet_id ,
35	// Toperation_t operation ,
36	// Ttype_t type ,
37	Tcontrol_t write_rd ,
38	Tgeneral_address_t num_reg_rd ,
39	Tgeneral_data_t data_rd ,
40	Tcontrol_t write_re ,
41	Tspecial_address_t num_reg_re ,
42	Tspecial_data_t data_re ,
43	Texception_t exception ,
44	Tcontrol_t no_sequence ,
45	Tgeneral_data_t address )
46	{
47	_context_id = context_id ;
48	_front_end_id = front_end_id ;
49	_ooo_engine_id = ooo_engine_id;
50	_packet_id = packet_id ;
51	//_operation = operation ;
52	//_type = type ;
53	_write_rd = write_rd ;
54	_num_reg_rd = num_reg_rd ;
55	_data_rd = data_rd ;
56	_write_re = write_re ;
57	_num_reg_re = num_reg_re ;
58	_data_re = data_re ;
59	_exception = exception ;
60	_no_sequence = no_sequence ;
61	_address = address ;
62	};
63
64	friend std::ostream& operator<< (std::ostream& output_stream,
65	entry_t & x)
66	{
67	output_stream << " * _context_id : " << toString(x._context_id ) << std::endl
68	<< " * _front_end_id : " << toString(x._front_end_id ) << std::endl
69	<< " * _ooo_engine_id : " << toString(x._ooo_engine_id) << std::endl
70	<< " * _packet_id : " << toString(x._packet_id ) << std::endl
71	//<< " * _operation : " << toString(x._operation ) << std::endl
72	//<< " * _type : " << toString(x._type ) << std::endl
73	<< " * _write_rd : " << toString(x._write_rd ) << std::endl
74	<< " * _num_reg_rd : " << toString(x._num_reg_rd ) << std::endl
75	<< " * _data_rd : " << toString(x._data_rd ) << std::endl
76	<< " * _write_re : " << toString(x._write_re ) << std::endl
77	<< " * _num_reg_re : " << toString(x._num_reg_re ) << std::endl
78	<< " * _data_re : " << toString(x._data_re ) << std::endl
79	<< " * _exception : " << toString(x._exception ) << std::endl
80	<< " * _no_sequence : " << toString(x._no_sequence ) << std::endl
81	<< " * _address : " << toString(x._address ) << std::endl;
82
83	return output_stream;
84	}
85	};
86
87	void top::test (void)
88	{
89	#ifdef SYSTEMC
90	if (usage_is_set(_usage,USE_SYSTEMC))
91	{
92	msgInformation(_("<%s> : Start Simulation ............\n"),name.c_str());
93
94	Time * _time = new Time();
95
96	/********************************************************
97	* Simulation - Begin
98	********************************************************/
99
100	// Initialisation
101
102	const uint32_t seed = 0;
103	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
104
105	srand(seed);
106
107	const int32_t percent_transaction_write_queue_in = 75;
108	const int32_t percent_transaction_write_queue_out = 75;
109	const int32_t percent_transaction_gpr = 75;
110	const int32_t percent_transaction_spr = 75;
111
112	bool gpr_val [_param->_nb_ooo_engine][_param->_nb_general_register];
113	bool gpr_use [_param->_nb_ooo_engine][_param->_nb_general_register];
114	Tgeneral_data_t gpr [_param->_nb_ooo_engine][_param->_nb_general_register];
115	bool spr_val [_param->_nb_ooo_engine][_param->_nb_special_register];
116	bool spr_use [_param->_nb_ooo_engine][_param->_nb_special_register];
117	Tgeneral_data_t spr [_param->_nb_ooo_engine][_param->_nb_special_register];
118
119	entry_t * request [_param->_nb_packet];
120
121	SC_CYCLE(0);
122	LABEL("Initialisation");
123
124	LABEL("Reset");
125	in_NRESET->write(0);
126	SC_CYCLE(5);
127	in_NRESET->write(1);
128
129	LABEL("Loop of Test");
130
131	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
132	{
133	LABEL("Iteration %d",iteration);
134
135	for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
136	{
137	for (uint32_t j=0; j<_param->_nb_general_register; j++)
138	{
139	gpr_val [i][j] = 0;
140	gpr_use [i][j] = 0;
141	gpr [i][j] = rand();
142	}
143	for (uint32_t j=0; j<_param->_nb_special_register; j++)
144	{
145	spr_val [i][j] = 0;
146	spr_use [i][j] = 0;
147	spr [i][j] = rand();
148	}
149	}
150
151	for (uint32_t i=0; i<_param->_nb_packet; i++)
152	{
153	request [i] = new entry_t (range<Tcontext_t >(rand(),_param->_size_context_id ),
154	range<Tcontext_t >(rand(),_param->_size_front_end_id ),
155	range<Tcontext_t >(rand(),_param->_size_ooo_engine_id ),
156	i,
157	//range<Toperation_t >(rand(),_param->_size_operation ),
158	//range<Ttype_t >(rand(),_param->_size_type ),
159	range<Tcontrol_t >(rand(),1 ),
160	range<Tgeneral_address_t>(rand(),_param->_size_general_register),
161	range<Tgeneral_data_t >(rand(),_param->_size_general_data ),
162	range<Tcontrol_t >(rand(),1 ),
163	range<Tspecial_address_t>(rand(),_param->_size_special_register),
164	range<Tspecial_data_t >(rand(),_param->_size_special_data ),
165	range<Texception_t >(rand(),0 ),
166	range<Tcontrol_t >(rand(),1 ),
167	range<Tgeneral_data_t >(rand(),_param->_size_general_data ));
168	}
169
170	uint32_t nb_request_in = 0;
171	uint32_t nb_request_out = 0;
172
173	while (nb_request_out < _param->_nb_packet)
174	{
175	bool val = (((rand()%100)<percent_transaction_write_queue_in) and
176	(nb_request_in < _param->_nb_packet) and
177	not (request [nb_request_in]->_write_rd and
178	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd]) and
179	not (request [nb_request_in]->_write_re and
180	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re]));
181
182	in_WRITE_QUEUE_IN_VAL ->write(val);
183	if (val)
184	{
185	in_WRITE_QUEUE_IN_CONTEXT_ID ->write(request [nb_request_in]->_context_id );
186	in_WRITE_QUEUE_IN_FRONT_END_ID ->write(request [nb_request_in]->_front_end_id );
187	in_WRITE_QUEUE_IN_OOO_ENGINE_ID->write(request [nb_request_in]->_ooo_engine_id);
188	in_WRITE_QUEUE_IN_PACKET_ID ->write(request [nb_request_in]->_packet_id );
189	//in_WRITE_QUEUE_IN_OPERATION ->write(request [nb_request_in]->_operation );
190	//in_WRITE_QUEUE_IN_TYPE ->write(request [nb_request_in]->_type );
191	in_WRITE_QUEUE_IN_WRITE_RD ->write(request [nb_request_in]->_write_rd );
192	in_WRITE_QUEUE_IN_NUM_REG_RD ->write(request [nb_request_in]->_num_reg_rd );
193	in_WRITE_QUEUE_IN_DATA_RD ->write(request [nb_request_in]->_data_rd );
194	in_WRITE_QUEUE_IN_WRITE_RE ->write(request [nb_request_in]->_write_re );
195	in_WRITE_QUEUE_IN_NUM_REG_RE ->write(request [nb_request_in]->_num_reg_re );
196	in_WRITE_QUEUE_IN_DATA_RE ->write(request [nb_request_in]->_data_re );
197	in_WRITE_QUEUE_IN_EXCEPTION ->write(request [nb_request_in]->_exception );
198	in_WRITE_QUEUE_IN_NO_SEQUENCE ->write(request [nb_request_in]->_no_sequence );
199	in_WRITE_QUEUE_IN_ADDRESS ->write(request [nb_request_in]->_address );
200	}
201	in_WRITE_QUEUE_OUT_ACK ->write((rand()%100)<percent_transaction_write_queue_out);
202	in_GPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_gpr);
203	in_SPR_WRITE_ACK [0] ->write((rand()%100)<percent_transaction_spr);
204
205	SC_CYCLE(0);
206
207	// ======================================================================
208	// ======================================================================
209	// ======================================================================
210	if (out_GPR_WRITE_VAL [0]->read() and
211	in_GPR_WRITE_ACK [0]->read())
212	{
213	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_GPR_WRITE_OOO_ENGINE_ID[0]->read():0;
214	Tgeneral_address_t num_reg = out_GPR_WRITE_NUM_REG [0]->read();
215	Tgeneral_data_t data = out_GPR_WRITE_DATA [0]->read();
216
217	LABEL(" * Accepted GPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
218
219	TEST(bool , gpr_val [ooo_engine_id][num_reg], 0);
220	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
221	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
222
223	gpr_val [ooo_engine_id][num_reg] = 1;
224	}
225
226	// ======================================================================
227	// ======================================================================
228	// ======================================================================
229	if (out_SPR_WRITE_VAL [0]->read() and
230	in_SPR_WRITE_ACK [0]->read())
231	{
232	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_SPR_WRITE_OOO_ENGINE_ID[0]->read():0;
233	Tspecial_address_t num_reg = out_SPR_WRITE_NUM_REG [0]->read();
234	Tspecial_data_t data = out_SPR_WRITE_DATA [0]->read();
235
236	LABEL(" * Accepted SPR_WRITE in register [%d][%d]", ooo_engine_id,num_reg);
237
238	TEST(bool , spr_val [ooo_engine_id][num_reg], 0);
239	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
240	TEST(Tgeneral_data_t, spr [ooo_engine_id][num_reg], data);
241
242	spr_val [ooo_engine_id][num_reg] = 1;
243	}
244
245	// ======================================================================
246	// ======================================================================
247	// ======================================================================
248	for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
249	{
250	Tcontext_t ooo_engine_id = (_param->_have_port_ooo_engine_id)?out_BYPASS_WRITE_OOO_ENGINE_ID[i]->read():0;
251
252	if (out_BYPASS_WRITE_GPR_VAL [i]->read())
253	{
254	Tgeneral_address_t num_reg = out_BYPASS_WRITE_GPR_NUM_REG [i]->read(); // RD
255	Tgeneral_data_t data = out_BYPASS_WRITE_GPR_DATA [i]->read();
256
257	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (GPR)", ooo_engine_id,num_reg);
258
259
260	TEST(bool , gpr_use [ooo_engine_id][num_reg], 1);
261	TEST(Tgeneral_data_t, gpr [ooo_engine_id][num_reg], data);
262	}
263	if (out_BYPASS_WRITE_SPR_VAL [i]->read())
264	{
265	Tspecial_address_t num_reg = out_BYPASS_WRITE_SPR_NUM_REG [i]->read(); // RE
266	Tspecial_data_t data = out_BYPASS_WRITE_SPR_DATA [i]->read();
267
268	LABEL(" * Accepted BYPASS_WRITE in register [%d][%d] (SPR)", ooo_engine_id,num_reg);
269
270	TEST(bool , spr_use [ooo_engine_id][num_reg], 1);
271	TEST(Tspecial_data_t, spr [ooo_engine_id][num_reg], data);
272	}
273	}
274
275	// ======================================================================
276	// ======================================================================
277	// ======================================================================
278	if ( in_WRITE_QUEUE_IN_VAL->read() and
279	out_WRITE_QUEUE_IN_ACK->read())
280	{
281	LABEL(" * Accepted WRITE_QUEUE_IN [%d]",nb_request_in);
282	// std::cout << *request [nb_request_in] << std::endl;
283
284	if (request [nb_request_in]->_write_rd)
285	{
286	gpr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 0;
287	gpr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = 1;
288	gpr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_rd] = request [nb_request_in]->_data_rd;
289	}
290	if (request [nb_request_in]->_write_re)
291	{
292	spr_val [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 0;
293	spr_use [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = 1;
294	spr [request [nb_request_in]->_ooo_engine_id][request [nb_request_in]->_num_reg_re] = request [nb_request_in]->_data_re;
295	}
296	nb_request_in ++;
297	}
298
299	// ======================================================================
300	// ======================================================================
301	// ======================================================================
302	if (out_WRITE_QUEUE_OUT_VAL->read() and
303	in_WRITE_QUEUE_OUT_ACK->read())
304	{
305	Tcontext_t packet;
306	if (_param->_have_port_rob_ptr)
307	packet = out_WRITE_QUEUE_OUT_PACKET_ID->read();
308	else
309	packet = 0;
310
311	LABEL(" * Accepted WRITE_QUEUE_OUT [%d]",packet);
312	// std::cout << *request [packet] << std::endl;
313
314	if (request [packet]->_write_rd)
315	{
316	TEST(bool, gpr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
317	TEST(bool, gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd], 1);
318	gpr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_rd] = 0;
319	}
320	if (request [packet]->_write_re)
321	{
322	TEST(bool, spr_val [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
323	TEST(bool, spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re], 1);
324	spr_use [request [packet]->_ooo_engine_id][request [packet]->_num_reg_re] = 0;
325	}
326
327	if (_param->_have_port_context_id)
328	TEST(Tcontext_t , out_WRITE_QUEUE_OUT_CONTEXT_ID ->read(), request [packet]->_context_id );
329	if (_param->_have_port_front_end_id)
330	TEST(Tcontext_t , out_WRITE_QUEUE_OUT_FRONT_END_ID ->read(), request [packet]->_front_end_id );
331	if (_param->_have_port_ooo_engine_id)
332	TEST(Tcontext_t , out_WRITE_QUEUE_OUT_OOO_ENGINE_ID->read(), request [packet]->_ooo_engine_id);
333
334	//TEST(Toperation_t , out_WRITE_QUEUE_OUT_OPERATION ->read(), request [packet]->_operation );
335	//TEST(Ttype_t , out_WRITE_QUEUE_OUT_TYPE ->read(), request [packet]->_type );
336	TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_FLAGS ->read(), request [packet]->_data_re );
337	TEST(Texception_t , out_WRITE_QUEUE_OUT_EXCEPTION ->read(), request [packet]->_exception );
338	TEST(Tcontrol_t , out_WRITE_QUEUE_OUT_NO_SEQUENCE ->read(), request [packet]->_no_sequence );
339	TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_ADDRESS ->read(), request [packet]->_address );
340	TEST(Tgeneral_data_t, out_WRITE_QUEUE_OUT_DATA ->read(), request [packet]->_data_rd );
341
342	nb_request_out ++;
343	}
344
345	SC_CYCLE(1);
346	}
347
348	for (uint32_t i=0; i<_param->_nb_packet; i++)
349	delete request [i];
350
351	}
352
353	/********************************************************
354	* Simulation - End
355	********************************************************/
356
357	TEST_OK ("");
358
359	sc_stop();
360	delete _time;
361
362	msgInformation(_("<%s> : ............ Stop Simulation\n"),name.c_str());
363	}
364	#endif
365	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/SelfTest/src/top_test.cpp @ 113

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