[73] | 1 | #ifndef morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_write_unit_write_unit_write_queue_Write_queue_h |
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| 2 | #define morpheo_behavioural_core_multi_execute_loop_execute_loop_multi_write_unit_write_unit_write_queue_Write_queue_h |
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| 3 | |
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| 4 | /* |
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| 5 | * $Id: Write_queue.h 81 2008-04-15 18:40:01Z rosiere $ |
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| 6 | * |
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| 7 | * [ Description ] |
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| 8 | * |
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| 9 | */ |
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| 10 | |
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| 11 | #ifdef SYSTEMC |
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| 12 | #include "systemc.h" |
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| 13 | #endif |
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| 14 | |
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| 15 | #include <iostream> |
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| 16 | #include <list> |
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| 17 | #include "Common/include/ToString.h" |
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| 18 | #include "Common/include/Debug.h" |
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| 19 | #include "Behavioural/include/Types.h" |
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| 20 | |
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| 21 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Parameters.h" |
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| 22 | #ifdef STATISTICS |
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| 23 | #include "Behavioural/include/Stat.h" |
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| 24 | #endif |
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| 25 | #include "Behavioural/include/Component.h" |
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| 26 | #ifdef VHDL |
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| 27 | #include "Behavioural/include/Vhdl.h" |
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| 28 | #endif |
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| 29 | #include "Behavioural/include/Usage.h" |
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| 30 | |
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| 31 | namespace morpheo { |
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| 32 | namespace behavioural { |
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| 33 | namespace core { |
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| 34 | namespace multi_execute_loop { |
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| 35 | namespace execute_loop { |
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| 36 | namespace multi_write_unit { |
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| 37 | namespace write_unit { |
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| 38 | namespace write_queue { |
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| 39 | |
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| 40 | class write_queue_entry_t |
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| 41 | { |
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| 42 | public : Tcontext_t _context_id ; |
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| 43 | public : Tcontext_t _front_end_id ; |
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| 44 | public : Tcontext_t _ooo_engine_id; |
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| 45 | public : Tpacket_t _packet_id ; |
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| 46 | //public : Toperation_t _operation ; |
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[77] | 47 | public : Ttype_t _type ; |
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[73] | 48 | public : Tcontrol_t _write_rd ; |
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| 49 | public : Tgeneral_address_t _num_reg_rd ; |
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| 50 | public : Tgeneral_data_t _data_rd ; |
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| 51 | public : Tcontrol_t _write_re ; |
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| 52 | public : Tspecial_address_t _num_reg_re ; |
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| 53 | public : Tspecial_data_t _data_re ; |
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| 54 | public : Texception_t _exception ; |
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| 55 | public : Tcontrol_t _no_sequence ; |
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| 56 | public : Tgeneral_data_t _address ; |
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| 57 | |
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| 58 | public : write_queue_entry_t (Tcontext_t context_id , |
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| 59 | Tcontext_t front_end_id , |
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| 60 | Tcontext_t ooo_engine_id, |
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| 61 | Tpacket_t packet_id , |
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| 62 | //Toperation_t operation , |
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[77] | 63 | Ttype_t type , |
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[73] | 64 | Tcontrol_t write_rd , |
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| 65 | Tgeneral_address_t num_reg_rd , |
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| 66 | Tgeneral_data_t data_rd , |
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| 67 | Tcontrol_t write_re , |
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| 68 | Tspecial_address_t num_reg_re , |
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| 69 | Tspecial_data_t data_re , |
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| 70 | Texception_t exception , |
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| 71 | Tcontrol_t no_sequence , |
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| 72 | Tgeneral_data_t address ) |
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| 73 | { |
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| 74 | _context_id = context_id ; |
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| 75 | _front_end_id = front_end_id ; |
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| 76 | _ooo_engine_id = ooo_engine_id; |
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| 77 | _packet_id = packet_id ; |
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| 78 | //_operation = operation ; |
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[77] | 79 | _type = type ; |
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[73] | 80 | _write_rd = write_rd ; |
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| 81 | _num_reg_rd = num_reg_rd ; |
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| 82 | _data_rd = data_rd ; |
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| 83 | _write_re = write_re ; |
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| 84 | _num_reg_re = num_reg_re ; |
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| 85 | _data_re = data_re ; |
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| 86 | _exception = exception ; |
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| 87 | _no_sequence = no_sequence ; |
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| 88 | _address = address ; |
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| 89 | }; |
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| 90 | }; |
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| 91 | |
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| 92 | |
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| 93 | class Write_queue |
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| 94 | #if SYSTEMC |
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| 95 | : public sc_module |
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| 96 | #endif |
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| 97 | { |
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| 98 | // -----[ fields ]---------------------------------------------------- |
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| 99 | // Parameters |
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| 100 | protected : const std::string _name; |
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| 101 | protected : const Parameters * _param; |
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| 102 | private : const Tusage_t _usage; |
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| 103 | |
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| 104 | #ifdef STATISTICS |
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[74] | 105 | public : Stat * _stat; |
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[73] | 106 | |
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| 107 | private : counter_t * _stat_use_queue; |
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| 108 | private : counter_t * _stat_average_use_queue; |
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| 109 | private : counter_t * _stat_percent_use_queue; |
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| 110 | |
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| 111 | #endif |
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| 112 | |
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| 113 | public : Component * _component; |
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| 114 | private : Interfaces * _interfaces; |
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| 115 | |
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| 116 | #ifdef SYSTEMC |
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| 117 | // ~~~~~[ Interface ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 118 | // Interface |
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| 119 | public : SC_CLOCK * in_CLOCK ; |
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| 120 | public : SC_IN (Tcontrol_t) * in_NRESET ; |
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| 121 | |
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| 122 | // -----[ Interface "Write_queue_in" ]-------------------------------- |
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| 123 | public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_VAL ; |
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| 124 | public : SC_OUT(Tcontrol_t ) * out_WRITE_QUEUE_IN_ACK ; |
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| 125 | public : SC_IN (Tcontext_t ) * in_WRITE_QUEUE_IN_CONTEXT_ID ; |
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| 126 | public : SC_IN (Tcontext_t ) * in_WRITE_QUEUE_IN_FRONT_END_ID ; |
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| 127 | public : SC_IN (Tcontext_t ) * in_WRITE_QUEUE_IN_OOO_ENGINE_ID; |
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| 128 | public : SC_IN (Tpacket_t ) * in_WRITE_QUEUE_IN_PACKET_ID ; |
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| 129 | //public : SC_IN (Toperation_t ) * in_WRITE_QUEUE_IN_OPERATION ; |
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[77] | 130 | public : SC_IN (Ttype_t ) * in_WRITE_QUEUE_IN_TYPE ; |
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[73] | 131 | public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_WRITE_RD ; |
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| 132 | public : SC_IN (Tgeneral_address_t) * in_WRITE_QUEUE_IN_NUM_REG_RD ; |
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| 133 | public : SC_IN (Tgeneral_data_t ) * in_WRITE_QUEUE_IN_DATA_RD ; |
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| 134 | public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_WRITE_RE ; |
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| 135 | public : SC_IN (Tspecial_address_t) * in_WRITE_QUEUE_IN_NUM_REG_RE ; |
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| 136 | public : SC_IN (Tspecial_data_t ) * in_WRITE_QUEUE_IN_DATA_RE ; |
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| 137 | public : SC_IN (Texception_t ) * in_WRITE_QUEUE_IN_EXCEPTION ; |
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| 138 | public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_IN_NO_SEQUENCE ; |
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| 139 | public : SC_IN (Tgeneral_data_t ) * in_WRITE_QUEUE_IN_ADDRESS ; |
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| 140 | |
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| 141 | // -----[ Interface "Write_queue_out" ]------------------------------- |
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| 142 | public : SC_OUT(Tcontrol_t ) * out_WRITE_QUEUE_OUT_VAL ; |
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| 143 | public : SC_IN (Tcontrol_t ) * in_WRITE_QUEUE_OUT_ACK ; |
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| 144 | public : SC_OUT(Tcontext_t ) * out_WRITE_QUEUE_OUT_CONTEXT_ID ; |
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| 145 | public : SC_OUT(Tcontext_t ) * out_WRITE_QUEUE_OUT_FRONT_END_ID ; |
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| 146 | public : SC_OUT(Tcontext_t ) * out_WRITE_QUEUE_OUT_OOO_ENGINE_ID; |
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| 147 | public : SC_OUT(Tpacket_t ) * out_WRITE_QUEUE_OUT_PACKET_ID ; |
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| 148 | //public : SC_OUT(Toperation_t ) * out_WRITE_QUEUE_OUT_OPERATION ; |
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| 149 | //public : SC_OUT(Ttype_t ) * out_WRITE_QUEUE_OUT_TYPE ; |
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| 150 | public : SC_OUT(Tspecial_data_t ) * out_WRITE_QUEUE_OUT_FLAGS ; |
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| 151 | public : SC_OUT(Texception_t ) * out_WRITE_QUEUE_OUT_EXCEPTION ; |
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| 152 | public : SC_OUT(Tcontrol_t ) * out_WRITE_QUEUE_OUT_NO_SEQUENCE ; |
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| 153 | public : SC_OUT(Tgeneral_data_t ) * out_WRITE_QUEUE_OUT_ADDRESS ; |
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| 154 | |
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| 155 | // -----[ Interface "gpr_write" ]------------------------------------- |
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| 156 | public : SC_OUT(Tcontrol_t ) ** out_GPR_WRITE_VAL ; |
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| 157 | public : SC_IN (Tcontrol_t ) ** in_GPR_WRITE_ACK ; |
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| 158 | public : SC_OUT(Tcontext_t ) ** out_GPR_WRITE_OOO_ENGINE_ID ; |
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| 159 | public : SC_OUT(Tgeneral_address_t) ** out_GPR_WRITE_NUM_REG ; |
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| 160 | public : SC_OUT(Tgeneral_data_t ) ** out_GPR_WRITE_DATA ; |
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| 161 | |
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| 162 | // -----[ Interface "spr_write" ]------------------------------------- |
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| 163 | public : SC_OUT(Tcontrol_t ) ** out_SPR_WRITE_VAL ; |
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| 164 | public : SC_IN (Tcontrol_t ) ** in_SPR_WRITE_ACK ; |
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| 165 | public : SC_OUT(Tcontext_t ) ** out_SPR_WRITE_OOO_ENGINE_ID ; |
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| 166 | public : SC_OUT(Tspecial_address_t) ** out_SPR_WRITE_NUM_REG ; |
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| 167 | public : SC_OUT(Tspecial_data_t ) ** out_SPR_WRITE_DATA ; |
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| 168 | |
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| 169 | // -----[ Interface "bypass_write" ]---------------------------------- |
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| 170 | public : SC_OUT(Tcontext_t ) ** out_BYPASS_WRITE_OOO_ENGINE_ID ; |
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| 171 | public : SC_OUT(Tcontrol_t ) ** out_BYPASS_WRITE_GPR_VAL ; |
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| 172 | public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_WRITE_GPR_NUM_REG ; // RD |
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| 173 | public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_WRITE_GPR_DATA ; |
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| 174 | public : SC_OUT(Tcontrol_t ) ** out_BYPASS_WRITE_SPR_VAL ; |
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| 175 | public : SC_OUT(Tspecial_address_t) ** out_BYPASS_WRITE_SPR_NUM_REG ; // RE |
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| 176 | public : SC_OUT(Tspecial_data_t ) ** out_BYPASS_WRITE_SPR_DATA ; |
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| 177 | |
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| 178 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 179 | |
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| 180 | // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[75] | 181 | protected : std::list<write_queue_entry_t *> * _queue; |
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[73] | 182 | |
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| 183 | // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 184 | Tcontrol_t internal_WRITE_QUEUE_IN_ACK; |
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| 185 | Tcontrol_t internal_WRITE_QUEUE_OUT_VAL; |
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| 186 | Tcontrol_t internal_GPR_WRITE_VAL; |
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| 187 | Tcontrol_t internal_SPR_WRITE_VAL; |
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| 188 | #endif |
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| 189 | |
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| 190 | // -----[ Methods ]--------------------------------------------------- |
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| 191 | |
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| 192 | #ifdef SYSTEMC |
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| 193 | SC_HAS_PROCESS (Write_queue); |
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| 194 | #endif |
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| 195 | public : Write_queue |
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| 196 | ( |
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| 197 | #ifdef SYSTEMC |
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| 198 | sc_module_name name, |
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| 199 | #else |
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| 200 | std::string name, |
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| 201 | #endif |
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| 202 | #ifdef STATISTICS |
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| 203 | morpheo::behavioural::Parameters_Statistics * param_statistics, |
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| 204 | #endif |
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| 205 | Parameters * param, |
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| 206 | morpheo::behavioural::Tusage_t usage=USE_ALL |
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| 207 | ); |
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| 208 | public : ~Write_queue (void); |
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| 209 | |
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| 210 | private : void allocation (void); |
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| 211 | private : void deallocation (void); |
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| 212 | |
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| 213 | #ifdef SYSTEMC |
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| 214 | public : void transition (void); |
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| 215 | public : void genMoore (void); |
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| 216 | #endif |
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| 217 | #ifdef STATISTICS |
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[74] | 218 | public : void statistics_declaration (morpheo::behavioural::Parameters_Statistics * param_statistics); |
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[73] | 219 | #endif |
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| 220 | |
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| 221 | #if VHDL |
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| 222 | public : void vhdl (void); |
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| 223 | private : void vhdl_declaration (Vhdl * & vhdl); |
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| 224 | private : void vhdl_body (Vhdl * & vhdl); |
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| 225 | #endif |
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| 226 | |
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| 227 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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| 228 | private : void end_cycle (void); |
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| 229 | #endif |
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| 230 | }; |
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| 231 | |
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| 232 | }; // end namespace write_queue |
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| 233 | }; // end namespace write_unit |
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| 234 | }; // end namespace multi_write_unit |
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| 235 | }; // end namespace execute_loop |
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| 236 | }; // end namespace multi_execute_loop |
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| 237 | }; // end namespace core |
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| 238 | |
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| 239 | }; // end namespace behavioural |
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| 240 | }; // end namespace morpheo |
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| 241 | |
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| 242 | #endif |
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