1 | /* |
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2 | * $Id: Write_queue_allocation.cpp 136 2009-10-20 18:52:15Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | */ |
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7 | |
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8 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h" |
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9 | #include "Behavioural/include/Allocation.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_execute_loop { |
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15 | namespace execute_loop { |
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16 | namespace multi_write_unit { |
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17 | namespace write_unit { |
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18 | namespace write_queue { |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Write_queue::allocation" |
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23 | void Write_queue::allocation (void) |
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24 | { |
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25 | log_printf(FUNC,Write_queue,FUNCTION,"Begin"); |
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26 | |
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27 | _component = new Component (_usage); |
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28 | |
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29 | Entity * entity = _component->set_entity (_name |
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30 | ,_param->_type |
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31 | #ifdef POSITION |
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32 | ,COMBINATORY |
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33 | #endif |
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34 | ); |
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35 | |
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36 | _interfaces = entity->set_interfaces(); |
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37 | |
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38 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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39 | |
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40 | Interface * interface = _interfaces->set_interface("" |
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41 | #ifdef POSITION |
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42 | ,IN |
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43 | ,SOUTH, |
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44 | "Generalist interface" |
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45 | #endif |
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46 | ); |
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47 | |
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48 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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49 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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50 | |
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51 | // -----[ Interface "Write_queue_in" ]-------------------------------- |
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52 | { |
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53 | ALLOC0_INTERFACE_BEGIN ("write_queue_in", IN, WEST, "Input of write_queue"); |
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54 | |
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55 | ALLOC0_VALACK_IN ( in_WRITE_QUEUE_IN_VAL,VAL); |
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56 | ALLOC0_VALACK_OUT(out_WRITE_QUEUE_IN_ACK,ACK); |
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57 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); |
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58 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); |
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59 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); |
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60 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); |
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61 | // ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); |
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62 | // ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); |
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63 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_CANCEL ,"cancel" ,Tcontrol_t ,1 ); |
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64 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); |
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65 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); |
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66 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); |
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67 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); |
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68 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register ); |
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69 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data ); |
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70 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); |
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71 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); |
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72 | ALLOC0_SIGNAL_IN ( in_WRITE_QUEUE_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); |
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73 | |
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74 | ALLOC0_INTERFACE_END(); |
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75 | } |
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76 | |
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77 | // -----[ Interface "Write_queue_out" ]------------------------------- |
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78 | { |
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79 | ALLOC0_INTERFACE_BEGIN("write_queue_out", OUT, EAST, "Output of write_queue"); |
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80 | |
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81 | ALLOC0_VALACK_OUT(out_WRITE_QUEUE_OUT_VAL,VAL); |
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82 | ALLOC0_VALACK_IN ( in_WRITE_QUEUE_OUT_ACK,ACK); |
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83 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); |
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84 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); |
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85 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id); |
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86 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); |
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87 | // ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); |
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88 | // ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); |
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89 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_CANCEL ,"cancel" ,Tcontrol_t ,1 ); |
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90 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data ); |
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91 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); |
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92 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); |
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93 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address); |
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94 | ALLOC0_SIGNAL_OUT(out_WRITE_QUEUE_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data ); |
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95 | |
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96 | ALLOC0_INTERFACE_END(); |
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97 | } |
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98 | |
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99 | // -----[ Interface "gpr_write" ]------------------------------------- |
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100 | { |
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101 | ALLOC1_INTERFACE_BEGIN("gpr_write", OUT, SOUTH ,"Output of write_queue", _param->_nb_gpr_write); |
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102 | |
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103 | ALLOC1_VALACK_OUT(out_GPR_WRITE_VAL,VAL); |
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104 | ALLOC1_VALACK_IN ( in_GPR_WRITE_ACK,ACK); |
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105 | ALLOC1_SIGNAL_OUT(out_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); |
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106 | ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register); |
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107 | ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data ); |
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108 | |
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109 | ALLOC1_INTERFACE_END(_param->_nb_gpr_write); |
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110 | } |
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111 | |
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112 | // -----[ Interface "spr_write" ]------------------------------------- |
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113 | { |
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114 | ALLOC1_INTERFACE_BEGIN("spr_write", OUT, SOUTH ,"Output of write_queue", _param->_nb_spr_write); |
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115 | |
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116 | ALLOC1_VALACK_OUT(out_SPR_WRITE_VAL,VAL); |
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117 | ALLOC1_VALACK_IN ( in_SPR_WRITE_ACK,ACK); |
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118 | ALLOC1_SIGNAL_OUT(out_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); |
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119 | ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register); |
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120 | ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data ); |
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121 | |
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122 | ALLOC1_INTERFACE_END(_param->_nb_spr_write); |
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123 | } |
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124 | |
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125 | // -----[ Interface "bypass_write" ]---------------------------------- |
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126 | { |
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127 | ALLOC1_INTERFACE_BEGIN("bypass_write", OUT, NORTH ,"Output of internal write_queue", _param->_nb_bypass_write); |
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128 | |
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129 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id ); |
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130 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1 ); |
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131 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_register); |
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132 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_data ); |
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133 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1 ); |
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134 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register); |
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135 | ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data ); |
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136 | |
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137 | ALLOC1_INTERFACE_END(_param->_nb_bypass_write); |
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138 | } |
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139 | |
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140 | // ~~~~~[ Register ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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141 | |
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142 | _queue = new std::list<write_queue_entry_t *>; |
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143 | |
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144 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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145 | #ifdef VHDL |
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146 | if (usage_is_set(_usage,USE_VHDL)) |
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147 | { |
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148 | _param_queue = new morpheo::behavioural::generic::queue::Parameters |
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149 | (_param->_size_queue, |
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150 | _param->_size_internal_queue, |
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151 | _param->_nb_bypass_write, |
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152 | false, |
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153 | false |
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154 | ); |
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155 | |
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156 | std::string queue_name = _name + "_queue"; |
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157 | _component_queue = new morpheo::behavioural::generic::queue::Queue |
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158 | (queue_name.c_str() |
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159 | #ifdef STATISTICS |
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160 | ,NULL |
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161 | #endif |
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162 | ,_param_queue |
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163 | ,USE_VHDL); |
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164 | |
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165 | _component->set_component(_component_queue->_component |
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166 | #ifdef POSITION |
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167 | , 50, 50, 50, 50 |
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168 | #endif |
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169 | , INSTANCE_LIBRARY |
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170 | ); |
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171 | } |
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172 | #endif |
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173 | |
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174 | #ifdef POSITION |
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175 | if (usage_is_set(_usage,USE_POSITION)) |
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176 | _component->generate_file(); |
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177 | #endif |
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178 | |
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179 | log_printf(FUNC,Write_queue,FUNCTION,"End"); |
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180 | }; |
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181 | |
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182 | }; // end namespace write_queue |
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183 | }; // end namespace write_unit |
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184 | }; // end namespace multi_write_unit |
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185 | }; // end namespace execute_loop |
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186 | }; // end namespace multi_execute_loop |
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187 | }; // end namespace core |
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188 | |
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189 | }; // end namespace behavioural |
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190 | }; // end namespace morpheo |
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