| 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Write_queue_genMealy_write.cpp 136 2009-10-20 18:52:15Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_execute_loop { |
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| 15 | namespace execute_loop { |
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| 16 | namespace multi_write_unit { |
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| 17 | namespace write_unit { |
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| 18 | namespace write_queue { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Write_queue::genMealy_write" |
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| 23 | void Write_queue::genMealy_write (void) |
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| 24 | { |
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| 25 | log_begin(Write_queue,FUNCTION); |
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| 26 | log_function(Write_queue,FUNCTION,_name.c_str()); |
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| 27 | |
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| 28 | if (PORT_READ(in_NRESET)) |
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| 29 | { |
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| 30 | // -----[ Interface "bypass_write" ]---------------------------------- |
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| 31 | // in genMoore |
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| 32 | // -----[ Interface "Write_queue_in" ]-------------------------------- |
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| 33 | // in genMoore |
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| 34 | |
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| 35 | bool val = not _queue->empty(); |
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| 36 | Tcontrol_t write_rd = val and _queue->front()->_write_rd; |
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| 37 | Tcontrol_t write_re = val and _queue->front()->_write_re; |
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| 38 | |
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| 39 | // -----[ Interface "gpr_write" ]------------------------------------- |
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| 40 | // -----[ Interface "spr_write" ]------------------------------------- |
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| 41 | { |
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| 42 | internal_GPR_WRITE_VAL = val and write_rd; |
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| 43 | internal_SPR_WRITE_VAL = val and write_re; |
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| 44 | |
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| 45 | PORT_WRITE(out_GPR_WRITE_VAL [0], internal_GPR_WRITE_VAL); |
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| 46 | PORT_WRITE(out_SPR_WRITE_VAL [0], internal_SPR_WRITE_VAL); |
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| 47 | |
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| 48 | write_rd = (write_rd)?(not PORT_READ(in_GPR_WRITE_ACK [0])):0; |
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| 49 | write_re = (write_re)?(not PORT_READ(in_SPR_WRITE_ACK [0])):0; |
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| 50 | |
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| 51 | if (val) |
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| 52 | { |
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| 53 | if (_param->_have_port_ooo_engine_id) |
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| 54 | { |
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| 55 | PORT_WRITE(out_GPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id); |
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| 56 | PORT_WRITE(out_SPR_WRITE_OOO_ENGINE_ID [0], _queue->front()->_ooo_engine_id); |
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| 57 | } |
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| 58 | PORT_WRITE(out_GPR_WRITE_NUM_REG [0], _queue->front()->_num_reg_rd); |
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| 59 | PORT_WRITE(out_GPR_WRITE_DATA [0], _queue->front()->_data_rd ); |
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| 60 | PORT_WRITE(out_SPR_WRITE_NUM_REG [0], _queue->front()->_num_reg_re); |
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| 61 | PORT_WRITE(out_SPR_WRITE_DATA [0], _queue->front()->_data_re ); |
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| 62 | } |
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| 63 | } |
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| 64 | |
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| 65 | // -----[ Interface "Write_queue_out" ]-------------------------------- |
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| 66 | { |
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| 67 | Texception_t load_speculative = (_queue->front()->_exception == EXCEPTION_MEMORY_LOAD_SPECULATIVE); |
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| 68 | |
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| 69 | internal_WRITE_QUEUE_OUT_VAL = ((val ) and |
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| 70 | (not load_speculative) and |
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| 71 | (not write_rd ) and |
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| 72 | (not write_re )); |
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| 73 | |
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| 74 | PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL); |
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| 75 | |
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| 76 | if (internal_WRITE_QUEUE_OUT_VAL) |
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| 77 | { |
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| 78 | if (_param->_have_port_context_id) |
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| 79 | PORT_WRITE(out_WRITE_QUEUE_OUT_CONTEXT_ID , _queue->front()->_context_id ); |
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| 80 | if (_param->_have_port_front_end_id) |
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| 81 | PORT_WRITE(out_WRITE_QUEUE_OUT_FRONT_END_ID , _queue->front()->_front_end_id ); |
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| 82 | if (_param->_have_port_ooo_engine_id) |
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| 83 | PORT_WRITE(out_WRITE_QUEUE_OUT_OOO_ENGINE_ID, _queue->front()->_ooo_engine_id); |
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| 84 | if (_param->_have_port_rob_ptr ) |
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| 85 | PORT_WRITE(out_WRITE_QUEUE_OUT_PACKET_ID , _queue->front()->_packet_id ); |
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| 86 | // PORT_WRITE(out_WRITE_QUEUE_OUT_OPERATION , _queue->front()->_operation ); |
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| 87 | // PORT_WRITE(out_WRITE_QUEUE_OUT_TYPE , _queue->front()->_type ); |
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| 88 | PORT_WRITE(out_WRITE_QUEUE_OUT_CANCEL , _queue->front()->_cancel ); |
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| 89 | PORT_WRITE(out_WRITE_QUEUE_OUT_FLAGS , _queue->front()->_data_re ); |
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| 90 | PORT_WRITE(out_WRITE_QUEUE_OUT_EXCEPTION , _queue->front()->_exception ); |
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| 91 | PORT_WRITE(out_WRITE_QUEUE_OUT_NO_SEQUENCE , _queue->front()->_no_sequence ); |
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| 92 | PORT_WRITE(out_WRITE_QUEUE_OUT_ADDRESS , _queue->front()->_address ); |
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| 93 | PORT_WRITE(out_WRITE_QUEUE_OUT_DATA , _queue->front()->_data_rd ); |
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| 94 | } |
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| 95 | } |
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| 96 | } |
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| 97 | else |
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| 98 | { |
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| 99 | internal_WRITE_QUEUE_OUT_VAL = 0; |
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| 100 | } |
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| 101 | |
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| 102 | PORT_WRITE(out_WRITE_QUEUE_OUT_VAL, internal_WRITE_QUEUE_OUT_VAL); |
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| 103 | |
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| 104 | log_end(Write_queue,FUNCTION); |
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| 105 | }; |
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| 106 | |
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| 107 | }; // end namespace write_queue |
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| 108 | }; // end namespace write_unit |
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| 109 | }; // end namespace multi_write_unit |
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| 110 | }; // end namespace execute_loop |
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| 111 | }; // end namespace multi_execute_loop |
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| 112 | }; // end namespace core |
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| 113 | |
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| 114 | }; // end namespace behavioural |
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| 115 | }; // end namespace morpheo |
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| 116 | #endif |
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