[73] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id: Write_queue_vhdl_body.cpp 103 2009-01-16 16:55:32Z moulu $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/include/Write_queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_execute_loop { |
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| 15 | namespace execute_loop { |
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| 16 | namespace multi_write_unit { |
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| 17 | namespace write_unit { |
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| 18 | namespace write_queue { |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Write_queue::vhdl_body" |
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| 23 | void Write_queue::vhdl_body (Vhdl * & vhdl) |
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| 24 | { |
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| 25 | log_printf(FUNC,Write_queue,FUNCTION,"Begin"); |
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| 26 | vhdl->set_body (""); |
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[103] | 27 | vhdl->set_comment(0,""); |
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| 28 | vhdl->set_comment(0,"-----------------------------------"); |
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| 29 | vhdl->set_comment(0,"-- Instance queue "); |
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| 30 | vhdl->set_comment(0,"-----------------------------------"); |
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| 31 | vhdl->set_comment(0,""); |
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| 32 | |
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| 33 | vhdl->set_body (0,"instance_"+_name+"_queue : "+_name+"_queue"); |
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| 34 | vhdl->set_body (0,"port map ("); |
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| 35 | vhdl->set_body (1," in_CLOCK \t=>\t in_CLOCK "); |
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| 36 | vhdl->set_body (1,", in_NRESET \t=>\t in_NRESET"); |
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| 37 | vhdl->set_body (1,", in_INSERT_VAL \t=>\tsig_QUEUE_INSERT_VAL"); |
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| 38 | vhdl->set_body (1,",out_INSERT_ACK \t=>\tsig_QUEUE_INSERT_ACK"); |
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| 39 | vhdl->set_body (1,", in_INSERT_DATA \t=>\tsig_QUEUE_INSERT_DATA"); |
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| 40 | vhdl->set_body (1,",out_RETIRE_VAL \t=>\tsig_QUEUE_RETIRE_VAL"); |
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| 41 | vhdl->set_body (1,", in_RETIRE_ACK \t=>\tsig_QUEUE_RETIRE_ACK"); |
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| 42 | vhdl->set_body (1,",out_RETIRE_DATA \t=>\tsig_QUEUE_RETIRE_DATA"); |
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| 43 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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| 44 | { |
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| 45 | vhdl->set_body (1,",out_SLOT_"+toString(i)+"_VAL \t=>\tsig_QUEUE_SLOT_"+toString(i)+"_VAL"); |
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| 46 | vhdl->set_body (1,",out_SLOT_"+toString(i)+"_DATA \t=>\tsig_QUEUE_SLOT_"+toString(i)+"_DATA"); |
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| 47 | } |
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| 48 | vhdl->set_body (0,");"); |
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| 49 | |
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| 50 | vhdl->set_body (0,""); |
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| 51 | |
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| 52 | |
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| 53 | vhdl->set_comment(0,""); |
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| 54 | vhdl->set_comment(0,"-----------------------------------"); |
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| 55 | vhdl->set_comment(0,"-- Insides "); |
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| 56 | vhdl->set_comment(0,"-----------------------------------"); |
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| 57 | vhdl->set_comment(0,""); |
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| 58 | |
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| 59 | vhdl->set_body (0,"write_rd_re_bis: process (in_CLOCK)"); |
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| 60 | vhdl->set_body (0,"begin -- process write rd/re bis"); |
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| 61 | vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); |
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| 62 | // #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 63 | // vhdl->set_body (2,"if (in_NRESET = '0') then"); |
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| 64 | // vhdl->set_body (2,"reg_GPR_WRITE <= '0';"); |
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| 65 | // vhdl->set_body (2,"reg_SPR_WRITE <= '0';"); |
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| 66 | // vhdl->set_body (2,"else"); |
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| 67 | // #endif |
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| 68 | vhdl->set_body (2,"reg_UPDATE <= (in_WRITE_QUEUE_OUT_ACK and sig_WRITE_QUEUE_OUT_VAL) or (not sig_QUEUE_RETIRE_VAL);"); |
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| 69 | |
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| 70 | vhdl->set_body (2,"if (sig_GPR_WRITE_0_VAL = '1' and in_GPR_WRITE_0_ACK = '1') then"); |
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| 71 | vhdl->set_body (3,"reg_GPR_WRITE <= '0';"); |
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| 72 | vhdl->set_body (2,"else"); |
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| 73 | vhdl->set_body (3,"reg_GPR_WRITE <= sig_GPR_WRITE;"); |
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| 74 | vhdl->set_body (2,"end if;"); |
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| 75 | |
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| 76 | vhdl->set_body (2,"if (sig_SPR_WRITE_0_VAL = '1' and in_SPR_WRITE_0_ACK = '1') then"); |
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| 77 | vhdl->set_body (3,"reg_SPR_WRITE <= '0';"); |
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| 78 | vhdl->set_body (2,"else"); |
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| 79 | vhdl->set_body (3,"reg_SPR_WRITE <= sig_SPR_WRITE;"); |
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| 80 | vhdl->set_body (2,"end if;"); |
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| 81 | |
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| 82 | // #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 83 | // vhdl->set_body (2,"end if;"); |
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| 84 | // #endif |
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| 85 | vhdl->set_body (1,"end if;"); |
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| 86 | vhdl->set_body (0,"end process write_rd_re_bis;"); |
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| 87 | |
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| 88 | vhdl->set_body (0,"sig_GPR_WRITE <= sig_WRITE_RD when (reg_UPDATE = '1') else reg_GPR_WRITE;"); |
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| 89 | vhdl->set_body (0,"sig_SPR_WRITE <= sig_WRITE_RE when (reg_UPDATE = '1') else reg_SPR_WRITE;"); |
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| 90 | vhdl->set_body (0,"sig_GPR_WRITE_0_VAL <= sig_QUEUE_RETIRE_VAL and sig_GPR_WRITE;"); |
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| 91 | vhdl->set_body (0,"sig_SPR_WRITE_0_VAL <= sig_QUEUE_RETIRE_VAL and sig_SPR_WRITE;"); |
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| 92 | vhdl->set_body (0,"sig_DELETE_QUEUE_FRONT <= sig_QUEUE_RETIRE_VAL and not sig_GPR_WRITE and not sig_SPR_WRITE when (sig_WRITE_QUEUE_OUT_EXCEPTION = "+toString(EXCEPTION_MEMORY_LOAD_SPECULATIVE)+") else '0';"); |
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| 93 | vhdl->set_body (0,"sig_WRITE_QUEUE_OUT_VAL <= sig_QUEUE_RETIRE_VAL and not sig_DELETE_QUEUE_FRONT and not sig_GPR_WRITE and not sig_SPR_WRITE;"); |
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| 94 | vhdl->set_body (0,"sig_QUEUE_RETIRE_ACK <= sig_DELETE_QUEUE_FRONT or (in_WRITE_QUEUE_OUT_ACK and sig_WRITE_QUEUE_OUT_VAL);"); |
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| 95 | |
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| 96 | if (_param->_nb_bypass_write > 0) |
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| 97 | { |
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| 98 | vhdl->set_body (0,"sig_BYPASS_WRITE_0_GPR_VAL <= sig_GPR_WRITE_0_VAL;"); |
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| 99 | vhdl->set_body (0,"sig_BYPASS_WRITE_0_SPR_VAL <= sig_SPR_WRITE_0_VAL;"); |
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| 100 | } |
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| 101 | |
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| 102 | for (uint32_t i=1; i<_param->_nb_bypass_write; i++) |
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| 103 | { |
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| 104 | vhdl->set_body (0,"sig_BYPASS_WRITE_"+toString(i)+"_GPR_VAL <= sig_QUEUE_SLOT_"+toString(i)+"_VAL and sig_BYPASS_WRITE_"+toString(i)+"_WRITE_RD;"); |
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| 105 | vhdl->set_body (0,"sig_BYPASS_WRITE_"+toString(i)+"_SPR_VAL <= sig_QUEUE_SLOT_"+toString(i)+"_VAL and sig_BYPASS_WRITE_"+toString(i)+"_WRITE_RE;"); |
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| 106 | } |
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| 107 | |
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| 108 | vhdl->set_body (0,""); |
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| 109 | |
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| 110 | |
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| 111 | vhdl->set_comment(0,""); |
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| 112 | vhdl->set_comment(0,"-----------------------------------"); |
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| 113 | vhdl->set_comment(0,"-- Input Buffer "); |
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| 114 | vhdl->set_comment(0,"-----------------------------------"); |
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| 115 | vhdl->set_comment(0,""); |
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| 116 | |
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| 117 | { |
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| 118 | uint32_t min = 0; |
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| 119 | uint32_t max, size; |
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| 120 | |
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| 121 | if(_param->_have_port_context_id ) |
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| 122 | { |
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| 123 | size = _param->_size_context_id; |
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| 124 | max = min-1+size; |
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| 125 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_CONTEXT_ID;"); |
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| 126 | min = max+1; |
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| 127 | } |
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| 128 | if(_param->_have_port_front_end_id ) |
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| 129 | { |
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| 130 | size = _param->_size_front_end_id; |
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| 131 | max = min-1+size; |
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| 132 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_FRONT_END_ID;"); |
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| 133 | min = max+1; |
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| 134 | } |
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| 135 | if(_param->_have_port_ooo_engine_id ) |
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| 136 | { |
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| 137 | size = _param->_size_ooo_engine_id; |
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| 138 | max = min-1+size; |
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| 139 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_OOO_ENGINE_ID;"); |
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| 140 | min = max+1; |
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| 141 | } |
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| 142 | if(_param->_have_port_rob_ptr) |
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| 143 | { |
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| 144 | size = _param->_size_rob_ptr; |
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| 145 | max = min-1+size; |
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| 146 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_PACKET_ID;"); |
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| 147 | min = max+1; |
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| 148 | } |
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| 149 | |
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| 150 | size = 1; |
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| 151 | max = min-1+size; |
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| 152 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_WRITE_RD;"); |
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| 153 | min = max+1; |
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| 154 | |
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| 155 | size = _param->_size_general_register; |
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| 156 | max = min-1+size; |
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| 157 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_NUM_REG_RD;"); |
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| 158 | min = max+1; |
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| 159 | |
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| 160 | size = _param->_size_general_data; |
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| 161 | max = min-1+size; |
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| 162 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_DATA_RD;"); |
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| 163 | min = max+1; |
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| 164 | |
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| 165 | size = 1; |
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| 166 | max = min-1+size; |
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| 167 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_WRITE_RE;"); |
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| 168 | min = max+1; |
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| 169 | |
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| 170 | size = _param->_size_special_register; |
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| 171 | max = min-1+size; |
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| 172 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_NUM_REG_RE;"); |
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| 173 | min = max+1; |
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| 174 | |
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| 175 | size = _param->_size_special_data; |
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| 176 | max = min-1+size; |
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| 177 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_DATA_RE;"); |
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| 178 | min = max+1; |
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| 179 | |
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| 180 | size = _param->_size_exception; |
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| 181 | max = min-1+size; |
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| 182 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_EXCEPTION;"); |
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| 183 | min = max+1; |
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| 184 | |
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| 185 | size = 1; |
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| 186 | max = min-1+size; |
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| 187 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_NO_SEQUENCE;"); |
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| 188 | min = max+1; |
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| 189 | |
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| 190 | size = _param->_size_instruction_address; |
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| 191 | max = min-1+size; |
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| 192 | vhdl->set_body (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_ADDRESS;"); |
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| 193 | min = max+1; |
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| 194 | } |
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| 195 | |
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| 196 | vhdl->set_body (0,""); |
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| 197 | |
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| 198 | |
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| 199 | vhdl->set_comment(0,""); |
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| 200 | vhdl->set_comment(0,"-----------------------------------"); |
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| 201 | vhdl->set_comment(0,"-- Output Buffer "); |
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| 202 | vhdl->set_comment(0,"-----------------------------------"); |
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| 203 | vhdl->set_comment(0,""); |
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| 204 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_VAL <= sig_WRITE_QUEUE_OUT_VAL;"); |
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| 205 | if(_param->_have_port_context_id) |
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| 206 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_CONTEXT_ID <= sig_WRITE_QUEUE_OUT_CONTEXT_ID ;"); |
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| 207 | if(_param->_have_port_front_end_id) |
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| 208 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_FRONT_END_ID <= sig_WRITE_QUEUE_OUT_FRONT_END_ID ;"); |
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| 209 | if(_param->_have_port_ooo_engine_id) |
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| 210 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID <= sig_WRITE_QUEUE_OUT_OOO_ENGINE_ID;"); |
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| 211 | if(_param->_have_port_rob_ptr) |
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| 212 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_PACKET_ID <= sig_WRITE_QUEUE_OUT_PACKET_ID ;"); |
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| 213 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_FLAGS <= sig_WRITE_QUEUE_OUT_FLAGS ;"); |
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| 214 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_EXCEPTION <= sig_WRITE_QUEUE_OUT_EXCEPTION ;"); |
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| 215 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_NO_SEQUENCE <= sig_WRITE_QUEUE_OUT_NO_SEQUENCE ;"); |
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| 216 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_ADDRESS <= sig_WRITE_QUEUE_OUT_ADDRESS ;"); |
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| 217 | vhdl->set_body (0,"out_WRITE_QUEUE_OUT_DATA <= sig_WRITE_QUEUE_OUT_DATA ;"); |
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| 218 | vhdl->set_body (""); |
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| 219 | |
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| 220 | vhdl->set_body (0,"out_GPR_WRITE_0_VAL <= sig_GPR_WRITE_0_VAL;"); |
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| 221 | if(_param->_have_port_ooo_engine_id) |
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| 222 | vhdl->set_body (0,"out_GPR_WRITE_0_OOO_ENGINE_ID <= sig_GPR_WRITE_0_OOO_ENGINE_ID;"); |
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| 223 | vhdl->set_body (0,"out_GPR_WRITE_0_NUM_REG <= sig_GPR_WRITE_0_NUM_REG;"); |
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| 224 | vhdl->set_body (0,"out_GPR_WRITE_0_DATA <= sig_GPR_WRITE_0_DATA;"); |
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| 225 | |
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| 226 | for (uint32_t i=1; i<_param->_nb_gpr_write; i++) |
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| 227 | vhdl->set_body (0,"out_GPR_WRITE_"+toString(i)+"_VAL <= '0';"); |
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| 228 | |
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| 229 | vhdl->set_body (0,"out_SPR_WRITE_0_VAL <= sig_SPR_WRITE_0_VAL;"); |
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| 230 | if(_param->_have_port_ooo_engine_id) |
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| 231 | vhdl->set_body (0,"out_SPR_WRITE_0_OOO_ENGINE_ID <= sig_SPR_WRITE_0_OOO_ENGINE_ID;"); |
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| 232 | vhdl->set_body (0,"out_SPR_WRITE_0_NUM_REG <= sig_SPR_WRITE_0_NUM_REG;"); |
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| 233 | vhdl->set_body (0,"out_SPR_WRITE_0_DATA <= sig_SPR_WRITE_0_DATA;"); |
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| 234 | |
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| 235 | for (uint32_t i=1; i<_param->_nb_spr_write; i++) |
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| 236 | vhdl->set_body (0,"out_SPR_WRITE_"+toString(i)+"_VAL <= '0';"); |
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| 237 | |
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| 238 | vhdl->set_body (""); |
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| 239 | |
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| 240 | for (uint32_t i=0; i<_param->_nb_bypass_write; i++) |
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| 241 | { |
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| 242 | vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL <= sig_BYPASS_WRITE_"+toString(i)+"_GPR_VAL;"); |
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| 243 | vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG <= sig_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG;"); |
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| 244 | vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA <= sig_BYPASS_WRITE_"+toString(i)+"_GPR_DATA;"); |
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| 245 | |
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| 246 | vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL <= sig_BYPASS_WRITE_"+toString(i)+"_SPR_VAL;"); |
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| 247 | vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG <= sig_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG;"); |
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| 248 | vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA <= sig_BYPASS_WRITE_"+toString(i)+"_SPR_DATA;"); |
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| 249 | |
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| 250 | if(_param->_have_port_ooo_engine_id) |
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| 251 | vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID <= sig_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID;"); |
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| 252 | } |
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| 253 | |
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[73] | 254 | log_printf(FUNC,Write_queue,FUNCTION,"End"); |
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| 255 | }; |
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| 256 | |
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| 257 | }; // end namespace write_queue |
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| 258 | }; // end namespace write_unit |
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| 259 | }; // end namespace multi_write_unit |
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| 260 | }; // end namespace execute_loop |
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| 261 | }; // end namespace multi_execute_loop |
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| 262 | }; // end namespace core |
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| 263 | |
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| 264 | }; // end namespace behavioural |
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| 265 | }; // end namespace morpheo |
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| 266 | #endif |
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