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Write_unit_allocation.cpp

Last change on this file was 136, checked in by rosiere, 15 years ago
1) Add new algo in ifetch queue 2) Add Cancel bit 3) new config
Property svn:keywords set to `Id`
File size: 24.6 KB

Line
1	/*
2	* $Id: Write_unit_allocation.cpp 136 2009-10-20 18:52:15Z rosiere $
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/include/Write_unit.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_execute_loop {
15	namespace execute_loop {
16	namespace multi_write_unit {
17	namespace write_unit {
18
19
20
21	#undef FUNCTION
22	#define FUNCTION "Write_unit::allocation"
23	void Write_unit::allocation (
24	#ifdef STATISTICS
25	morpheo::behavioural::Parameters_Statistics * param_statistics
26	#else
27	void
28	#endif
29	)
30	{
31	log_printf(FUNC,Write_unit,FUNCTION,"Begin");
32
33	_component = new Component (_usage);
34
35	Entity * entity = _component->set_entity (_name
36	,_param->_type
37	#ifdef POSITION
38	,COMBINATORY
39	#endif
40	);
41
42	_interfaces = entity->set_interfaces();
43
44	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
45
46	Interface * interface = _interfaces->set_interface(""
47	#ifdef POSITION
48	,IN
49	,SOUTH,
50	"Generalist interface"
51	#endif
52	);
53
54	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
55	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
56
57	// -----[ Interface "write_unit_in" ]--------------------------------
58	{
59	ALLOC0_INTERFACE_BEGIN("write_unit_in", IN, WEST, "Input of write_unit");
60
61	ALLOC0_VALACK_IN ( in_WRITE_UNIT_IN_VAL,VAL);
62	ALLOC0_VALACK_OUT(out_WRITE_UNIT_IN_ACK,ACK);
63	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );
64	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id );
65	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
66	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr );
67	// ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation );
68	// ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type );
69	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_CANCEL ,"cancel" ,Tcontrol_t ,1 );
70	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 );
71	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register );
72	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data );
73	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 );
74	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register );
75	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_special_data );
76	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception );
77	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 );
78	ALLOC0_SIGNAL_IN ( in_WRITE_UNIT_IN_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address);
79
80	ALLOC0_INTERFACE_END();
81	}
82
83	// -----[ Interface "write_unit_out" ]-------------------------------
84	{
85	ALLOC0_INTERFACE_BEGIN("write_unit_out", OUT, EAST, "Output of write_unit");
86
87	ALLOC0_VALACK_OUT(out_WRITE_UNIT_OUT_VAL,VAL);
88	ALLOC0_VALACK_IN ( in_WRITE_UNIT_OUT_ACK,ACK);
89	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id );
90	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id );
91	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id);
92	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr );
93	// ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation );
94	// ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type );
95	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_CANCEL ,"cancel" ,Tcontrol_t ,1 );
96	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data );
97	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception );
98	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 );
99	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_ADDRESS ,"address" ,Taddress_t ,_param->_size_instruction_address);
100	ALLOC0_SIGNAL_OUT(out_WRITE_UNIT_OUT_DATA ,"data" ,Tgeneral_data_t,_param->_size_general_data );
101
102	ALLOC0_INTERFACE_END();
103	}
104
105	// -----[ Interface "gpr_write" ]-------------------------------------
106	{
107	ALLOC1_INTERFACE_BEGIN("gpr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_gpr_write);
108
109	ALLOC1_VALACK_OUT(out_GPR_WRITE_VAL,VAL);
110	ALLOC1_VALACK_IN ( in_GPR_WRITE_ACK,ACK);
111	ALLOC1_SIGNAL_OUT(out_GPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
112	ALLOC1_SIGNAL_OUT(out_GPR_WRITE_NUM_REG ,"num_reg" ,Tgeneral_address_t,_param->_size_general_register);
113	ALLOC1_SIGNAL_OUT(out_GPR_WRITE_DATA ,"data" ,Tgeneral_data_t ,_param->_size_general_data );
114
115	ALLOC1_INTERFACE_END(_param->_nb_gpr_write);
116	}
117
118	// -----[ Interface "spr_write" ]-------------------------------------
119	{
120	ALLOC1_INTERFACE_BEGIN("spr_write", OUT, SOUTH ,"Output of write_unit", _param->_nb_spr_write);
121
122	ALLOC1_VALACK_OUT(out_SPR_WRITE_VAL,VAL);
123	ALLOC1_VALACK_IN ( in_SPR_WRITE_ACK,ACK);
124	ALLOC1_SIGNAL_OUT(out_SPR_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
125	ALLOC1_SIGNAL_OUT(out_SPR_WRITE_NUM_REG ,"num_reg" ,Tspecial_address_t,_param->_size_special_register);
126	ALLOC1_SIGNAL_OUT(out_SPR_WRITE_DATA ,"data" ,Tspecial_data_t ,_param->_size_special_data );
127
128	ALLOC1_INTERFACE_END(_param->_nb_spr_write);
129	}
130
131	// -----[ Interface "bypass_write" ]----------------------------------
132	{
133	ALLOC1_INTERFACE_BEGIN("bypass_write", OUT, NORTH ,"Output of internal write_unit", _param->_nb_bypass_write);
134
135	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id );
136	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_VAL ,"gpr_val" ,Tcontrol_t ,1 );
137	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_NUM_REG ,"gpr_num_reg" ,Tgeneral_address_t,_param->_size_general_register);
138	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_GPR_DATA ,"gpr_data" ,Tgeneral_data_t ,_param->_size_general_data );
139	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_VAL ,"spr_val" ,Tcontrol_t ,1 );
140	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_NUM_REG ,"spr_num_reg" ,Tspecial_address_t,_param->_size_special_register);
141	ALLOC1_SIGNAL_OUT(out_BYPASS_WRITE_SPR_DATA ,"spr_data" ,Tspecial_data_t ,_param->_size_special_data );
142
143	ALLOC1_INTERFACE_END(_param->_nb_bypass_write);
144	}
145
146	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
147
148	std::string name;
149
150	{
151	name = _name+"_write_queue";
152	log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str());
153
154	component_write_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::write_queue::Write_queue
155	(name.c_str()
156	#ifdef STATISTICS
157	,param_statistics
158	#endif
159	,_param->_param_write_queue
160	,_usage);
161
162	_component->set_component (component_write_queue->_component
163	#ifdef POSITION
164	, 50, 50, 10, 10
165	#endif
166	);
167	}
168
169	if (_param->_have_component_execute_queue)
170	{
171	name = _name+"_execute_queue";
172	log_printf(INFO,Core,FUNCTION,_("Create : %s"),name.c_str());
173
174	component_execute_queue = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::execute_queue::Execute_queue
175	(name.c_str()
176	#ifdef STATISTICS
177	,param_statistics
178	#endif
179	,_param->_param_execute_queue
180	,_usage);
181
182	_component->set_component (component_execute_queue->_component
183	#ifdef POSITION
184	, 50, 50, 10, 10
185	#endif
186	);
187	}
188
189	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
190	{
191	name = _name+"_write_queue";
192	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str());
193
194	#ifdef POSITION
195	_component->interface_map (name ,"",
196	_name,"");
197	#endif
198
199	_component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
200	_component->port_map(name,"in_NRESET", _name, "in_NRESET");
201
202
203	#ifdef POSITION
204	_component->interface_map (name ,"write_queue_in",
205	_name,"write_unit_in");
206	#endif
207
208	_component->port_map(name, "in_WRITE_QUEUE_IN_VAL" , _name, "in_WRITE_UNIT_IN_VAL" );
209	_component->port_map(name,"out_WRITE_QUEUE_IN_ACK" , _name,"out_WRITE_UNIT_IN_ACK" );
210	if (_param->_have_port_context_id)
211	_component->port_map(name, "in_WRITE_QUEUE_IN_CONTEXT_ID" , _name, "in_WRITE_UNIT_IN_CONTEXT_ID" );
212	if (_param->_have_port_front_end_id)
213	_component->port_map(name, "in_WRITE_QUEUE_IN_FRONT_END_ID" , _name, "in_WRITE_UNIT_IN_FRONT_END_ID" );
214	if (_param->_have_port_ooo_engine_id)
215	_component->port_map(name, "in_WRITE_QUEUE_IN_OOO_ENGINE_ID", _name, "in_WRITE_UNIT_IN_OOO_ENGINE_ID");
216	if (_param->_have_port_rob_ptr)
217	_component->port_map(name, "in_WRITE_QUEUE_IN_PACKET_ID" , _name, "in_WRITE_UNIT_IN_PACKET_ID" );
218	//_component->port_map(name, "in_WRITE_QUEUE_IN_OPERATION" , _name, "in_WRITE_UNIT_IN_OPERATION" );
219	//_component->port_map(name, "in_WRITE_QUEUE_IN_TYPE" , _name, "in_WRITE_UNIT_IN_TYPE" );
220	_component->port_map(name, "in_WRITE_QUEUE_IN_CANCEL" , _name, "in_WRITE_UNIT_IN_CANCEL" );
221	_component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RD" , _name, "in_WRITE_UNIT_IN_WRITE_RD" );
222	_component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RD" , _name, "in_WRITE_UNIT_IN_NUM_REG_RD" );
223	_component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RD" , _name, "in_WRITE_UNIT_IN_DATA_RD" );
224	_component->port_map(name, "in_WRITE_QUEUE_IN_WRITE_RE" , _name, "in_WRITE_UNIT_IN_WRITE_RE" );
225	_component->port_map(name, "in_WRITE_QUEUE_IN_NUM_REG_RE" , _name, "in_WRITE_UNIT_IN_NUM_REG_RE" );
226	_component->port_map(name, "in_WRITE_QUEUE_IN_DATA_RE" , _name, "in_WRITE_UNIT_IN_DATA_RE" );
227	_component->port_map(name, "in_WRITE_QUEUE_IN_EXCEPTION" , _name, "in_WRITE_UNIT_IN_EXCEPTION" );
228	_component->port_map(name, "in_WRITE_QUEUE_IN_NO_SEQUENCE" , _name, "in_WRITE_UNIT_IN_NO_SEQUENCE" );
229	_component->port_map(name, "in_WRITE_QUEUE_IN_ADDRESS" , _name, "in_WRITE_UNIT_IN_ADDRESS" );
230
231
232	if (_param->_have_component_execute_queue)
233	{
234	#ifdef POSITION
235	_component->interface_map (name ,"write_queue_out",
236	_name+"_execute_queue", "execute_queue_in");
237	#endif
238
239	_component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_VAL" );
240	_component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name+"_execute_queue","out_EXECUTE_QUEUE_IN_ACK" );
241	if (_param->_have_port_context_id)
242	_component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_CONTEXT_ID" );
243	if (_param->_have_port_front_end_id)
244	_component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FRONT_END_ID" );
245	if (_param->_have_port_ooo_engine_id)
246	_component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID");
247	if (_param->_have_port_rob_ptr)
248	_component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_PACKET_ID" );
249	//_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_OPERATION" );
250	//_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_TYPE" );
251	_component->port_map(name,"out_WRITE_QUEUE_OUT_CANCEL" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_CANCEL" );
252	_component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_FLAGS" );
253	_component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_EXCEPTION" );
254	_component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_NO_SEQUENCE" );
255	_component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_ADDRESS" );
256	_component->port_map(name,"out_WRITE_QUEUE_OUT_DATA" , _name+"_execute_queue", "in_EXECUTE_QUEUE_IN_DATA" );
257	}
258	else
259	{
260	#ifdef POSITION
261	_component->interface_map (name ,"write_queue_out",
262	_name,"write_unit_out");
263	#endif
264
265	_component->port_map(name,"out_WRITE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" );
266	_component->port_map(name, "in_WRITE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" );
267	if (_param->_have_port_context_id)
268	_component->port_map(name,"out_WRITE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" );
269	if (_param->_have_port_front_end_id)
270	_component->port_map(name,"out_WRITE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
271	if (_param->_have_port_ooo_engine_id)
272	_component->port_map(name,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
273	if (_param->_have_port_rob_ptr)
274	_component->port_map(name,"out_WRITE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" );
275	//_component->port_map(name,"out_WRITE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" );
276	//_component->port_map(name,"out_WRITE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" );
277	_component->port_map(name,"out_WRITE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" );
278	_component->port_map(name,"out_WRITE_QUEUE_OUT_CANCEL" , _name,"out_WRITE_UNIT_OUT_CANCEL" );
279	_component->port_map(name,"out_WRITE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" );
280	_component->port_map(name,"out_WRITE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" );
281	_component->port_map(name,"out_WRITE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" );
282	_component->port_map(name,"out_WRITE_QUEUE_OUT_DATA" , _name,"out_WRITE_UNIT_OUT_DATA" );
283	}
284
285	for (uint32_t i=0; i<_param->_nb_gpr_write; i++)
286	{
287	#ifdef POSITION
288	_component->interface_map (name ,"gpr_write_"+toString(i),
289	_name,"gpr_write_"+toString(i));
290	#endif
291
292	_component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_GPR_WRITE_"+toString(i)+"_VAL" );
293	_component->port_map(name, "in_GPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_GPR_WRITE_"+toString(i)+"_ACK" );
294	if (_param->_have_port_ooo_engine_id)
295	_component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
296	_component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_GPR_WRITE_"+toString(i)+"_NUM_REG" );
297	_component->port_map(name,"out_GPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_GPR_WRITE_"+toString(i)+"_DATA" );
298	}
299
300	for (uint32_t i=0; i<_param->_nb_spr_write; i++)
301	{
302	#ifdef POSITION
303	_component->interface_map (name ,"spr_write_"+toString(i),
304	_name,"spr_write_"+toString(i));
305	#endif
306
307	_component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_VAL" ,_name,"out_SPR_WRITE_"+toString(i)+"_VAL" );
308	_component->port_map(name, "in_SPR_WRITE_"+toString(i)+"_ACK" ,_name, "in_SPR_WRITE_"+toString(i)+"_ACK" );
309	if (_param->_have_port_ooo_engine_id)
310	_component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
311	_component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" ,_name,"out_SPR_WRITE_"+toString(i)+"_NUM_REG" );
312	_component->port_map(name,"out_SPR_WRITE_"+toString(i)+"_DATA" ,_name,"out_SPR_WRITE_"+toString(i)+"_DATA" );
313	}
314
315
316	for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
317	{
318	#ifdef POSITION
319	_component->interface_map (name ,"bypass_write_"+toString(i),
320	_name,"bypass_write_"+toString(i));
321	#endif
322
323	if (_param->_have_port_ooo_engine_id)
324	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID",_name,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
325	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL" );
326	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG" );
327	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA" );
328	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL" );
329	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG" );
330	_component->port_map(name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" ,_name,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA" );
331	}
332	}
333
334	if (_param->_have_component_execute_queue)
335	{
336	name = _name+"_execute_queue";
337	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),name.c_str());
338
339	#ifdef POSITION
340	_component->interface_map (name ,"",
341	_name,"");
342	#endif
343
344	_component->port_map(name,"in_CLOCK" , _name, "in_CLOCK");
345	_component->port_map(name,"in_NRESET", _name, "in_NRESET");
346
347
348	#ifdef POSITION
349	_component->interface_map (name ,"execute_queue_in",
350	_name+"_write_queue","write_queue_in");
351	#endif
352
353	_component->port_map(name, "in_EXECUTE_QUEUE_IN_VAL" , _name+"_write_queue","out_WRITE_QUEUE_OUT_VAL" );
354	_component->port_map(name,"out_EXECUTE_QUEUE_IN_ACK" , _name+"_write_queue", "in_WRITE_QUEUE_OUT_ACK" );
355	if (_param->_have_port_context_id)
356	_component->port_map(name, "in_EXECUTE_QUEUE_IN_CONTEXT_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_CONTEXT_ID" );
357	if (_param->_have_port_front_end_id)
358	_component->port_map(name, "in_EXECUTE_QUEUE_IN_FRONT_END_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_FRONT_END_ID" );
359	if (_param->_have_port_ooo_engine_id)
360	_component->port_map(name, "in_EXECUTE_QUEUE_IN_OOO_ENGINE_ID", _name+"_write_queue","out_WRITE_QUEUE_OUT_OOO_ENGINE_ID");
361	if (_param->_have_port_rob_ptr)
362	_component->port_map(name, "in_EXECUTE_QUEUE_IN_PACKET_ID" , _name+"_write_queue","out_WRITE_QUEUE_OUT_PACKET_ID" );
363	//_component->port_map(name, "in_EXECUTE_QUEUE_IN_OPERATION" , _name+"_write_queue","out_WRITE_QUEUE_OUT_OPERATION" );
364	//_component->port_map(name, "in_EXECUTE_QUEUE_IN_TYPE" , _name+"_write_queue","out_WRITE_QUEUE_OUT_TYPE" );
365	_component->port_map(name, "in_EXECUTE_QUEUE_IN_CANCEL" , _name+"_write_queue","out_WRITE_QUEUE_OUT_CANCEL" );
366	_component->port_map(name, "in_EXECUTE_QUEUE_IN_FLAGS" , _name+"_write_queue","out_WRITE_QUEUE_OUT_FLAGS" );
367	_component->port_map(name, "in_EXECUTE_QUEUE_IN_EXCEPTION" , _name+"_write_queue","out_WRITE_QUEUE_OUT_EXCEPTION" );
368	_component->port_map(name, "in_EXECUTE_QUEUE_IN_NO_SEQUENCE" , _name+"_write_queue","out_WRITE_QUEUE_OUT_NO_SEQUENCE" );
369	_component->port_map(name, "in_EXECUTE_QUEUE_IN_ADDRESS" , _name+"_write_queue","out_WRITE_QUEUE_OUT_ADDRESS" );
370	_component->port_map(name, "in_EXECUTE_QUEUE_IN_DATA" , _name+"_write_queue","out_WRITE_QUEUE_OUT_DATA" );
371
372	#ifdef POSITION
373	_component->interface_map (name ,"execute_queue_out",
374	_name,"write_unit_out");
375	#endif
376
377	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_VAL" , _name,"out_WRITE_UNIT_OUT_VAL" );
378	_component->port_map(name, "in_EXECUTE_QUEUE_OUT_ACK" , _name, "in_WRITE_UNIT_OUT_ACK" );
379	if (_param->_have_port_context_id)
380	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_CONTEXT_ID" , _name,"out_WRITE_UNIT_OUT_CONTEXT_ID" );
381	if (_param->_have_port_front_end_id)
382	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_FRONT_END_ID" , _name,"out_WRITE_UNIT_OUT_FRONT_END_ID" );
383	if (_param->_have_port_ooo_engine_id)
384	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OOO_ENGINE_ID", _name,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID");
385	if (_param->_have_port_rob_ptr)
386	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_PACKET_ID" , _name,"out_WRITE_UNIT_OUT_PACKET_ID" );
387	//_component->port_map(name,"out_EXECUTE_QUEUE_OUT_OPERATION" , _name,"out_WRITE_UNIT_OUT_OPERATION" );
388	//_component->port_map(name,"out_EXECUTE_QUEUE_OUT_TYPE" , _name,"out_WRITE_UNIT_OUT_TYPE" );
389	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_CANCEL" , _name,"out_WRITE_UNIT_OUT_CANCEL" );
390	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_FLAGS" , _name,"out_WRITE_UNIT_OUT_FLAGS" );
391	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_EXCEPTION" , _name,"out_WRITE_UNIT_OUT_EXCEPTION" );
392	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_NO_SEQUENCE" , _name,"out_WRITE_UNIT_OUT_NO_SEQUENCE" );
393	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_ADDRESS" , _name,"out_WRITE_UNIT_OUT_ADDRESS" );
394	_component->port_map(name,"out_EXECUTE_QUEUE_OUT_DATA" , _name,"out_WRITE_UNIT_OUT_DATA" );
395	}
396
397	#ifdef POSITION
398	if (usage_is_set(_usage,USE_POSITION))
399	_component->generate_file();
400	#endif
401
402	log_printf(FUNC,Write_unit,FUNCTION,"End");
403	};
404
405	}; // end namespace write_unit
406	}; // end namespace multi_write_unit
407	}; // end namespace execute_loop
408	}; // end namespace multi_execute_loop
409	}; // end namespace core
410
411	}; // end namespace behavioural
412	}; // end namespace morpheo

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/src/Write_unit_allocation.cpp

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