[60] | 1 | /* |
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| 2 | * $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #define NB_ITERATION 1 |
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[64] | 10 | #define CYCLE_MAX (10240*NB_ITERATION) |
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[60] | 11 | |
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[82] | 12 | #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Register_unit/SelfTest/include/test.h" |
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| 13 | #include "Common/include/Test.h" |
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[60] | 14 | |
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| 15 | void test (string name, |
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| 16 | morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::Parameters * _param) |
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| 17 | { |
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| 18 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 19 | |
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| 20 | #ifdef STATISTICS |
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| 21 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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| 22 | #endif |
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| 23 | |
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[88] | 24 | Tusage_t _usage = USE_ALL; |
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| 25 | |
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| 26 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 27 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 28 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 29 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 30 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 31 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 32 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 33 | |
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[82] | 34 | Register_unit * _Register_unit = new Register_unit |
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| 35 | (name.c_str(), |
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[60] | 36 | #ifdef STATISTICS |
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[82] | 37 | _parameters_statistics, |
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[60] | 38 | #endif |
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[82] | 39 | _param, |
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[88] | 40 | _usage); |
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[60] | 41 | |
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| 42 | #ifdef SYSTEMC |
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| 43 | /********************************************************************* |
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| 44 | * Déclarations des signaux |
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| 45 | *********************************************************************/ |
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| 46 | sc_clock * in_CLOCK; |
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| 47 | sc_signal<Tcontrol_t> * in_NRESET; |
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| 48 | |
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| 49 | // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 50 | sc_signal<Tcontrol_t > ** in_GPR_READ_VAL ; |
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| 51 | sc_signal<Tcontrol_t > ** out_GPR_READ_ACK ; |
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| 52 | sc_signal<Tcontext_t > ** in_GPR_READ_OOO_ENGINE_ID ; |
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| 53 | sc_signal<Tgeneral_address_t> ** in_GPR_READ_NUM_REG ; |
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| 54 | sc_signal<Tgeneral_data_t > ** out_GPR_READ_DATA ; |
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| 55 | sc_signal<Tcontrol_t > ** out_GPR_READ_DATA_VAL ; |
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| 56 | |
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| 57 | // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 58 | sc_signal<Tcontrol_t > ** in_GPR_WRITE_VAL ; |
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| 59 | sc_signal<Tcontrol_t > ** out_GPR_WRITE_ACK ; |
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| 60 | sc_signal<Tcontext_t > ** in_GPR_WRITE_OOO_ENGINE_ID ; |
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| 61 | sc_signal<Tgeneral_address_t> ** in_GPR_WRITE_NUM_REG ; |
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| 62 | sc_signal<Tgeneral_data_t > ** in_GPR_WRITE_DATA ; |
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| 63 | |
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| 64 | // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 65 | sc_signal<Tcontrol_t > ** in_SPR_READ_VAL ; |
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| 66 | sc_signal<Tcontrol_t > ** out_SPR_READ_ACK ; |
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| 67 | sc_signal<Tcontext_t > ** in_SPR_READ_OOO_ENGINE_ID ; |
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| 68 | sc_signal<Tspecial_address_t> ** in_SPR_READ_NUM_REG ; |
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| 69 | sc_signal<Tspecial_data_t > ** out_SPR_READ_DATA ; |
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| 70 | sc_signal<Tcontrol_t > ** out_SPR_READ_DATA_VAL ; |
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| 71 | |
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| 72 | // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 73 | sc_signal<Tcontrol_t > ** in_SPR_WRITE_VAL ; |
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| 74 | sc_signal<Tcontrol_t > ** out_SPR_WRITE_ACK ; |
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| 75 | sc_signal<Tcontext_t > ** in_SPR_WRITE_OOO_ENGINE_ID ; |
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| 76 | sc_signal<Tspecial_address_t> ** in_SPR_WRITE_NUM_REG ; |
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| 77 | sc_signal<Tspecial_data_t > ** in_SPR_WRITE_DATA ; |
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| 78 | |
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| 79 | // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 80 | sc_signal<Tcontrol_t > *** in_INSERT_ROB_VAL ; |
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| 81 | sc_signal<Tcontrol_t > *** out_INSERT_ROB_ACK ; |
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| 82 | sc_signal<Tcontrol_t > *** in_INSERT_ROB_RD_USE ; |
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| 83 | sc_signal<Tgeneral_address_t> *** in_INSERT_ROB_RD_NUM_REG ; // use=1 : status[num_reg]<- 0 |
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| 84 | sc_signal<Tcontrol_t > *** in_INSERT_ROB_RE_USE ; |
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| 85 | sc_signal<Tspecial_address_t> *** in_INSERT_ROB_RE_NUM_REG ; |
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| 86 | |
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[88] | 87 | // // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 88 | // sc_signal<Tcontrol_t > *** in_RETIRE_ROB_VAL ; |
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| 89 | // sc_signal<Tcontrol_t > *** out_RETIRE_ROB_ACK ; |
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| 90 | // sc_signal<Tcontrol_t > *** in_RETIRE_ROB_RD_OLD_USE ; |
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| 91 | // sc_signal<Tgeneral_address_t> *** in_RETIRE_ROB_RD_OLD_NUM_REG ; // old_use=1 : status[old_num_reg]<- 0 |
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| 92 | // sc_signal<Tcontrol_t > *** in_RETIRE_ROB_RD_NEW_USE ; |
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| 93 | // sc_signal<Tgeneral_address_t> *** in_RETIRE_ROB_RD_NEW_NUM_REG ; // new_use=1 : status[new_num_reg]<- 1 |
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| 94 | // sc_signal<Tcontrol_t > *** in_RETIRE_ROB_RE_OLD_USE ; |
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| 95 | // sc_signal<Tspecial_address_t> *** in_RETIRE_ROB_RE_OLD_NUM_REG ; |
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| 96 | // sc_signal<Tcontrol_t > *** in_RETIRE_ROB_RE_NEW_USE ; |
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| 97 | // sc_signal<Tspecial_address_t> *** in_RETIRE_ROB_RE_NEW_NUM_REG ; |
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[60] | 98 | |
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[62] | 99 | string rename = "signal"; |
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[60] | 100 | |
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| 101 | in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 102 | in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 103 | |
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| 104 | |
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| 105 | // ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 106 | in_GPR_READ_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_gpr_read]; |
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| 107 | out_GPR_READ_ACK = new sc_signal<Tcontrol_t > * [_param->_nb_gpr_read]; |
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| 108 | in_GPR_READ_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_gpr_read]; |
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| 109 | in_GPR_READ_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_gpr_read]; |
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| 110 | out_GPR_READ_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_gpr_read]; |
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| 111 | out_GPR_READ_DATA_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_gpr_read]; |
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| 112 | |
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| 113 | for (uint32_t i=0; i<_param->_nb_gpr_read; i++) |
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| 114 | { |
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| 115 | in_GPR_READ_VAL [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 116 | out_GPR_READ_ACK [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 117 | in_GPR_READ_OOO_ENGINE_ID [i]= new sc_signal<Tcontext_t > (rename.c_str()); |
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| 118 | in_GPR_READ_NUM_REG [i]= new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 119 | out_GPR_READ_DATA [i]= new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 120 | out_GPR_READ_DATA_VAL [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 121 | } |
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| 122 | |
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| 123 | // ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 124 | in_GPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_gpr_write]; |
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| 125 | out_GPR_WRITE_ACK = new sc_signal<Tcontrol_t > * [_param->_nb_gpr_write]; |
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| 126 | in_GPR_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_gpr_write]; |
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| 127 | in_GPR_WRITE_NUM_REG = new sc_signal<Tgeneral_address_t> * [_param->_nb_gpr_write]; |
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| 128 | in_GPR_WRITE_DATA = new sc_signal<Tgeneral_data_t > * [_param->_nb_gpr_write]; |
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| 129 | |
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| 130 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
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| 131 | { |
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| 132 | in_GPR_WRITE_VAL [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 133 | out_GPR_WRITE_ACK [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 134 | in_GPR_WRITE_OOO_ENGINE_ID [i]= new sc_signal<Tcontext_t > (rename.c_str()); |
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| 135 | in_GPR_WRITE_NUM_REG [i]= new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 136 | in_GPR_WRITE_DATA [i]= new sc_signal<Tgeneral_data_t > (rename.c_str()); |
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| 137 | } |
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| 138 | |
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| 139 | // ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 140 | in_SPR_READ_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_spr_read]; |
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| 141 | out_SPR_READ_ACK = new sc_signal<Tcontrol_t > * [_param->_nb_spr_read]; |
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| 142 | in_SPR_READ_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_spr_read]; |
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| 143 | in_SPR_READ_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_spr_read]; |
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| 144 | out_SPR_READ_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_spr_read]; |
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| 145 | out_SPR_READ_DATA_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_spr_read]; |
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| 146 | |
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| 147 | for (uint32_t i=0; i<_param->_nb_spr_read; i++) |
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| 148 | { |
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| 149 | in_SPR_READ_VAL [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 150 | out_SPR_READ_ACK [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 151 | in_SPR_READ_OOO_ENGINE_ID [i]= new sc_signal<Tcontext_t > (rename.c_str()); |
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| 152 | in_SPR_READ_NUM_REG [i]= new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 153 | out_SPR_READ_DATA [i]= new sc_signal<Tspecial_data_t > (rename.c_str()); |
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| 154 | out_SPR_READ_DATA_VAL [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 155 | } |
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| 156 | |
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| 157 | // ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 158 | in_SPR_WRITE_VAL = new sc_signal<Tcontrol_t > * [_param->_nb_spr_write]; |
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| 159 | out_SPR_WRITE_ACK = new sc_signal<Tcontrol_t > * [_param->_nb_spr_write]; |
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| 160 | in_SPR_WRITE_OOO_ENGINE_ID = new sc_signal<Tcontext_t > * [_param->_nb_spr_write]; |
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| 161 | in_SPR_WRITE_NUM_REG = new sc_signal<Tspecial_address_t> * [_param->_nb_spr_write]; |
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| 162 | in_SPR_WRITE_DATA = new sc_signal<Tspecial_data_t > * [_param->_nb_spr_write]; |
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| 163 | |
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| 164 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
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| 165 | { |
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| 166 | in_SPR_WRITE_VAL [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 167 | out_SPR_WRITE_ACK [i]= new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 168 | in_SPR_WRITE_OOO_ENGINE_ID [i]= new sc_signal<Tcontext_t > (rename.c_str()); |
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| 169 | in_SPR_WRITE_NUM_REG [i]= new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 170 | in_SPR_WRITE_DATA [i]= new sc_signal<Tspecial_data_t > (rename.c_str()); |
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| 171 | } |
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| 172 | |
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| 173 | // ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 174 | in_INSERT_ROB_VAL = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 175 | out_INSERT_ROB_ACK = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 176 | in_INSERT_ROB_RD_USE = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 177 | in_INSERT_ROB_RD_NUM_REG = new sc_signal<Tgeneral_address_t> ** [_param->_nb_ooo_engine]; |
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| 178 | in_INSERT_ROB_RE_USE = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 179 | in_INSERT_ROB_RE_NUM_REG = new sc_signal<Tspecial_address_t> ** [_param->_nb_ooo_engine]; |
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| 180 | |
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| 181 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
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| 182 | { |
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| 183 | uint32_t x=_param->_nb_inst_insert_rob [i]; |
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| 184 | |
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| 185 | in_INSERT_ROB_VAL [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 186 | out_INSERT_ROB_ACK [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 187 | in_INSERT_ROB_RD_USE [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 188 | in_INSERT_ROB_RD_NUM_REG [i] = new sc_signal<Tgeneral_address_t> * [x]; |
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| 189 | in_INSERT_ROB_RE_USE [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 190 | in_INSERT_ROB_RE_NUM_REG [i] = new sc_signal<Tspecial_address_t> * [x]; |
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| 191 | |
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| 192 | for (uint32_t j=0; j<x; j++) |
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| 193 | { |
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| 194 | in_INSERT_ROB_VAL [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 195 | out_INSERT_ROB_ACK [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 196 | in_INSERT_ROB_RD_USE [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 197 | in_INSERT_ROB_RD_NUM_REG [i][j] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 198 | in_INSERT_ROB_RE_USE [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 199 | in_INSERT_ROB_RE_NUM_REG [i][j] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 200 | |
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| 201 | } |
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| 202 | } |
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| 203 | |
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[88] | 204 | // // ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 205 | // in_RETIRE_ROB_VAL = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 206 | // out_RETIRE_ROB_ACK = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 207 | // in_RETIRE_ROB_RD_OLD_USE = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 208 | // in_RETIRE_ROB_RD_OLD_NUM_REG = new sc_signal<Tgeneral_address_t> ** [_param->_nb_ooo_engine]; |
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| 209 | // in_RETIRE_ROB_RE_OLD_USE = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 210 | // in_RETIRE_ROB_RE_OLD_NUM_REG = new sc_signal<Tspecial_address_t> ** [_param->_nb_ooo_engine]; |
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| 211 | // in_RETIRE_ROB_RD_NEW_USE = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 212 | // in_RETIRE_ROB_RD_NEW_NUM_REG = new sc_signal<Tgeneral_address_t> ** [_param->_nb_ooo_engine]; |
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| 213 | // in_RETIRE_ROB_RE_NEW_USE = new sc_signal<Tcontrol_t > ** [_param->_nb_ooo_engine]; |
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| 214 | // in_RETIRE_ROB_RE_NEW_NUM_REG = new sc_signal<Tspecial_address_t> ** [_param->_nb_ooo_engine]; |
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[60] | 215 | |
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[88] | 216 | // for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
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| 217 | // { |
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| 218 | // uint32_t x=_param->_nb_inst_retire_rob [i]; |
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[60] | 219 | |
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[88] | 220 | // in_RETIRE_ROB_VAL [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 221 | // out_RETIRE_ROB_ACK [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 222 | // in_RETIRE_ROB_RD_OLD_USE [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 223 | // in_RETIRE_ROB_RD_OLD_NUM_REG [i] = new sc_signal<Tgeneral_address_t> * [x]; |
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| 224 | // in_RETIRE_ROB_RE_OLD_USE [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 225 | // in_RETIRE_ROB_RE_OLD_NUM_REG [i] = new sc_signal<Tspecial_address_t> * [x]; |
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| 226 | // in_RETIRE_ROB_RD_NEW_USE [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 227 | // in_RETIRE_ROB_RD_NEW_NUM_REG [i] = new sc_signal<Tgeneral_address_t> * [x]; |
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| 228 | // in_RETIRE_ROB_RE_NEW_USE [i] = new sc_signal<Tcontrol_t > * [x]; |
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| 229 | // in_RETIRE_ROB_RE_NEW_NUM_REG [i] = new sc_signal<Tspecial_address_t> * [x]; |
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[60] | 230 | |
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[88] | 231 | // for (uint32_t j=0; j<x; j++) |
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| 232 | // { |
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| 233 | // in_RETIRE_ROB_VAL [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 234 | // out_RETIRE_ROB_ACK [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 235 | // in_RETIRE_ROB_RD_OLD_USE [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 236 | // in_RETIRE_ROB_RD_OLD_NUM_REG [i][j] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 237 | // in_RETIRE_ROB_RE_OLD_USE [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 238 | // in_RETIRE_ROB_RE_OLD_NUM_REG [i][j] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 239 | // in_RETIRE_ROB_RD_NEW_USE [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 240 | // in_RETIRE_ROB_RD_NEW_NUM_REG [i][j] = new sc_signal<Tgeneral_address_t> (rename.c_str()); |
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| 241 | // in_RETIRE_ROB_RE_NEW_USE [i][j] = new sc_signal<Tcontrol_t > (rename.c_str()); |
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| 242 | // in_RETIRE_ROB_RE_NEW_NUM_REG [i][j] = new sc_signal<Tspecial_address_t> (rename.c_str()); |
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| 243 | // } |
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| 244 | // } |
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[60] | 245 | |
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| 246 | |
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| 247 | /******************************************************** |
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| 248 | * Instanciation |
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| 249 | ********************************************************/ |
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| 250 | |
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| 251 | cout << "<" << name << "> Instanciation of _Register_unit" << endl; |
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| 252 | |
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| 253 | (*(_Register_unit->in_CLOCK)) (*(in_CLOCK)); |
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| 254 | (*(_Register_unit->in_NRESET)) (*(in_NRESET)); |
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| 255 | |
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| 256 | for (uint32_t i=0; i<_param->_nb_gpr_read; i++) |
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| 257 | { |
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| 258 | (*(_Register_unit-> in_GPR_READ_VAL [i]))(*( in_GPR_READ_VAL [i])); |
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| 259 | (*(_Register_unit->out_GPR_READ_ACK [i]))(*(out_GPR_READ_ACK [i])); |
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| 260 | if (_param->_have_port_ooo_engine_id == true) |
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| 261 | (*(_Register_unit-> in_GPR_READ_OOO_ENGINE_ID [i]))(*( in_GPR_READ_OOO_ENGINE_ID [i])); |
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| 262 | (*(_Register_unit-> in_GPR_READ_NUM_REG [i]))(*( in_GPR_READ_NUM_REG [i])); |
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| 263 | (*(_Register_unit->out_GPR_READ_DATA [i]))(*(out_GPR_READ_DATA [i])); |
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| 264 | (*(_Register_unit->out_GPR_READ_DATA_VAL [i]))(*(out_GPR_READ_DATA_VAL [i])); |
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| 265 | } |
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| 266 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
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| 267 | { |
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| 268 | (*(_Register_unit-> in_GPR_WRITE_VAL [i]))(*( in_GPR_WRITE_VAL [i])); |
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| 269 | (*(_Register_unit->out_GPR_WRITE_ACK [i]))(*(out_GPR_WRITE_ACK [i])); |
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| 270 | if (_param->_have_port_ooo_engine_id == true) |
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| 271 | (*(_Register_unit-> in_GPR_WRITE_OOO_ENGINE_ID [i]))(*( in_GPR_WRITE_OOO_ENGINE_ID [i])); |
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| 272 | (*(_Register_unit-> in_GPR_WRITE_NUM_REG [i]))(*( in_GPR_WRITE_NUM_REG [i])); |
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| 273 | (*(_Register_unit-> in_GPR_WRITE_DATA [i]))(*( in_GPR_WRITE_DATA [i])); |
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| 274 | } |
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| 275 | for (uint32_t i=0; i<_param->_nb_spr_read; i++) |
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| 276 | { |
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| 277 | (*(_Register_unit-> in_SPR_READ_VAL [i]))(*( in_SPR_READ_VAL [i])); |
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| 278 | (*(_Register_unit->out_SPR_READ_ACK [i]))(*(out_SPR_READ_ACK [i])); |
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| 279 | if (_param->_have_port_ooo_engine_id == true) |
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| 280 | (*(_Register_unit-> in_SPR_READ_OOO_ENGINE_ID [i]))(*( in_SPR_READ_OOO_ENGINE_ID [i])); |
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| 281 | (*(_Register_unit-> in_SPR_READ_NUM_REG [i]))(*( in_SPR_READ_NUM_REG [i])); |
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| 282 | (*(_Register_unit->out_SPR_READ_DATA [i]))(*(out_SPR_READ_DATA [i])); |
---|
| 283 | (*(_Register_unit->out_SPR_READ_DATA_VAL [i]))(*(out_SPR_READ_DATA_VAL [i])); |
---|
| 284 | } |
---|
| 285 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
| 286 | { |
---|
| 287 | (*(_Register_unit-> in_SPR_WRITE_VAL [i]))(*( in_SPR_WRITE_VAL [i])); |
---|
| 288 | (*(_Register_unit->out_SPR_WRITE_ACK [i]))(*(out_SPR_WRITE_ACK [i])); |
---|
| 289 | if (_param->_have_port_ooo_engine_id == true) |
---|
| 290 | (*(_Register_unit-> in_SPR_WRITE_OOO_ENGINE_ID [i]))(*( in_SPR_WRITE_OOO_ENGINE_ID [i])); |
---|
| 291 | (*(_Register_unit-> in_SPR_WRITE_NUM_REG [i]))(*( in_SPR_WRITE_NUM_REG [i])); |
---|
| 292 | (*(_Register_unit-> in_SPR_WRITE_DATA [i]))(*( in_SPR_WRITE_DATA [i])); |
---|
| 293 | } |
---|
| 294 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 295 | for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++) |
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| 296 | { |
---|
| 297 | (*(_Register_unit-> in_INSERT_ROB_VAL [i][j]))(*( in_INSERT_ROB_VAL [i][j])); |
---|
| 298 | (*(_Register_unit->out_INSERT_ROB_ACK [i][j]))(*(out_INSERT_ROB_ACK [i][j])); |
---|
| 299 | (*(_Register_unit-> in_INSERT_ROB_RD_USE [i][j]))(*( in_INSERT_ROB_RD_USE [i][j])); |
---|
| 300 | (*(_Register_unit-> in_INSERT_ROB_RD_NUM_REG [i][j]))(*( in_INSERT_ROB_RD_NUM_REG [i][j])); |
---|
| 301 | (*(_Register_unit-> in_INSERT_ROB_RE_USE [i][j]))(*( in_INSERT_ROB_RE_USE [i][j])); |
---|
| 302 | (*(_Register_unit-> in_INSERT_ROB_RE_NUM_REG [i][j]))(*( in_INSERT_ROB_RE_NUM_REG [i][j])); |
---|
| 303 | } |
---|
[88] | 304 | // for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 305 | // for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) |
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| 306 | // { |
---|
| 307 | // (*(_Register_unit-> in_RETIRE_ROB_VAL [i][j]))(*( in_RETIRE_ROB_VAL [i][j])); |
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| 308 | // (*(_Register_unit->out_RETIRE_ROB_ACK [i][j]))(*(out_RETIRE_ROB_ACK [i][j])); |
---|
| 309 | // (*(_Register_unit-> in_RETIRE_ROB_RD_OLD_USE [i][j]))(*( in_RETIRE_ROB_RD_OLD_USE [i][j])); |
---|
| 310 | // (*(_Register_unit-> in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]))(*( in_RETIRE_ROB_RD_OLD_NUM_REG [i][j])); |
---|
| 311 | // (*(_Register_unit-> in_RETIRE_ROB_RE_OLD_USE [i][j]))(*( in_RETIRE_ROB_RE_OLD_USE [i][j])); |
---|
| 312 | // (*(_Register_unit-> in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]))(*( in_RETIRE_ROB_RE_OLD_NUM_REG [i][j])); |
---|
| 313 | // (*(_Register_unit-> in_RETIRE_ROB_RD_NEW_USE [i][j]))(*( in_RETIRE_ROB_RD_NEW_USE [i][j])); |
---|
| 314 | // (*(_Register_unit-> in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]))(*( in_RETIRE_ROB_RD_NEW_NUM_REG [i][j])); |
---|
| 315 | // (*(_Register_unit-> in_RETIRE_ROB_RE_NEW_USE [i][j]))(*( in_RETIRE_ROB_RE_NEW_USE [i][j])); |
---|
| 316 | // (*(_Register_unit-> in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]))(*( in_RETIRE_ROB_RE_NEW_NUM_REG [i][j])); |
---|
| 317 | // } |
---|
[60] | 318 | |
---|
| 319 | cout << "<" << name << "> Start Simulation ............" << endl; |
---|
| 320 | Time * _time = new Time(); |
---|
| 321 | |
---|
| 322 | /******************************************************** |
---|
| 323 | * Simulation - Begin |
---|
| 324 | ********************************************************/ |
---|
| 325 | |
---|
| 326 | // Initialisation |
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[64] | 327 | uint32_t max_nb_general_register = 0; |
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[60] | 328 | |
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[64] | 329 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
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| 330 | if (_param->_nb_general_register [i] > max_nb_general_register) |
---|
| 331 | max_nb_general_register = _param->_nb_general_register [i]; |
---|
| 332 | |
---|
| 333 | uint32_t max_nb_special_register = 0; |
---|
| 334 | |
---|
| 335 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
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| 336 | if (_param->_nb_special_register [i] > max_nb_special_register) |
---|
| 337 | max_nb_special_register = _param->_nb_special_register [i]; |
---|
| 338 | |
---|
| 339 | const int32_t percent_transaction_read = 70; |
---|
| 340 | const int32_t percent_transaction_write = 70; |
---|
| 341 | const int32_t percent_transaction_insert = 70; |
---|
| 342 | const int32_t percent_transaction_insert_use = 70; |
---|
[88] | 343 | // const int32_t percent_transaction_retire = 70; |
---|
| 344 | // const int32_t percent_transaction_retire_use = 70; |
---|
[64] | 345 | const uint32_t nb_request = max_nb_general_register; |
---|
| 346 | |
---|
[60] | 347 | const uint32_t seed = 0; |
---|
| 348 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
---|
| 349 | |
---|
| 350 | srand(seed); |
---|
| 351 | |
---|
[64] | 352 | Tgeneral_data_t gpr [_param->_nb_ooo_engine][max_nb_general_register]; |
---|
| 353 | Tcontrol_t gpr_status [_param->_nb_ooo_engine][max_nb_general_register]; |
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| 354 | Tspecial_data_t spr [_param->_nb_ooo_engine][max_nb_special_register]; |
---|
| 355 | Tcontrol_t spr_status [_param->_nb_ooo_engine][max_nb_special_register]; |
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| 356 | |
---|
[60] | 357 | SC_START(0); |
---|
| 358 | |
---|
| 359 | LABEL("Initialisation"); |
---|
| 360 | |
---|
[65] | 361 | in_NRESET->write(0); |
---|
| 362 | SC_START(5); |
---|
| 363 | in_NRESET->write(1); |
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| 364 | |
---|
[64] | 365 | for (uint32_t i=0; i<_param->_nb_gpr_read ; i++) |
---|
| 366 | in_GPR_READ_VAL [i]->write(0); |
---|
| 367 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
| 368 | in_GPR_WRITE_VAL [i]->write(0); |
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| 369 | for (uint32_t i=0; i<_param->_nb_spr_read ; i++) |
---|
| 370 | in_SPR_READ_VAL [i]->write(0); |
---|
| 371 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
| 372 | in_SPR_WRITE_VAL [i]->write(0); |
---|
| 373 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 374 | { |
---|
| 375 | for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++) |
---|
| 376 | in_INSERT_ROB_VAL [i][j]->write(0); |
---|
[88] | 377 | // for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) |
---|
| 378 | // in_RETIRE_ROB_VAL [i][j]->write(0); |
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[64] | 379 | } |
---|
| 380 | |
---|
| 381 | Tgeneral_address_t gpr_address [_param->_nb_gpr_write]; |
---|
| 382 | Tgeneral_address_t gpr_address_next; |
---|
| 383 | uint32_t nb_port_gpr_active; // number of port active |
---|
| 384 | |
---|
| 385 | Tspecial_address_t spr_address [_param->_nb_spr_write]; |
---|
| 386 | Tspecial_address_t spr_address_next; |
---|
| 387 | uint32_t nb_port_spr_active; // number of port active |
---|
| 388 | |
---|
[60] | 389 | LABEL("Loop of Test"); |
---|
| 390 | |
---|
| 391 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
---|
| 392 | { |
---|
[82] | 393 | LABEL("Iteration %d",iteration); |
---|
[60] | 394 | |
---|
[64] | 395 | LABEL("(GPR) Write default value"); |
---|
| 396 | |
---|
| 397 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 398 | for(uint32_t j=0; j<max_nb_general_register; j++) |
---|
| 399 | { |
---|
| 400 | gpr [i][j] = rand()%_param->_size_general_data; |
---|
| 401 | gpr_status [i][j] = 1; |
---|
| 402 | } |
---|
| 403 | |
---|
| 404 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 405 | { |
---|
| 406 | gpr_address_next = _param->_nb_gpr_write; |
---|
| 407 | nb_port_gpr_active = _param->_nb_gpr_write; |
---|
| 408 | |
---|
| 409 | for (uint32_t j=0; j<_param->_nb_gpr_write; j++) |
---|
| 410 | { |
---|
| 411 | gpr_address[j] = j; |
---|
| 412 | if (j >= _param->_nb_general_register [i]) |
---|
| 413 | nb_port_gpr_active --; |
---|
| 414 | } |
---|
| 415 | |
---|
| 416 | while (nb_port_gpr_active > 0) |
---|
| 417 | { |
---|
| 418 | for (uint32_t j=0; j<_param->_nb_gpr_write; j++) |
---|
| 419 | { |
---|
| 420 | in_GPR_WRITE_VAL [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and |
---|
| 421 | ((rand() % 100) < percent_transaction_write)); |
---|
| 422 | in_GPR_WRITE_OOO_ENGINE_ID [j]->write(i); |
---|
| 423 | in_GPR_WRITE_NUM_REG [j]->write(gpr_address[j]); |
---|
| 424 | in_GPR_WRITE_DATA [j]->write(gpr [i][gpr_address[j]]); |
---|
| 425 | } |
---|
| 426 | |
---|
| 427 | SC_START(1); |
---|
| 428 | |
---|
| 429 | // Test if write |
---|
| 430 | for (uint32_t j=0; j<_param->_nb_gpr_write; j++) |
---|
| 431 | if (in_GPR_WRITE_VAL [j]->read() and out_GPR_WRITE_ACK [j]->read()) |
---|
| 432 | { |
---|
| 433 | gpr_address[j] = gpr_address_next; |
---|
| 434 | |
---|
| 435 | if (gpr_address_next >= _param->_nb_general_register [i]) |
---|
| 436 | nb_port_gpr_active --; |
---|
| 437 | |
---|
| 438 | gpr_address_next ++; |
---|
| 439 | } |
---|
| 440 | } |
---|
| 441 | } |
---|
| 442 | |
---|
| 443 | for (uint32_t i=0; i<_param->_nb_gpr_write; i++) |
---|
| 444 | in_GPR_WRITE_VAL [i]->write(0); |
---|
| 445 | |
---|
| 446 | LABEL("(GPR) Read - and test data writted"); |
---|
| 447 | |
---|
| 448 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 449 | { |
---|
| 450 | gpr_address_next = _param->_nb_gpr_read; |
---|
| 451 | nb_port_gpr_active = _param->_nb_gpr_read; |
---|
| 452 | |
---|
| 453 | for (uint32_t j=0; j<_param->_nb_gpr_read; j++) |
---|
| 454 | { |
---|
| 455 | gpr_address[j] = j; |
---|
| 456 | if (j >= _param->_nb_general_register [i]) |
---|
| 457 | nb_port_gpr_active --; |
---|
| 458 | } |
---|
| 459 | |
---|
| 460 | while (nb_port_gpr_active > 0) |
---|
| 461 | { |
---|
| 462 | for (uint32_t j=0; j<_param->_nb_gpr_read; j++) |
---|
| 463 | { |
---|
| 464 | in_GPR_READ_VAL [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and |
---|
| 465 | ((rand() % 100) < percent_transaction_read)); |
---|
| 466 | in_GPR_READ_OOO_ENGINE_ID [j]->write(i); |
---|
| 467 | in_GPR_READ_NUM_REG [j]->write(gpr_address[j]); |
---|
| 468 | } |
---|
| 469 | |
---|
| 470 | SC_START(1); |
---|
| 471 | |
---|
| 472 | // Test if read |
---|
| 473 | for (uint32_t j=0; j<_param->_nb_gpr_read; j++) |
---|
| 474 | if (in_GPR_READ_VAL [j]->read() and out_GPR_READ_ACK [j]->read()) |
---|
| 475 | { |
---|
| 476 | TEST(Tgeneral_data_t, out_GPR_READ_DATA [j]->read(), gpr [i][gpr_address[j]]); |
---|
| 477 | TEST(Tcontrol_t , out_GPR_READ_DATA_VAL[j]->read(), gpr_status [i][gpr_address[j]]); |
---|
| 478 | |
---|
| 479 | gpr_address[j] = gpr_address_next; |
---|
| 480 | |
---|
| 481 | if (gpr_address_next >= _param->_nb_general_register [i]) |
---|
| 482 | nb_port_gpr_active --; |
---|
| 483 | |
---|
| 484 | gpr_address_next ++; |
---|
| 485 | } |
---|
| 486 | } |
---|
| 487 | } |
---|
| 488 | |
---|
| 489 | for (uint32_t i=0; i<_param->_nb_gpr_read; i++) |
---|
| 490 | in_GPR_READ_VAL [i]->write(0); |
---|
| 491 | |
---|
| 492 | LABEL("(SPR) Write default value"); |
---|
| 493 | |
---|
| 494 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 495 | for(uint32_t j=0; j<max_nb_special_register; j++) |
---|
| 496 | { |
---|
| 497 | spr [i][j] = rand()%_param->_size_special_data; |
---|
| 498 | spr_status [i][j] = 1; |
---|
| 499 | } |
---|
| 500 | |
---|
| 501 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 502 | { |
---|
| 503 | spr_address_next = _param->_nb_spr_write; |
---|
| 504 | nb_port_spr_active = _param->_nb_spr_write; |
---|
| 505 | |
---|
| 506 | for (uint32_t j=0; j<_param->_nb_spr_write; j++) |
---|
| 507 | { |
---|
| 508 | spr_address[j] = j; |
---|
| 509 | if (j >= _param->_nb_special_register [i]) |
---|
| 510 | nb_port_spr_active --; |
---|
| 511 | } |
---|
| 512 | |
---|
| 513 | while (nb_port_spr_active > 0) |
---|
| 514 | { |
---|
| 515 | for (uint32_t j=0; j<_param->_nb_spr_write; j++) |
---|
| 516 | { |
---|
| 517 | in_SPR_WRITE_VAL [j]->write((spr_address[j] < _param->_nb_special_register [i]) and |
---|
| 518 | ((rand() % 100) < percent_transaction_write)); |
---|
| 519 | in_SPR_WRITE_OOO_ENGINE_ID [j]->write(i); |
---|
| 520 | in_SPR_WRITE_NUM_REG [j]->write(spr_address[j]); |
---|
| 521 | in_SPR_WRITE_DATA [j]->write(spr [i][spr_address[j]]); |
---|
| 522 | } |
---|
| 523 | |
---|
| 524 | SC_START(1); |
---|
| 525 | |
---|
| 526 | // Test if write |
---|
| 527 | for (uint32_t j=0; j<_param->_nb_spr_write; j++) |
---|
| 528 | if (in_SPR_WRITE_VAL [j]->read() and out_SPR_WRITE_ACK [j]->read()) |
---|
| 529 | { |
---|
| 530 | spr_address[j] = spr_address_next; |
---|
| 531 | |
---|
| 532 | if (spr_address_next >= _param->_nb_special_register [i]) |
---|
| 533 | nb_port_spr_active --; |
---|
| 534 | |
---|
| 535 | spr_address_next ++; |
---|
| 536 | } |
---|
| 537 | } |
---|
| 538 | } |
---|
| 539 | |
---|
| 540 | for (uint32_t i=0; i<_param->_nb_spr_write; i++) |
---|
| 541 | in_SPR_WRITE_VAL [i]->write(0); |
---|
| 542 | |
---|
| 543 | LABEL("(SPR) Read - and test data writted"); |
---|
| 544 | |
---|
| 545 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 546 | { |
---|
| 547 | spr_address_next = _param->_nb_spr_read; |
---|
| 548 | nb_port_spr_active = _param->_nb_spr_read; |
---|
| 549 | |
---|
| 550 | for (uint32_t j=0; j<_param->_nb_spr_read; j++) |
---|
| 551 | { |
---|
| 552 | spr_address[j] = j; |
---|
| 553 | if (j >= _param->_nb_special_register [i]) |
---|
| 554 | nb_port_spr_active --; |
---|
| 555 | } |
---|
| 556 | |
---|
| 557 | while (nb_port_spr_active > 0) |
---|
| 558 | { |
---|
| 559 | for (uint32_t j=0; j<_param->_nb_spr_read; j++) |
---|
| 560 | { |
---|
| 561 | in_SPR_READ_VAL [j]->write((spr_address[j] < _param->_nb_special_register [i]) and |
---|
| 562 | ((rand() % 100) < percent_transaction_read)); |
---|
| 563 | in_SPR_READ_OOO_ENGINE_ID [j]->write(i); |
---|
| 564 | in_SPR_READ_NUM_REG [j]->write(spr_address[j]); |
---|
| 565 | } |
---|
| 566 | |
---|
| 567 | SC_START(1); |
---|
| 568 | |
---|
| 569 | // Test if read |
---|
| 570 | for (uint32_t j=0; j<_param->_nb_spr_read; j++) |
---|
| 571 | if (in_SPR_READ_VAL [j]->read() and out_SPR_READ_ACK [j]->read()) |
---|
| 572 | { |
---|
| 573 | TEST(Tspecial_data_t, out_SPR_READ_DATA [j]->read(), spr [i][spr_address[j]]); |
---|
| 574 | TEST(Tcontrol_t , out_SPR_READ_DATA_VAL[j]->read(), spr_status [i][spr_address[j]]); |
---|
| 575 | |
---|
| 576 | spr_address[j] = spr_address_next; |
---|
| 577 | |
---|
| 578 | if (spr_address_next >= _param->_nb_special_register [i]) |
---|
| 579 | nb_port_spr_active --; |
---|
| 580 | |
---|
| 581 | spr_address_next ++; |
---|
| 582 | } |
---|
| 583 | } |
---|
| 584 | } |
---|
| 585 | |
---|
| 586 | for (uint32_t i=0; i<_param->_nb_spr_read; i++) |
---|
| 587 | in_SPR_READ_VAL [i]->write(0); |
---|
| 588 | |
---|
| 589 | LABEL("insert rob"); |
---|
| 590 | |
---|
| 591 | uint32_t cpt = 0; |
---|
| 592 | |
---|
| 593 | while (cpt < nb_request) |
---|
| 594 | { |
---|
| 595 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 596 | { |
---|
| 597 | uint32_t x=_param->_nb_inst_insert_rob [i]; |
---|
| 598 | for (uint32_t j=0; j<x; j++) |
---|
| 599 | { |
---|
| 600 | in_INSERT_ROB_VAL [i][j]->write((rand() % 100) < percent_transaction_insert); |
---|
| 601 | in_INSERT_ROB_RD_USE [i][j]->write((rand() % 100) < percent_transaction_insert_use); |
---|
| 602 | in_INSERT_ROB_RD_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); |
---|
| 603 | in_INSERT_ROB_RE_USE [i][j]->write((rand() % 100) < percent_transaction_insert_use); |
---|
| 604 | in_INSERT_ROB_RE_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); |
---|
| 605 | } |
---|
| 606 | } |
---|
| 607 | |
---|
| 608 | SC_START(1); |
---|
| 609 | |
---|
| 610 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 611 | { |
---|
| 612 | uint32_t x=_param->_nb_inst_insert_rob [i]; |
---|
| 613 | for (uint32_t j=0; j<x; j++) |
---|
| 614 | { |
---|
| 615 | if (in_INSERT_ROB_VAL [i][j]->read() and out_INSERT_ROB_ACK [i][j]->read()) |
---|
| 616 | { |
---|
| 617 | cpt ++; |
---|
| 618 | |
---|
| 619 | if (in_INSERT_ROB_RD_USE [i][j]->read()) |
---|
| 620 | gpr_status [i][in_INSERT_ROB_RD_NUM_REG [i][j]->read()] = 0; |
---|
| 621 | |
---|
| 622 | if (in_INSERT_ROB_RE_USE [i][j]->read()) |
---|
| 623 | spr_status [i][in_INSERT_ROB_RE_NUM_REG [i][j]->read()] = 0; |
---|
| 624 | } |
---|
| 625 | } |
---|
| 626 | } |
---|
| 627 | } |
---|
| 628 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 629 | for (uint32_t j=0; j<_param->_nb_inst_insert_rob [i]; j++) |
---|
| 630 | in_INSERT_ROB_VAL [i][j]->write(0); |
---|
| 631 | |
---|
| 632 | LABEL("(GPR) Read - and test data writted"); |
---|
| 633 | |
---|
| 634 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 635 | { |
---|
| 636 | gpr_address_next = _param->_nb_gpr_read; |
---|
| 637 | nb_port_gpr_active = _param->_nb_gpr_read; |
---|
| 638 | |
---|
| 639 | for (uint32_t j=0; j<_param->_nb_gpr_read; j++) |
---|
| 640 | { |
---|
| 641 | gpr_address[j] = j; |
---|
| 642 | if (j >= _param->_nb_general_register [i]) |
---|
| 643 | nb_port_gpr_active --; |
---|
| 644 | } |
---|
| 645 | |
---|
| 646 | while (nb_port_gpr_active > 0) |
---|
| 647 | { |
---|
| 648 | for (uint32_t j=0; j<_param->_nb_gpr_read; j++) |
---|
| 649 | { |
---|
| 650 | in_GPR_READ_VAL [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and |
---|
| 651 | ((rand() % 100) < percent_transaction_read)); |
---|
| 652 | in_GPR_READ_OOO_ENGINE_ID [j]->write(i); |
---|
| 653 | in_GPR_READ_NUM_REG [j]->write(gpr_address[j]); |
---|
| 654 | } |
---|
| 655 | |
---|
| 656 | SC_START(1); |
---|
| 657 | |
---|
| 658 | // Test if read |
---|
| 659 | for (uint32_t j=0; j<_param->_nb_gpr_read; j++) |
---|
| 660 | if (in_GPR_READ_VAL [j]->read() and out_GPR_READ_ACK [j]->read()) |
---|
| 661 | { |
---|
| 662 | TEST(Tgeneral_data_t, out_GPR_READ_DATA [j]->read(), gpr [i][gpr_address[j]]); |
---|
| 663 | TEST(Tcontrol_t , out_GPR_READ_DATA_VAL[j]->read(), gpr_status [i][gpr_address[j]]); |
---|
| 664 | |
---|
| 665 | gpr_address[j] = gpr_address_next; |
---|
| 666 | |
---|
| 667 | if (gpr_address_next >= _param->_nb_general_register [i]) |
---|
| 668 | nb_port_gpr_active --; |
---|
| 669 | |
---|
| 670 | gpr_address_next ++; |
---|
| 671 | } |
---|
| 672 | } |
---|
| 673 | } |
---|
| 674 | |
---|
| 675 | for (uint32_t i=0; i<_param->_nb_gpr_read; i++) |
---|
| 676 | in_GPR_READ_VAL [i]->write(0); |
---|
| 677 | |
---|
| 678 | LABEL("(SPR) Read - and test data writted"); |
---|
| 679 | |
---|
| 680 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 681 | { |
---|
| 682 | spr_address_next = _param->_nb_spr_read; |
---|
| 683 | nb_port_spr_active = _param->_nb_spr_read; |
---|
| 684 | |
---|
| 685 | for (uint32_t j=0; j<_param->_nb_spr_read; j++) |
---|
| 686 | { |
---|
| 687 | spr_address[j] = j; |
---|
| 688 | if (j >= _param->_nb_special_register [i]) |
---|
| 689 | nb_port_spr_active --; |
---|
| 690 | } |
---|
| 691 | |
---|
| 692 | while (nb_port_spr_active > 0) |
---|
| 693 | { |
---|
| 694 | for (uint32_t j=0; j<_param->_nb_spr_read; j++) |
---|
| 695 | { |
---|
| 696 | in_SPR_READ_VAL [j]->write((spr_address[j] < _param->_nb_special_register [i]) and |
---|
| 697 | ((rand() % 100) < percent_transaction_read)); |
---|
| 698 | in_SPR_READ_OOO_ENGINE_ID [j]->write(i); |
---|
| 699 | in_SPR_READ_NUM_REG [j]->write(spr_address[j]); |
---|
| 700 | } |
---|
| 701 | |
---|
| 702 | SC_START(1); |
---|
| 703 | |
---|
| 704 | // Test if read |
---|
| 705 | for (uint32_t j=0; j<_param->_nb_spr_read; j++) |
---|
| 706 | if (in_SPR_READ_VAL [j]->read() and out_SPR_READ_ACK [j]->read()) |
---|
| 707 | { |
---|
| 708 | TEST(Tspecial_data_t, out_SPR_READ_DATA [j]->read(), spr [i][spr_address[j]]); |
---|
| 709 | TEST(Tcontrol_t , out_SPR_READ_DATA_VAL[j]->read(), spr_status [i][spr_address[j]]); |
---|
| 710 | |
---|
| 711 | spr_address[j] = spr_address_next; |
---|
| 712 | |
---|
| 713 | if (spr_address_next >= _param->_nb_special_register [i]) |
---|
| 714 | nb_port_spr_active --; |
---|
| 715 | |
---|
| 716 | spr_address_next ++; |
---|
| 717 | } |
---|
| 718 | } |
---|
| 719 | } |
---|
| 720 | |
---|
[88] | 721 | // LABEL("retire rob"); |
---|
[64] | 722 | |
---|
[88] | 723 | // cpt = 0; |
---|
[64] | 724 | |
---|
[88] | 725 | // while (cpt < nb_request) |
---|
| 726 | // { |
---|
| 727 | // for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 728 | // { |
---|
| 729 | // uint32_t x=_param->_nb_inst_retire_rob [i]; |
---|
| 730 | // for (uint32_t j=0; j<x; j++) |
---|
| 731 | // { |
---|
| 732 | // in_RETIRE_ROB_VAL [i][j]->write((rand() % 100) < percent_transaction_retire); |
---|
| 733 | // in_RETIRE_ROB_RD_OLD_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); |
---|
| 734 | // in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); |
---|
| 735 | // in_RETIRE_ROB_RD_NEW_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); |
---|
| 736 | // in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_general_register [i]); |
---|
| 737 | // in_RETIRE_ROB_RE_OLD_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); |
---|
| 738 | // in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); |
---|
| 739 | // in_RETIRE_ROB_RE_NEW_USE [i][j]->write((rand() % 100) < percent_transaction_retire_use); |
---|
| 740 | // in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->write(rand() % _param->_nb_special_register [i]); |
---|
| 741 | // } |
---|
| 742 | // } |
---|
[64] | 743 | |
---|
[88] | 744 | // SC_START(1); |
---|
[64] | 745 | |
---|
[88] | 746 | // for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 747 | // { |
---|
| 748 | // uint32_t x=_param->_nb_inst_retire_rob [i]; |
---|
| 749 | // for (uint32_t j=0; j<x; j++) |
---|
| 750 | // { |
---|
| 751 | // if (in_RETIRE_ROB_VAL [i][j]->read() and out_RETIRE_ROB_ACK [i][j]->read()) |
---|
| 752 | // { |
---|
| 753 | // cpt ++; |
---|
[64] | 754 | |
---|
[88] | 755 | // if (in_RETIRE_ROB_RD_OLD_USE [i][j]->read()) |
---|
| 756 | // gpr_status [i][in_RETIRE_ROB_RD_OLD_NUM_REG [i][j]->read()] = 0; |
---|
| 757 | // if (in_RETIRE_ROB_RD_NEW_USE [i][j]->read()) |
---|
| 758 | // gpr_status [i][in_RETIRE_ROB_RD_NEW_NUM_REG [i][j]->read()] = 1; |
---|
| 759 | // if (in_RETIRE_ROB_RE_OLD_USE [i][j]->read()) |
---|
| 760 | // spr_status [i][in_RETIRE_ROB_RE_OLD_NUM_REG [i][j]->read()] = 0; |
---|
| 761 | // if (in_RETIRE_ROB_RE_NEW_USE [i][j]->read()) |
---|
| 762 | // spr_status [i][in_RETIRE_ROB_RE_NEW_NUM_REG [i][j]->read()] = 1; |
---|
| 763 | // } |
---|
| 764 | // } |
---|
| 765 | // } |
---|
| 766 | // } |
---|
| 767 | // for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 768 | // for (uint32_t j=0; j<_param->_nb_inst_retire_rob [i]; j++) |
---|
| 769 | // in_RETIRE_ROB_VAL [i][j]->write(0); |
---|
[64] | 770 | |
---|
| 771 | LABEL("(GPR) Read - and test data writted"); |
---|
| 772 | |
---|
| 773 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 774 | { |
---|
| 775 | gpr_address_next = _param->_nb_gpr_read; |
---|
| 776 | nb_port_gpr_active = _param->_nb_gpr_read; |
---|
| 777 | |
---|
| 778 | for (uint32_t j=0; j<_param->_nb_gpr_read; j++) |
---|
| 779 | { |
---|
| 780 | gpr_address[j] = j; |
---|
| 781 | if (j >= _param->_nb_general_register [i]) |
---|
| 782 | nb_port_gpr_active --; |
---|
| 783 | } |
---|
| 784 | |
---|
| 785 | while (nb_port_gpr_active > 0) |
---|
| 786 | { |
---|
| 787 | for (uint32_t j=0; j<_param->_nb_gpr_read; j++) |
---|
| 788 | { |
---|
| 789 | in_GPR_READ_VAL [j]->write((gpr_address[j] < _param->_nb_general_register [i]) and |
---|
| 790 | ((rand() % 100) < percent_transaction_read)); |
---|
| 791 | in_GPR_READ_OOO_ENGINE_ID [j]->write(i); |
---|
| 792 | in_GPR_READ_NUM_REG [j]->write(gpr_address[j]); |
---|
| 793 | } |
---|
| 794 | |
---|
| 795 | SC_START(1); |
---|
| 796 | |
---|
| 797 | // Test if read |
---|
| 798 | for (uint32_t j=0; j<_param->_nb_gpr_read; j++) |
---|
| 799 | if (in_GPR_READ_VAL [j]->read() and out_GPR_READ_ACK [j]->read()) |
---|
| 800 | { |
---|
| 801 | TEST(Tgeneral_data_t, out_GPR_READ_DATA [j]->read(), gpr [i][gpr_address[j]]); |
---|
| 802 | TEST(Tcontrol_t , out_GPR_READ_DATA_VAL[j]->read(), gpr_status [i][gpr_address[j]]); |
---|
| 803 | |
---|
| 804 | gpr_address[j] = gpr_address_next; |
---|
| 805 | |
---|
| 806 | if (gpr_address_next >= _param->_nb_general_register [i]) |
---|
| 807 | nb_port_gpr_active --; |
---|
| 808 | |
---|
| 809 | gpr_address_next ++; |
---|
| 810 | } |
---|
| 811 | } |
---|
| 812 | } |
---|
| 813 | |
---|
| 814 | for (uint32_t i=0; i<_param->_nb_gpr_read; i++) |
---|
| 815 | in_GPR_READ_VAL [i]->write(0); |
---|
| 816 | |
---|
| 817 | LABEL("(SPR) Read - and test data writted"); |
---|
| 818 | |
---|
| 819 | for (uint32_t i=0; i<_param->_nb_ooo_engine; i++) |
---|
| 820 | { |
---|
| 821 | spr_address_next = _param->_nb_spr_read; |
---|
| 822 | nb_port_spr_active = _param->_nb_spr_read; |
---|
| 823 | |
---|
| 824 | for (uint32_t j=0; j<_param->_nb_spr_read; j++) |
---|
| 825 | { |
---|
| 826 | spr_address[j] = j; |
---|
| 827 | if (j >= _param->_nb_special_register [i]) |
---|
| 828 | nb_port_spr_active --; |
---|
| 829 | } |
---|
| 830 | |
---|
| 831 | while (nb_port_spr_active > 0) |
---|
| 832 | { |
---|
| 833 | for (uint32_t j=0; j<_param->_nb_spr_read; j++) |
---|
| 834 | { |
---|
| 835 | in_SPR_READ_VAL [j]->write((spr_address[j] < _param->_nb_special_register [i]) and |
---|
| 836 | ((rand() % 100) < percent_transaction_read)); |
---|
| 837 | in_SPR_READ_OOO_ENGINE_ID [j]->write(i); |
---|
| 838 | in_SPR_READ_NUM_REG [j]->write(spr_address[j]); |
---|
| 839 | } |
---|
| 840 | |
---|
| 841 | SC_START(1); |
---|
| 842 | |
---|
| 843 | // Test if read |
---|
| 844 | for (uint32_t j=0; j<_param->_nb_spr_read; j++) |
---|
| 845 | if (in_SPR_READ_VAL [j]->read() and out_SPR_READ_ACK [j]->read()) |
---|
| 846 | { |
---|
| 847 | TEST(Tspecial_data_t, out_SPR_READ_DATA [j]->read(), spr [i][spr_address[j]]); |
---|
| 848 | TEST(Tcontrol_t , out_SPR_READ_DATA_VAL[j]->read(), spr_status [i][spr_address[j]]); |
---|
| 849 | |
---|
| 850 | spr_address[j] = spr_address_next; |
---|
| 851 | |
---|
| 852 | if (spr_address_next >= _param->_nb_special_register [i]) |
---|
| 853 | nb_port_spr_active --; |
---|
| 854 | |
---|
| 855 | spr_address_next ++; |
---|
| 856 | } |
---|
| 857 | } |
---|
| 858 | } |
---|
| 859 | |
---|
[60] | 860 | } |
---|
| 861 | |
---|
| 862 | /******************************************************** |
---|
| 863 | * Simulation - End |
---|
| 864 | ********************************************************/ |
---|
| 865 | |
---|
| 866 | TEST_OK ("End of Simulation"); |
---|
| 867 | delete _time; |
---|
| 868 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
---|
| 869 | |
---|
| 870 | delete in_CLOCK; |
---|
| 871 | delete in_NRESET; |
---|
| 872 | |
---|
| 873 | delete [] in_GPR_READ_VAL ; |
---|
| 874 | delete [] out_GPR_READ_ACK ; |
---|
| 875 | delete [] in_GPR_READ_OOO_ENGINE_ID ; |
---|
| 876 | delete [] in_GPR_READ_NUM_REG ; |
---|
| 877 | delete [] out_GPR_READ_DATA ; |
---|
| 878 | delete [] out_GPR_READ_DATA_VAL ; |
---|
| 879 | delete [] in_GPR_WRITE_VAL ; |
---|
| 880 | delete [] out_GPR_WRITE_ACK ; |
---|
| 881 | delete [] in_GPR_WRITE_OOO_ENGINE_ID ; |
---|
| 882 | delete [] in_GPR_WRITE_NUM_REG ; |
---|
| 883 | delete [] in_GPR_WRITE_DATA ; |
---|
| 884 | delete [] in_SPR_READ_VAL ; |
---|
| 885 | delete [] out_SPR_READ_ACK ; |
---|
| 886 | delete [] in_SPR_READ_OOO_ENGINE_ID ; |
---|
| 887 | delete [] in_SPR_READ_NUM_REG ; |
---|
| 888 | delete [] out_SPR_READ_DATA ; |
---|
| 889 | delete [] out_SPR_READ_DATA_VAL ; |
---|
| 890 | delete [] in_SPR_WRITE_VAL ; |
---|
| 891 | delete [] out_SPR_WRITE_ACK ; |
---|
| 892 | delete [] in_SPR_WRITE_OOO_ENGINE_ID ; |
---|
| 893 | delete [] in_SPR_WRITE_NUM_REG ; |
---|
| 894 | delete [] in_SPR_WRITE_DATA ; |
---|
| 895 | delete [] in_INSERT_ROB_VAL ; |
---|
| 896 | delete [] out_INSERT_ROB_ACK ; |
---|
| 897 | delete [] in_INSERT_ROB_RD_USE ; |
---|
| 898 | delete [] in_INSERT_ROB_RD_NUM_REG ; |
---|
| 899 | delete [] in_INSERT_ROB_RE_USE ; |
---|
| 900 | delete [] in_INSERT_ROB_RE_NUM_REG ; |
---|
[88] | 901 | // delete [] in_RETIRE_ROB_VAL ; |
---|
| 902 | // delete [] out_RETIRE_ROB_ACK ; |
---|
| 903 | // delete [] in_RETIRE_ROB_RD_OLD_USE ; |
---|
| 904 | // delete [] in_RETIRE_ROB_RD_OLD_NUM_REG ; |
---|
| 905 | // delete [] in_RETIRE_ROB_RD_NEW_USE ; |
---|
| 906 | // delete [] in_RETIRE_ROB_RD_NEW_NUM_REG ; |
---|
| 907 | // delete [] in_RETIRE_ROB_RE_OLD_USE ; |
---|
| 908 | // delete [] in_RETIRE_ROB_RE_OLD_NUM_REG ; |
---|
| 909 | // delete [] in_RETIRE_ROB_RE_NEW_USE ; |
---|
| 910 | // delete [] in_RETIRE_ROB_RE_NEW_NUM_REG ; |
---|
[60] | 911 | #endif |
---|
| 912 | |
---|
| 913 | delete _Register_unit; |
---|
| 914 | #ifdef STATISTICS |
---|
| 915 | delete _parameters_statistics; |
---|
| 916 | #endif |
---|
| 917 | } |
---|