/* * $Id: main.cpp 88 2008-12-10 18:31:39Z rosiere $ * * [ Description ] * */ #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/SelfTest/include/test.h" #define NB_PARAMS 18 void usage (int argc, char * argv[]) { err (_(" %s name_instance list_params.\n"),argv[0]); err (_("list_params is :\n")); err (_(" * nb_read_unit (uint32_t )\n")); err (_(" * nb_functionnal_unit (uint32_t )\n")); err (_(" * nb_load_store_unit (uint32_t )\n")); err (_(" * nb_write_unit (uint32_t )\n")); err (_(" * nb_context (uint32_t )\n")); err (_(" * nb_front_end (uint32_t )\n")); err (_(" * nb_ooo_engine (uint32_t )\n")); err (_(" * nb_packet (uint32_t )\n")); err (_(" * size_general_data (uint32_t )\n")); err (_(" * size_special_data (uint32_t )\n")); err (_(" * size_read_queue [nb_read_unit] (uint32_t )\n")); err (_(" * size_reservation_station [nb_read_unit] (uint32_t )\n")); err (_(" * nb_inst_retire [nb_read_unit] (uint32_t )\n")); err (_(" * nb_inst_functionnal_unit [nb_functionnal_unit] (uint32_t )\n")); err (_(" * size_store_queue [nb_load_store_unit] (uint32_t )\n")); err (_(" * size_load_queue [nb_load_store_unit] (uint32_t )\n")); err (_(" * size_speculative_access_queue [nb_load_store_unit] (uint32_t )\n")); err (_(" * nb_port_check [nb_load_store_unit] (uint32_t )\n")); err (_(" * speculative_load [nb_load_store_unit] (Tspeculative_load_t)\n")); err (_(" * nb_bypass_memory [nb_load_store_unit] (uint32_t )\n")); err (_(" * nb_cache_port [nb_load_store_unit] (uint32_t )\n")); err (_(" * nb_inst_memory [nb_load_store_unit] (uint32_t )\n")); err (_(" * size_write_queue [nb_write_unit] (uint32_t )\n")); err (_(" * size_execute_queue [nb_write_unit] (uint32_t )\n")); err (_(" * nb_bypass_write [nb_write_unit] (uint32_t )\n")); err (_(" * nb_gpr_bank (uint32_t )\n")); err (_(" * nb_gpr_port_read_by_bank (uint32_t )\n")); err (_(" * nb_gpr_port_write_by_bank (uint32_t )\n")); err (_(" * nb_spr_bank (uint32_t )\n")); err (_(" * nb_spr_port_read_by_bank (uint32_t )\n")); err (_(" * nb_spr_port_write_by_bank (uint32_t )\n")); err (_(" * nb_general_register [nb_ooo_engine] (uint32_t )\n")); err (_(" * nb_special_register [nb_ooo_engine] (uint32_t )\n")); err (_(" * nb_inst_insert_rob [nb_ooo_engine] (uint32_t )\n")); err (_(" * nb_inst_retire_rob [nb_ooo_engine] (uint32_t )\n")); err (_(" * execution_unit_to_write_unit_priority (Tpriority_t )\n")); err (_(" * execution_unit_to_write_unit_table_routing[nb_execute_unit][nb_execute_unit_port][nb_write_unit] (bool )\n")); err (_(" * execution_unit_to_write_unit_table_thread [nb_write_unit][nb_thread] (bool )\n")); err (_(" * read_unit_to_execution_unit_priority (Tpriority_t )\n")); err (_(" * read_unit_to_execution_unit_table_routing [nb_read_unit][nb_execute_unit][nb_execute_unit_port] (bool )\n")); err (_(" * read_unit_to_execution_unit_table_thread [nb_execute_unit][nb_thread] (bool )\n")); err (_(" * is_load_store_unit [nb_execute_unit] (bool )\n")); err (_(" * translate_num_execute_unit [nb_execute_unit] (uint32_t )\n")); exit (1); } #ifndef SYSTEMC int main (int argc, char * argv[]) #else int sc_main (int argc, char * argv[]) #endif { // Command for (int32_t i=0; i(argv[x++]); uint32_t * nb_bypass_memory = new uint32_t [nb_load_store_unit]; for (uint32_t i=0; i(argv[x++]); bool *** execution_unit_to_write_unit_table_routing = new bool ** [nb_execute_unit]; for (uint32_t i=0; i(argv[x++]); bool *** read_unit_to_execution_unit_table_routing = new bool ** [nb_read_unit]; for (uint32_t i=0; i(argv[x++]); uint32_t * translate_num_execute_unit = new uint32_t [nb_execute_unit]; for (uint32_t i=0; i(argv[x++]); execute_timing_t *** timing = new execute_timing_t ** [nb_functionnal_unit]; // alloc and reset timing array for (uint32_t i=0; i< nb_functionnal_unit; i++) { timing [i] = new execute_timing_t * [MAX_TYPE]; for (uint32_t j=0; j< MAX_TYPE; j++) { timing [i][j]= new execute_timing_t [MAX_OPERATION]; for (uint32_t k=0; k< MAX_OPERATION; k++) timing[i][j][k]._delay = timing[i][j][k]._latence = 0; } } for (uint32_t i=0; i< nb_functionnal_unit; i++) for (uint32_t j=0; j< MAX_TYPE; j++) { if ( (j != TYPE_MEMORY) and not ((i!=0) and ((j == TYPE_SPECIAL) or (j == TYPE_CUSTOM)))) for (uint32_t k=0; k< MAX_OPERATION; k++) timing[i][j][k]._delay = timing[i][j][k]._latence = 1; } morpheo::behavioural::custom::custom_information_t (*get_custom_information) (void) = &(morpheo::behavioural::custom::default_get_custom_information); try { morpheo::behavioural::core::multi_execute_loop::execute_loop::Parameters * param = new morpheo::behavioural::core::multi_execute_loop::execute_loop::Parameters (nb_read_unit , nb_functionnal_unit , nb_load_store_unit , nb_write_unit , nb_context , nb_front_end , nb_ooo_engine , nb_packet , size_general_data , size_special_data , size_read_queue , size_reservation_station , nb_inst_retire , nb_inst_functionnal_unit , timing , get_custom_information , size_store_queue , size_load_queue , size_speculative_access_queue , nb_port_check , speculative_load , nb_bypass_memory , nb_cache_port , nb_inst_memory , size_write_queue , size_execute_queue , nb_bypass_write , nb_gpr_bank , nb_gpr_port_read_by_bank , nb_gpr_port_write_by_bank , nb_spr_bank , nb_spr_port_read_by_bank , nb_spr_port_write_by_bank , nb_general_register , nb_special_register , nb_inst_insert_rob , nb_inst_retire_rob , execution_unit_to_write_unit_priority , execution_unit_to_write_unit_table_routing , execution_unit_to_write_unit_table_thread , read_unit_to_execution_unit_priority , read_unit_to_execution_unit_table_routing , read_unit_to_execution_unit_table_thread , is_load_store_unit , //[nb_execute_unit] translate_num_execute_unit , //[nb_execute_unit] true // is_toplevel ); test (name,param); } catch (morpheo::ErrorMorpheo & error) { msg (_("%s\n"),error.what ()); exit (EXIT_FAILURE); } catch (...) { err (_("This test must generate a error.\n")); exit (EXIT_FAILURE); } return (EXIT_SUCCESS); }