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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/src/Execute_loop_allocation.cpp @ 82

Last change on this file since 82 was 82, checked in by rosiere, 16 years ago
support locale (now must "just" translate) update all component with new test format update all component with usage New component : decod queue and prediction_unit
Property svn:keywords set to `Id`
File size: 88.1 KB

Line
1	/*
2	* $Id: Execute_loop_allocation.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "Behavioural/Core/Multi_Execute_loop/Execute_loop/include/Execute_loop.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_execute_loop {
15	namespace execute_loop {
16
17
18
19	#undef FUNCTION
20	#define FUNCTION "Execute_loop::allocation"
21	void Execute_loop::allocation (
22	#ifdef STATISTICS
23	morpheo::behavioural::Parameters_Statistics * param_statistics
24	#else
25	void
26	#endif
27	)
28	{
29	log_printf(FUNC,Execute_loop,FUNCTION,"Begin");
30
31	_component = new Component (_usage);
32
33	Entity * entity = _component->set_entity (_name
34	,"Execute_loop"
35	#ifdef POSITION
36	,COMBINATORY
37	#endif
38	);
39
40	_interfaces = entity->set_interfaces();
41
42	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
43
44	Interface * interface = _interfaces->set_interface(""
45	#ifdef POSITION
46	,IN
47	,SOUTH,
48	"Generalist interface"
49	#endif
50	);
51
52	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
53	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
54
55	// ~~~~~[ Interface "execute_loop_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
56	{
57	ALLOC1_INTERFACE("execute_loop_in", IN, EAST, "Operation's Input", _param->_nb_read_unit);
58
59	ALLOC1_VALACK_IN ( in_EXECUTE_LOOP_IN_VAL,VAL);
60	ALLOC1_VALACK_OUT(out_EXECUTE_LOOP_IN_ACK,ACK);
61	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id);
62	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id);
63	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id);
64	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id);
65	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation);
66	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type);
67	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_max_size_store_queue);
68	if (_param->_have_port_load_queue_ptr)
69	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_max_size_load_queue);
70	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1);
71	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data);
72	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_READ_RA ,"read_ra" ,Tcontrol_t ,1);
73	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_NUM_REG_RA ,"num_reg_ra" ,Tgeneral_address_t,_param->_size_general_register);
74	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_READ_RB ,"read_rb" ,Tcontrol_t ,1);
75	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_NUM_REG_RB ,"num_reg_rb" ,Tgeneral_address_t,_param->_size_general_register);
76	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_READ_RC ,"read_rc" ,Tcontrol_t ,1);
77	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_NUM_REG_RC ,"num_reg_rc" ,Tspecial_address_t,_param->_size_special_register);
78	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1);
79	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register);
80	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1);
81	ALLOC1_SIGNAL_IN ( in_EXECUTE_LOOP_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_special_register);
82	}
83	// ~~~~~[ Interface "execute_loop_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
84	{
85	ALLOC1_INTERFACE("execute_loop_out",OUT, EAST, "Operation's Output", _param->_nb_write_unit);
86
87	ALLOC1_VALACK_OUT(out_EXECUTE_LOOP_OUT_VAL,VAL);
88	ALLOC1_VALACK_IN ( in_EXECUTE_LOOP_OUT_ACK,ACK);
89	ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id);
90	ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id);
91	ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_OOO_ENGINE_ID,"ooo_engine_id",Tcontext_t ,_param->_size_ooo_engine_id);
92	ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_packet_id);
93	// ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation);
94	// ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type);
95	ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_FLAGS ,"flags" ,Tspecial_data_t,_param->_size_special_data);
96	ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception);
97	ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1);
98	ALLOC1_SIGNAL_OUT(out_EXECUTE_LOOP_OUT_ADDRESS ,"address" ,Tgeneral_data_t,_param->_size_general_data);
99	}
100	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
101	{
102	ALLOC1_INTERFACE("dcache_req",OUT, NORTH, "Data cache port : request", _param->_nb_load_store_unit);
103
104	ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL,VAL);
105	ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK,ACK);
106	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID,"context_id",Tcontext_t ,_param->_max_size_dcache_context_id);
107	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_max_size_dcache_packet_id );
108	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t,_param->_size_general_data);
109	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type);
110	ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data);
111	}
112	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
113	{
114	ALLOC1_INTERFACE("dcache_rsp",IN, NORTH, "Data cache port : respons", _param->_nb_load_store_unit);
115
116	ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL,VAL);
117	ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK,ACK);
118	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID,"context_id",Tcontext_t ,_param->_max_size_dcache_context_id);
119	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_max_size_dcache_packet_id);
120	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data);
121	ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error);
122	}
123	// ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
124	{
125	ALLOC2_INTERFACE("insert_rob",IN, EAST, "Rename's stage : insert a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_interface_it1]);
126
127	_ALLOC2_VALACK_IN ( in_INSERT_ROB_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]);
128	_ALLOC2_VALACK_OUT(out_INSERT_ROB_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]);
129
130	_ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RD_USE ,"rd_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]);
131	_ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RD_NUM_REG,"rd_num_reg",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]);
132	_ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_USE ,"re_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]);
133	_ALLOC2_SIGNAL_IN ( in_INSERT_ROB_RE_NUM_REG,"re_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_insert_rob[alloc_signal_it1]);
134	}
135	// ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
136	{
137	ALLOC2_INTERFACE("retire_rob",IN, EAST, "Rename's stage : retire a new instruction in the Re Order Buffer",_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_interface_it1]);
138
139	_ALLOC2_VALACK_IN ( in_RETIRE_ROB_VAL,VAL,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
140	_ALLOC2_VALACK_OUT(out_RETIRE_ROB_ACK,ACK,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
141
142	_ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_OLD_USE ,"rd_old_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
143	_ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_OLD_NUM_REG,"rd_old_num_reg",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
144	_ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_NEW_USE ,"rd_new_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
145	_ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RD_NEW_NUM_REG,"rd_new_num_reg",Tgeneral_address_t,_param->_size_general_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
146	_ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_OLD_USE ,"re_old_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
147	_ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_OLD_NUM_REG,"re_old_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
148	_ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_NEW_USE ,"re_new_use" ,Tcontrol_t ,1 ,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
149	_ALLOC2_SIGNAL_IN ( in_RETIRE_ROB_RE_NEW_NUM_REG,"re_new_num_reg",Tspecial_address_t,_param->_size_special_register,_param->_nb_ooo_engine,_param->_nb_inst_retire_rob[alloc_signal_it1]);
150	}
151
152	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
153	std::string name;
154
155	_component_read_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::Read_unit * [_param->_nb_read_unit];
156	for (uint32_t i=0; i<_param->_nb_read_unit; i++)
157	{
158	name = _name+"_read_unit_"+toString(i);
159	std::cout << "Create : " << name << std::endl;
160
161	_component_read_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_read_unit::read_unit::Read_unit
162	(name.c_str()
163	#ifdef STATISTICS
164	,param_statistics
165	#endif
166	,_param->_param_read_unit[i]
167	,_usage);
168
169	_component->set_component (_component_read_unit [i]->_component
170	#ifdef POSITION
171	, 50, 50, 10, 10
172	#endif
173	);
174	}
175
176	_component_functionnal_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::Functionnal_unit * [_param->_nb_functionnal_unit];
177	for (uint32_t i=0; i<_param->_nb_functionnal_unit; i++)
178	{
179	name = _name+"_functionnal_unit_"+toString(i);
180	std::cout << "Create : " << name << std::endl;
181
182	_component_functionnal_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::functionnal_unit::Functionnal_unit
183	(name.c_str()
184	#ifdef STATISTICS
185	,param_statistics
186	#endif
187	,_param->_param_functionnal_unit[i]
188	,_usage);
189
190	_component->set_component (_component_functionnal_unit [i]->_component
191	#ifdef POSITION
192	, 50, 50, 10, 10
193	#endif
194	);
195	}
196
197	_component_load_store_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit * [_param->_nb_load_store_unit];
198	for (uint32_t i=0; i<_param->_nb_load_store_unit; i++)
199	{
200	name = _name+"_load_store_unit_"+toString(i);
201	std::cout << "Create : " << name << std::endl;
202
203	_component_load_store_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_execute_unit::execute_unit::load_store_unit::Load_store_unit
204	(name.c_str()
205	#ifdef STATISTICS
206	,param_statistics
207	#endif
208	,_param->_param_load_store_unit[i]
209	,_usage);
210
211	_component->set_component (_component_load_store_unit [i]->_component
212	#ifdef POSITION
213	, 50, 50, 10, 10
214	#endif
215	);
216	}
217
218	_component_write_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::Write_unit * [_param->_nb_write_unit];
219	for (uint32_t i=0; i<_param->_nb_write_unit; i++)
220	{
221	name = _name+"_write_unit_"+toString(i);
222	std::cout << "Create : " << name << std::endl;
223
224	_component_write_unit [i] = new morpheo::behavioural::core::multi_execute_loop::execute_loop::multi_write_unit::write_unit::Write_unit
225	(name.c_str()
226	#ifdef STATISTICS
227	,param_statistics
228	#endif
229	,_param->_param_write_unit[i]
230	,_usage);
231
232	_component->set_component (_component_write_unit [i]->_component
233	#ifdef POSITION
234	, 50, 50, 10, 10
235	#endif
236	);
237	}
238
239	{
240	name = _name+"_read_unit_to_execution_unit";
241	std::cout << "Create : " << name << std::endl;
242
243	_component_read_unit_to_execution_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::network::read_unit_to_execution_unit::Read_unit_to_Execution_unit
244	(name.c_str()
245	#ifdef STATISTICS
246	,param_statistics
247	#endif
248	,_param->_param_read_unit_to_execution_unit
249	,_usage);
250
251	_component->set_component (_component_read_unit_to_execution_unit->_component
252	#ifdef POSITION
253	, 50, 50, 10, 10
254	#endif
255	);
256	}
257
258	{
259	name = _name+"_execution_unit_to_write_unit";
260	std::cout << "Create : " << name << std::endl;
261
262	_component_execution_unit_to_write_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::network::execution_unit_to_write_unit::Execution_unit_to_Write_unit
263	(name.c_str()
264	#ifdef STATISTICS
265	,param_statistics
266	#endif
267	,_param->_param_execution_unit_to_write_unit
268	,_usage);
269
270	_component->set_component (_component_execution_unit_to_write_unit->_component
271	#ifdef POSITION
272	, 50, 50, 10, 10
273	#endif
274	);
275	}
276
277	{
278	name = _name+"_register_unit";
279	std::cout << "Create : " << name << std::endl;
280
281	_component_register_unit = new morpheo::behavioural::core::multi_execute_loop::execute_loop::register_unit::Register_unit
282	(name.c_str()
283	#ifdef STATISTICS
284	,param_statistics
285	#endif
286	,_param->_param_register_unit
287	,_usage);
288
289	_component->set_component (_component_register_unit->_component
290	#ifdef POSITION
291	, 50, 50, 10, 10
292	#endif
293	);
294	}
295
296	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
297	std::string src,dest;
298
299	// ===================================================================
300	// =====[ READ_UNIT ]=================================================
301	// ===================================================================
302	{
303	uint32_t it_read_unit_out = 0;
304
305	for (uint32_t i=0; i<_param->_nb_read_unit; i++)
306	{
307	src = _name+"_read_unit_"+toString(i);
308	std::cout << "Instance : " << src << std::endl;
309
310	{
311	dest = _name;
312	#ifdef POSITION
313	_component->interface_map (src ,"",
314	dest,"");
315	#endif
316	PORT_MAP(_component ,src , "in_CLOCK" ,dest, "in_CLOCK");
317	PORT_MAP(_component ,src , "in_NRESET",dest, "in_NRESET");
318	}
319
320	// ~~~~~[ Interface "read_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
321	{
322	dest = _name;
323	#ifdef POSITION
324	_component->interface_map (src ,"read_unit_in",
325	dest,"execute_loop_in_"+toString(i));
326	#endif
327
328	PORT_MAP(_component ,src , "in_READ_UNIT_IN_VAL" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_VAL" );
329	PORT_MAP(_component ,src ,"out_READ_UNIT_IN_ACK" ,dest ,"out_EXECUTE_LOOP_IN_"+toString(i)+"_ACK" );
330	if (_param->_have_port_context_id)
331	PORT_MAP(_component ,src , "in_READ_UNIT_IN_CONTEXT_ID" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_CONTEXT_ID" );
332	if (_param->_have_port_front_end_id)
333	PORT_MAP(_component ,src , "in_READ_UNIT_IN_FRONT_END_ID" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_FRONT_END_ID" );
334	if (_param->_have_port_ooo_engine_id)
335	PORT_MAP(_component ,src , "in_READ_UNIT_IN_OOO_ENGINE_ID" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_OOO_ENGINE_ID" );
336	if (_param->_have_port_packet_id)
337	PORT_MAP(_component ,src , "in_READ_UNIT_IN_PACKET_ID" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_PACKET_ID" );
338	PORT_MAP(_component ,src , "in_READ_UNIT_IN_OPERATION" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_OPERATION" );
339	PORT_MAP(_component ,src , "in_READ_UNIT_IN_TYPE" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_TYPE" );
340	PORT_MAP(_component ,src , "in_READ_UNIT_IN_STORE_QUEUE_PTR_WRITE",dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE");
341	if (_param->_have_port_load_queue_ptr)
342	PORT_MAP(_component ,src , "in_READ_UNIT_IN_LOAD_QUEUE_PTR_WRITE" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" );
343	PORT_MAP(_component ,src , "in_READ_UNIT_IN_HAS_IMMEDIAT" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_HAS_IMMEDIAT" );
344	PORT_MAP(_component ,src , "in_READ_UNIT_IN_IMMEDIAT" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_IMMEDIAT" );
345	PORT_MAP(_component ,src , "in_READ_UNIT_IN_READ_RA" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_READ_RA" );
346	PORT_MAP(_component ,src , "in_READ_UNIT_IN_NUM_REG_RA" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_NUM_REG_RA" );
347	PORT_MAP(_component ,src , "in_READ_UNIT_IN_READ_RB" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_READ_RB" );
348	PORT_MAP(_component ,src , "in_READ_UNIT_IN_NUM_REG_RB" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_NUM_REG_RB" );
349	PORT_MAP(_component ,src , "in_READ_UNIT_IN_READ_RC" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_READ_RC" );
350	PORT_MAP(_component ,src , "in_READ_UNIT_IN_NUM_REG_RC" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_NUM_REG_RC" );
351	PORT_MAP(_component ,src , "in_READ_UNIT_IN_WRITE_RD" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_WRITE_RD" );
352	PORT_MAP(_component ,src , "in_READ_UNIT_IN_NUM_REG_RD" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_NUM_REG_RD" );
353	PORT_MAP(_component ,src , "in_READ_UNIT_IN_WRITE_RE" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_WRITE_RE" );
354	PORT_MAP(_component ,src , "in_READ_UNIT_IN_NUM_REG_RE" ,dest , "in_EXECUTE_LOOP_IN_"+toString(i)+"_NUM_REG_RE" );
355	}
356
357	// ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
358	for (uint32_t j=0; j < _param->_nb_inst_retire[i]; j++)
359	{
360	dest = _name+"_read_unit_to_execution_unit";
361
362	#ifdef POSITION
363	_component->interface_map (src ,"read_unit_"+toString(i),
364	dest,"read_unit_"+toString(it_read_unit_out));
365	#endif
366
367	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_VAL" ,
368	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_VAL" );
369	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(i )+"_ACK" ,
370	dest,"out_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_ACK" );
371	if (_param->_have_port_context_id)
372	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_CONTEXT_ID" ,
373	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_CONTEXT_ID" );
374	if (_param->_have_port_front_end_id)
375	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_FRONT_END_ID" ,
376	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_FRONT_END_ID" );
377	if (_param->_have_port_ooo_engine_id)
378	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_OOO_ENGINE_ID" ,
379	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OOO_ENGINE_ID" );
380	if (_param->_have_port_packet_id)
381	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_PACKET_ID" ,
382	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_PACKET_ID" );
383	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_OPERATION" ,
384	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OPERATION" );
385	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_TYPE" ,
386	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_TYPE" );
387	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_STORE_QUEUE_PTR_WRITE",
388	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_STORE_QUEUE_PTR_WRITE");
389	if (_param->_have_port_load_queue_ptr)
390	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_LOAD_QUEUE_PTR_WRITE" ,
391	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_LOAD_QUEUE_PTR_WRITE" );
392	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_HAS_IMMEDIAT" ,
393	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_HAS_IMMEDIAT" );
394	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_IMMEDIAT" ,
395	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_IMMEDIAT" );
396	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_DATA_RA" ,
397	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RA" );
398	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_DATA_RB" ,
399	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RB" );
400	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_DATA_RC" ,
401	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RC" );
402	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_WRITE_RD" ,
403	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RD" );
404	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_NUM_REG_RD" ,
405	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RD" );
406	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_WRITE_RE" ,
407	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RE" );
408	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(i )+"_NUM_REG_RE" ,
409	dest, "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RE" );
410
411	it_read_unit_out ++;
412	}
413
414	// ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
415	{
416	dest = _name+"_register_unit";
417	#ifdef POSITION
418	_component->interface_map (src ,"gpr_read_0",
419	dest,"gpr_read_"+toString(2*i ));
420	_component->interface_map (src ,"gpr_read_1",
421	dest,"gpr_read_"+toString(2*i+1));
422	#endif
423	PORT_MAP(_component ,src ,"out_GPR_READ_0_VAL" , dest, "in_GPR_READ_"+toString(2*i )+"_VAL" );
424	PORT_MAP(_component ,src , "in_GPR_READ_0_ACK" , dest,"out_GPR_READ_"+toString(2*i )+"_ACK" );
425	if (_param->_have_port_ooo_engine_id)
426	PORT_MAP(_component ,src ,"out_GPR_READ_0_OOO_ENGINE_ID", dest, "in_GPR_READ_"+toString(2*i )+"_OOO_ENGINE_ID");
427	PORT_MAP(_component ,src ,"out_GPR_READ_0_NUM_REG" , dest, "in_GPR_READ_"+toString(2*i )+"_NUM_REG" );
428	PORT_MAP(_component ,src , "in_GPR_READ_0_DATA" , dest,"out_GPR_READ_"+toString(2*i )+"_DATA" );
429	PORT_MAP(_component ,src , "in_GPR_READ_0_DATA_VAL" , dest,"out_GPR_READ_"+toString(2*i )+"_DATA_VAL" );
430	PORT_MAP(_component ,src ,"out_GPR_READ_1_VAL" , dest, "in_GPR_READ_"+toString(2*i+1)+"_VAL" );
431	PORT_MAP(_component ,src , "in_GPR_READ_1_ACK" , dest,"out_GPR_READ_"+toString(2*i+1)+"_ACK" );
432	if (_param->_have_port_ooo_engine_id)
433	PORT_MAP(_component ,src ,"out_GPR_READ_1_OOO_ENGINE_ID", dest, "in_GPR_READ_"+toString(2*i+1)+"_OOO_ENGINE_ID");
434	PORT_MAP(_component ,src ,"out_GPR_READ_1_NUM_REG" , dest, "in_GPR_READ_"+toString(2*i+1)+"_NUM_REG" );
435	PORT_MAP(_component ,src , "in_GPR_READ_1_DATA" , dest,"out_GPR_READ_"+toString(2*i+1)+"_DATA" );
436	PORT_MAP(_component ,src , "in_GPR_READ_1_DATA_VAL" , dest,"out_GPR_READ_"+toString(2*i+1)+"_DATA_VAL" );
437	}
438
439	// ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
440	{
441	dest = _name+"_register_unit";
442	#ifdef POSITION
443	_component->interface_map (src ,"spr_read_0",
444	dest,"spr_read_"+toString(2*i ));
445	#endif
446	PORT_MAP(_component ,src ,"out_SPR_READ_0_VAL" , dest, "in_SPR_READ_"+toString(2*i )+"_VAL" );
447	PORT_MAP(_component ,src , "in_SPR_READ_0_ACK" , dest,"out_SPR_READ_"+toString(2*i )+"_ACK" );
448	if (_param->_have_port_ooo_engine_id)
449	PORT_MAP(_component ,src ,"out_SPR_READ_0_OOO_ENGINE_ID", dest, "in_SPR_READ_"+toString(2*i )+"_OOO_ENGINE_ID");
450	PORT_MAP(_component ,src ,"out_SPR_READ_0_NUM_REG" , dest, "in_SPR_READ_"+toString(2*i )+"_NUM_REG" );
451	PORT_MAP(_component ,src , "in_SPR_READ_0_DATA" , dest,"out_SPR_READ_"+toString(2*i )+"_DATA" );
452	PORT_MAP(_component ,src , "in_SPR_READ_0_DATA_VAL" , dest,"out_SPR_READ_"+toString(2*i )+"_DATA_VAL" );
453	}
454
455	// ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
456	uint32_t it_gpr_write = 0;
457	for (std::set<uint32_t>::iterator it=_param->_set_read_unit_source_register_write[i].begin();
458	it!=_param->_set_read_unit_source_register_write[i].end();
459	it++)
460	{
461	dest = _name+"_write_unit_"+toString(*it);
462	#ifdef POSITION
463	_component->interface_map (src ,"gpr_write_"+toString(it_gpr_write),
464	dest,"gpr_write");
465	#endif
466
467	PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_VAL" ,
468	dest,"out_GPR_WRITE_0_VAL" );
469	if (_param->_have_port_ooo_engine_id)
470	PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_OOO_ENGINE_ID",
471	dest,"out_GPR_WRITE_0_OOO_ENGINE_ID");
472	PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_NUM_REG" ,
473	dest,"out_GPR_WRITE_0_NUM_REG" );
474	PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_DATA" ,
475	dest,"out_GPR_WRITE_0_DATA" );
476
477	// PORT MAP to the "write_unit" component
478	#ifdef POSITION
479	_component->interface_map (dest,"gpr_write",
480	src ,"gpr_write_"+toString(it_gpr_write));
481	#endif
482
483	PORT_MAP(_component ,dest,"out_GPR_WRITE_0_VAL" ,
484	src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_VAL" );
485	if (_param->_have_port_ooo_engine_id)
486	PORT_MAP(_component ,dest,"out_GPR_WRITE_0_OOO_ENGINE_ID",
487	src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_OOO_ENGINE_ID");
488	PORT_MAP(_component ,dest,"out_GPR_WRITE_0_NUM_REG" ,
489	src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_NUM_REG" );
490	PORT_MAP(_component ,dest,"out_GPR_WRITE_0_DATA" ,
491	src , "in_GPR_WRITE_"+toString(it_gpr_write)+"_DATA" );
492
493	it_gpr_write ++;
494	}
495
496	// ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
497	uint32_t it_spr_write = 0;
498	for (std::set<uint32_t>::iterator it=_param->_set_read_unit_source_register_write[i].begin();
499	it!=_param->_set_read_unit_source_register_write[i].end();
500	it++)
501	{
502	dest = _name+"_write_unit_"+toString(*it);
503	#ifdef POSITION
504	_component->interface_map (src ,"spr_write_"+toString(it_spr_write),
505	dest,"spr_write");
506	#endif
507
508	PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_VAL" ,
509	dest,"out_SPR_WRITE_0_VAL" );
510	if (_param->_have_port_ooo_engine_id)
511	PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_OOO_ENGINE_ID",
512	dest,"out_SPR_WRITE_0_OOO_ENGINE_ID");
513	PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_NUM_REG" ,
514	dest,"out_SPR_WRITE_0_NUM_REG" );
515	PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(it_spr_write)+"_DATA" ,
516	dest,"out_SPR_WRITE_0_DATA" );
517
518	// PORT MAP to the "write_unit" component
519	#ifdef POSITION
520	_component->interface_map (dest,"spr_write",
521	src ,"spr_write_"+toString(it_spr_write));
522	#endif
523	PORT_MAP(_component ,dest,"out_SPR_WRITE_0_VAL" ,
524	src , "in_SPR_WRITE_"+toString(it_spr_write)+"_VAL" );
525	if (_param->_have_port_ooo_engine_id)
526	PORT_MAP(_component ,dest,"out_SPR_WRITE_0_OOO_ENGINE_ID",
527	src , "in_SPR_WRITE_"+toString(it_spr_write)+"_OOO_ENGINE_ID");
528	PORT_MAP(_component ,dest,"out_SPR_WRITE_0_NUM_REG" ,
529	src , "in_SPR_WRITE_"+toString(it_spr_write)+"_NUM_REG" );
530	PORT_MAP(_component ,dest,"out_SPR_WRITE_0_DATA" ,
531	src , "in_SPR_WRITE_"+toString(it_spr_write)+"_DATA" );
532
533	it_spr_write ++;
534	}
535
536	// ~~~~~[ Interface "bypass_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
537	uint32_t it_bypass_write = 0;
538	for (std::set<uint32_t>::iterator it=_param->_set_read_unit_source_bypass_write[i].begin();
539	it!=_param->_set_read_unit_source_bypass_write[i].end();
540	it++)
541	{
542	dest = _name+"_write_unit_"+toString(*it);
543
544	for (uint32_t j=0; j<_param->_nb_bypass_write[*it]; j++)
545	{
546	#ifdef POSITION
547	_component->interface_map (src ,"bypass_write_"+toString(it_bypass_write),
548	dest,"bypass_write_"+toString(j));
549	#endif
550
551	if (_param->_have_port_ooo_engine_id)
552	PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_OOO_ENGINE_ID",
553	dest,"out_BYPASS_WRITE_"+toString(j )+"_OOO_ENGINE_ID");
554	PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_VAL" ,
555	dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_VAL" );
556	PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_NUM_REG" ,
557	dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_NUM_REG" );
558	PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_DATA" ,
559	dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_DATA" );
560	PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_VAL" ,
561	dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_VAL" );
562	PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_NUM_REG" ,
563	dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_NUM_REG" );
564	PORT_MAP(_component ,src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_DATA" ,
565	dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_DATA" );
566
567	#ifdef POSITION
568	_component->interface_map (dest,"bypass_write_"+toString(j),
569	src ,"bypass_write_"+toString(it_bypass_write));
570	#endif
571
572	if (_param->_have_port_ooo_engine_id)
573	PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_OOO_ENGINE_ID",
574	src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_OOO_ENGINE_ID");
575	PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_VAL" ,
576	src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_VAL" );
577	PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_NUM_REG" ,
578	src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_NUM_REG" );
579	PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_GPR_DATA" ,
580	src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_GPR_DATA" );
581	PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_VAL" ,
582	src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_VAL" );
583	PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_NUM_REG" ,
584	src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_NUM_REG" );
585	PORT_MAP(_component ,dest,"out_BYPASS_WRITE_"+toString(j )+"_SPR_DATA" ,
586	src , "in_BYPASS_WRITE_"+toString(it_bypass_write)+"_SPR_DATA" );
587
588	it_bypass_write ++;
589	}
590	}
591
592	// ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
593	uint32_t it_bypass_memory = 0;
594	for (std::set<uint32_t>::iterator it=_param->_set_read_unit_source_bypass_memory[i].begin();
595	it!=_param->_set_read_unit_source_bypass_memory[i].end();
596	it++)
597	{
598	dest = _name+"_load_store_unit_"+toString(_param->_translate_num_execute_unit[*it]);
599
600	for (uint32_t j=0; j<_param->_nb_bypass_memory[_param->_translate_num_execute_unit[*it]]; j++)
601	{
602	#ifdef POSITION
603	_component->interface_map (src ,"bypass_memory_"+toString(it_bypass_memory),
604	dest,"bypass_memory_"+toString(j));
605	#endif
606
607	if (_param->_have_port_ooo_engine_id)
608	PORT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_OOO_ENGINE_ID",
609	dest,"out_BYPASS_MEMORY_"+toString(j )+"_OOO_ENGINE_ID");
610	PORT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_VAL" ,
611	dest,"out_BYPASS_MEMORY_"+toString(j )+"_VAL" );
612	PORT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_NUM_REG" ,
613	dest,"out_BYPASS_MEMORY_"+toString(j )+"_NUM_REG" );
614	PORT_MAP(_component ,src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_DATA" ,
615	dest,"out_BYPASS_MEMORY_"+toString(j )+"_DATA" );
616
617	// port map to the "load_store_unit" component
618	#ifdef POSITION
619	_component->interface_map (dest,"bypass_memory_"+toString(j),
620	src ,"bypass_memory_"+toString(it_bypass_memory));
621	#endif
622
623	if (_param->_have_port_ooo_engine_id)
624	PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_OOO_ENGINE_ID",
625	src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_OOO_ENGINE_ID");
626	PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_VAL" ,
627	src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_VAL" );
628	PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_NUM_REG" ,
629	src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_NUM_REG" );
630	PORT_MAP(_component ,dest,"out_BYPASS_MEMORY_"+toString(j )+"_DATA" ,
631	src , "in_BYPASS_MEMORY_"+toString(it_bypass_memory)+"_DATA" );
632
633	it_bypass_memory ++;
634	}
635	}
636	}
637	}
638
639	// ===================================================================
640	// =====[ EXECUTE_UNIT ]==============================================
641	// ===================================================================
642	for (uint32_t i=0; i<_param->_nb_execute_unit; i++)
643	{
644	uint32_t x=_param->_translate_num_execute_unit[i];
645
646	if (_param->_is_load_store_unit[i] == false)
647	{
648	// ===================================================================
649	// =====[ FUNCTIONNAL_UNIT ]==========================================
650	// ===================================================================
651
652	src = _name+"_functionnal_unit_"+toString(x);
653	std::cout << "Instance : " << src << std::endl;
654
655	{
656	dest = _name;
657	#ifdef POSITION
658	_component->interface_map (src ,"",
659	dest,"");
660	#endif
661	PORT_MAP(_component ,src , "in_CLOCK" ,dest, "in_CLOCK");
662	PORT_MAP(_component ,src , "in_NRESET",dest, "in_NRESET");
663	}
664
665	// ~~~~~[ Interface "execute_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
666	{
667	dest = _name+"_read_unit_to_execution_unit";
668
669	#ifdef POSITION
670	_component->interface_map (src ,"execute_in",
671	dest,"execute_unit_in_"+toString(i));
672	#endif
673
674	PORT_MAP(_component ,src , "in_EXECUTE_IN_VAL" ,
675	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" );
676	PORT_MAP(_component ,src ,"out_EXECUTE_IN_ACK" ,
677	dest, "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" );
678	if (_param->_have_port_context_id)
679	PORT_MAP(_component ,src , "in_EXECUTE_IN_CONTEXT_ID" ,
680	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" );
681	if (_param->_have_port_front_end_id)
682	PORT_MAP(_component ,src , "in_EXECUTE_IN_FRONT_END_ID" ,
683	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" );
684	if (_param->_have_port_ooo_engine_id)
685	PORT_MAP(_component ,src , "in_EXECUTE_IN_OOO_ENGINE_ID" ,
686	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" );
687	if (_param->_have_port_packet_id)
688	PORT_MAP(_component ,src , "in_EXECUTE_IN_PACKET_ID" ,
689	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" );
690	PORT_MAP(_component ,src , "in_EXECUTE_IN_OPERATION" ,
691	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" );
692	PORT_MAP(_component ,src , "in_EXECUTE_IN_TYPE" ,
693	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" );
694	PORT_MAP(_component ,src , "in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE",
695	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE");
696	if (_param->_have_port_load_queue_ptr)
697	PORT_MAP(_component ,src , "in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE" ,
698	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" );
699	PORT_MAP(_component ,src , "in_EXECUTE_IN_HAS_IMMEDIAT" ,
700	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" );
701	PORT_MAP(_component ,src , "in_EXECUTE_IN_IMMEDIAT" ,
702	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" );
703	PORT_MAP(_component ,src , "in_EXECUTE_IN_DATA_RA" ,
704	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" );
705	PORT_MAP(_component ,src , "in_EXECUTE_IN_DATA_RB" ,
706	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" );
707	PORT_MAP(_component ,src , "in_EXECUTE_IN_DATA_RC" ,
708	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" );
709	PORT_MAP(_component ,src , "in_EXECUTE_IN_WRITE_RD" ,
710	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" );
711	PORT_MAP(_component ,src , "in_EXECUTE_IN_NUM_REG_RD" ,
712	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" );
713	PORT_MAP(_component ,src , "in_EXECUTE_IN_WRITE_RE" ,
714	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" );
715	PORT_MAP(_component ,src , "in_EXECUTE_IN_NUM_REG_RE" ,
716	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" );
717	}
718
719	// ~~~~~[ Interface "execute_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
720	{
721	dest = _name+"_execution_unit_to_write_unit";
722
723	#ifdef POSITION
724	_component->interface_map (src ,"execute_out",
725	dest,"execute_unit_out_"+toString(i));
726	#endif
727
728	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_VAL" ,
729	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" );
730	PORT_MAP(_component ,src , "in_EXECUTE_OUT_ACK" ,
731	dest,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" );
732	if (_param->_have_port_context_id)
733	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_CONTEXT_ID" ,
734	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" );
735	if (_param->_have_port_front_end_id)
736	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_FRONT_END_ID" ,
737	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" );
738	if (_param->_have_port_ooo_engine_id)
739	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_OOO_ENGINE_ID",
740	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID");
741	if (_param->_have_port_packet_id)
742	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_PACKET_ID" ,
743	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" );
744	// PORT_MAP(_component ,src ,"out_EXECUTE_OUT_OPERATION" ,
745	// dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" );
746	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_TYPE" ,
747	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" );
748	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_WRITE_RD" ,
749	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" );
750	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_NUM_REG_RD" ,
751	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" );
752	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_DATA_RD" ,
753	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" );
754	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_WRITE_RE" ,
755	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" );
756	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_NUM_REG_RE" ,
757	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" );
758	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_DATA_RE" ,
759	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" );
760	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_EXCEPTION" ,
761	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" );
762	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_NO_SEQUENCE" ,
763	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" );
764	PORT_MAP(_component ,src ,"out_EXECUTE_OUT_ADDRESS" ,
765	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" );
766	}
767	}
768	else
769	{
770	// ===================================================================
771	// =====[ LOAD_STORE_UNIT ]===========================================
772	// ===================================================================
773
774	src = _name+"_load_store_unit_"+toString(x);
775	std::cout << "Instance : " << src << std::endl;
776
777	// ~~~~~[ Interface "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
778	{
779	dest = _name;
780	#ifdef POSITION
781	_component->interface_map (src ,"",
782	dest,"");
783	#endif
784	PORT_MAP(_component ,src , "in_CLOCK" ,dest, "in_CLOCK");
785	PORT_MAP(_component ,src , "in_NRESET",dest, "in_NRESET");
786	}
787
788	// ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
789	{
790	dest = _name+"_read_unit_to_execution_unit";
791
792	#ifdef POSITION
793	_component->interface_map (src ,"memory_in",
794	dest,"execute_unit_in_"+toString(i));
795	#endif
796
797	PORT_MAP(_component ,src , "in_MEMORY_IN_VAL" ,
798	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" );
799	PORT_MAP(_component ,src ,"out_MEMORY_IN_ACK" ,
800	dest, "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" );
801	if (_param->_have_port_context_id)
802	PORT_MAP(_component ,src , "in_MEMORY_IN_CONTEXT_ID" ,
803	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" );
804	if (_param->_have_port_front_end_id)
805	PORT_MAP(_component ,src , "in_MEMORY_IN_FRONT_END_ID" ,
806	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" );
807	if (_param->_have_port_ooo_engine_id)
808	PORT_MAP(_component ,src , "in_MEMORY_IN_OOO_ENGINE_ID" ,
809	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" );
810	if (_param->_have_port_packet_id)
811	PORT_MAP(_component ,src , "in_MEMORY_IN_PACKET_ID" ,
812	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" );
813	PORT_MAP(_component ,src , "in_MEMORY_IN_OPERATION" ,
814	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" );
815	PORT_MAP(_component ,src , "in_MEMORY_IN_TYPE" ,
816	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" );
817	PORT_MAP(_component ,src , "in_MEMORY_IN_STORE_QUEUE_PTR_WRITE",
818	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE");
819	if (_param->_have_port_load_queue_ptr)
820	PORT_MAP(_component ,src , "in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE" ,
821	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" );
822	PORT_MAP(_component ,src , "in_MEMORY_IN_HAS_IMMEDIAT" ,
823	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" );
824	PORT_MAP(_component ,src , "in_MEMORY_IN_IMMEDIAT" ,
825	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" );
826	PORT_MAP(_component ,src , "in_MEMORY_IN_DATA_RA" ,
827	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" );
828	PORT_MAP(_component ,src , "in_MEMORY_IN_DATA_RB" ,
829	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" );
830	PORT_MAP(_component ,src , "in_MEMORY_IN_DATA_RC" ,
831	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" );
832	PORT_MAP(_component ,src , "in_MEMORY_IN_WRITE_RD" ,
833	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" );
834	PORT_MAP(_component ,src , "in_MEMORY_IN_NUM_REG_RD" ,
835	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" );
836	PORT_MAP(_component ,src , "in_MEMORY_IN_WRITE_RE" ,
837	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" );
838	PORT_MAP(_component ,src , "in_MEMORY_IN_NUM_REG_RE" ,
839	dest,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" );
840	}
841
842	// ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
843	{
844	dest = _name+"_execution_unit_to_write_unit";
845
846	#ifdef POSITION
847	_component->interface_map (src ,"memory_out",
848	dest,"execute_unit_out_"+toString(i));
849	#endif
850
851	PORT_MAP(_component ,src ,"out_MEMORY_OUT_VAL" ,
852	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" );
853	PORT_MAP(_component ,src , "in_MEMORY_OUT_ACK" ,
854	dest,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" );
855	if (_param->_have_port_context_id)
856	PORT_MAP(_component ,src ,"out_MEMORY_OUT_CONTEXT_ID" ,
857	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" );
858	if (_param->_have_port_front_end_id)
859	PORT_MAP(_component ,src ,"out_MEMORY_OUT_FRONT_END_ID" ,
860	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" );
861	if (_param->_have_port_ooo_engine_id)
862	PORT_MAP(_component ,src ,"out_MEMORY_OUT_OOO_ENGINE_ID",
863	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID");
864	if (_param->_have_port_packet_id)
865	PORT_MAP(_component ,src ,"out_MEMORY_OUT_PACKET_ID" ,
866	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" );
867	// PORT_MAP(_component ,src ,"out_MEMORY_OUT_OPERATION" ,
868	// dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" );
869	PORT_MAP(_component ,src ,"out_MEMORY_OUT_TYPE" ,
870	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" );
871	PORT_MAP(_component ,src ,"out_MEMORY_OUT_WRITE_RD" ,
872	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" );
873	PORT_MAP(_component ,src ,"out_MEMORY_OUT_NUM_REG_RD" ,
874	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" );
875	PORT_MAP(_component ,src ,"out_MEMORY_OUT_DATA_RD" ,
876	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" );
877	PORT_MAP(_component ,src ,"out_MEMORY_OUT_WRITE_RE" ,
878	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" );
879	PORT_MAP(_component ,src ,"out_MEMORY_OUT_NUM_REG_RE" ,
880	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" );
881	PORT_MAP(_component ,src ,"out_MEMORY_OUT_DATA_RE" ,
882	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" );
883	PORT_MAP(_component ,src ,"out_MEMORY_OUT_EXCEPTION" ,
884	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" );
885	PORT_MAP(_component ,src ,"out_MEMORY_OUT_NO_SEQUENCE" ,
886	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" );
887	PORT_MAP(_component ,src ,"out_MEMORY_OUT_ADDRESS" ,
888	dest, "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" );
889	}
890
891	// ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
892	{
893	dest = _name;
894
895	#ifdef POSITION
896	_component->interface_map (src ,"dcache_req",
897	dest,"dcache_req_"+toString(i));
898	#endif
899	PORT_MAP(_component ,src ,"out_DCACHE_REQ_VAL" ,dest,"out_DCACHE_REQ_"+toString(i)+"_VAL" );
900	PORT_MAP(_component ,src , "in_DCACHE_REQ_ACK" ,dest, "in_DCACHE_REQ_"+toString(i)+"_ACK" );
901	if (_param->_have_port_dcache_context_id)
902	PORT_MAP(_component ,src ,"out_DCACHE_REQ_CONTEXT_ID",dest,"out_DCACHE_REQ_"+toString(i)+"_CONTEXT_ID");
903	PORT_MAP(_component ,src ,"out_DCACHE_REQ_PACKET_ID" ,dest,"out_DCACHE_REQ_"+toString(i)+"_PACKET_ID" );
904	PORT_MAP(_component ,src ,"out_DCACHE_REQ_ADDRESS" ,dest,"out_DCACHE_REQ_"+toString(i)+"_ADDRESS" );
905	PORT_MAP(_component ,src ,"out_DCACHE_REQ_TYPE" ,dest,"out_DCACHE_REQ_"+toString(i)+"_TYPE" );
906	PORT_MAP(_component ,src ,"out_DCACHE_REQ_WDATA" ,dest,"out_DCACHE_REQ_"+toString(i)+"_WDATA" );
907	}
908
909	// ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
910	{
911	dest = _name;
912
913	#ifdef POSITION
914	_component->interface_map (src ,"dcache_rsp",
915	dest,"dcache_rsp_"+toString(i));
916	#endif
917	PORT_MAP(_component ,src , "in_DCACHE_RSP_VAL" ,dest, "in_DCACHE_RSP_"+toString(i)+"_VAL" );
918	PORT_MAP(_component ,src ,"out_DCACHE_RSP_ACK" ,dest,"out_DCACHE_RSP_"+toString(i)+"_ACK" );
919	if (_param->_have_port_dcache_context_id)
920	PORT_MAP(_component ,src , "in_DCACHE_RSP_CONTEXT_ID",dest, "in_DCACHE_RSP_"+toString(i)+"_CONTEXT_ID");
921	PORT_MAP(_component ,src , "in_DCACHE_RSP_PACKET_ID" ,dest, "in_DCACHE_RSP_"+toString(i)+"_PACKET_ID" );
922	PORT_MAP(_component ,src , "in_DCACHE_RSP_RDATA" ,dest, "in_DCACHE_RSP_"+toString(i)+"_RDATA" );
923	PORT_MAP(_component ,src , "in_DCACHE_RSP_ERROR" ,dest, "in_DCACHE_RSP_"+toString(i)+"_ERROR" );
924	}
925
926	// ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
927	{
928	// Port map with "read_unit" is ok!
929	}
930	}
931	}
932
933	// ===================================================================
934	// =====[ WRITE_UNIT ]================================================
935	// ===================================================================
936	for (uint32_t i=0; i<_param->_nb_write_unit; i++)
937	{
938	src = _name+"_write_unit_"+toString(i);
939	std::cout << "Instance : " << src << std::endl;
940
941	{
942	dest = _name;
943	#ifdef POSITION
944	_component->interface_map (src ,"",
945	dest,"");
946	#endif
947	PORT_MAP(_component ,src , "in_CLOCK" ,dest, "in_CLOCK");
948	PORT_MAP(_component ,src , "in_NRESET",dest, "in_NRESET");
949	}
950
951	// -----[ Interface "write_unit_in" ]---------------------------------
952	{
953	dest = _name+"_execution_unit_to_write_unit";
954	#ifdef POSITION
955	_component->interface_map (src ,"write_unit_in",
956	dest,"execute_unit_in_"+toString(i));
957	#endif
958
959	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_VAL" ,
960	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_VAL" );
961	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_ACK" ,
962	dest, "in_WRITE_UNIT_IN_"+toString(i)+"_ACK" );
963	if (_param->_have_port_context_id)
964	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_CONTEXT_ID" ,
965	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" );
966	if (_param->_have_port_front_end_id)
967	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_FRONT_END_ID" ,
968	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" );
969	if (_param->_have_port_ooo_engine_id)
970	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_OOO_ENGINE_ID",
971	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID");
972	if (_param->_have_port_packet_id)
973	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_PACKET_ID" ,
974	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_PACKET_ID" );
975	// PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_OPERATION" ,
976	// dest,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" );
977	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_TYPE" ,
978	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" );
979	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_WRITE_RD" ,
980	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" );
981	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_NUM_REG_RD" ,
982	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" );
983	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_DATA_RD" ,
984	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RD" );
985	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_WRITE_RE" ,
986	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RE" );
987	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_NUM_REG_RE" ,
988	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" );
989	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_DATA_RE" ,
990	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RE" );
991	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_EXCEPTION" ,
992	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_EXCEPTION" );
993	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_NO_SEQUENCE" ,
994	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_NO_SEQUENCE" );
995	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_ADDRESS" ,
996	dest,"out_WRITE_UNIT_IN_"+toString(i)+"_ADDRESS" );
997	}
998
999	// -----[ Interface "write_unit_out" ]--------------------------------
1000	{
1001	dest = _name;
1002	#ifdef POSITION
1003	_component->interface_map (src ,"write_unit_out",
1004	dest,"execute_loop_out_"+toString(i));
1005	#endif
1006
1007	PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_VAL" ,
1008	dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_VAL" );
1009	PORT_MAP(_component ,src , "in_WRITE_UNIT_OUT_ACK" ,
1010	dest, "in_EXECUTE_LOOP_OUT_"+toString(i)+"_ACK" );
1011	if (_param->_have_port_context_id)
1012	PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_CONTEXT_ID" ,
1013	dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_CONTEXT_ID" );
1014	if (_param->_have_port_front_end_id)
1015	PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_FRONT_END_ID" ,
1016	dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_FRONT_END_ID" );
1017	if (_param->_have_port_ooo_engine_id)
1018	PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_OOO_ENGINE_ID",
1019	dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_OOO_ENGINE_ID");
1020	if (_param->_have_port_packet_id)
1021	PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_PACKET_ID" ,
1022	dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_PACKET_ID" );
1023	// PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_OPERATION" ,
1024	// dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_OPERATION" );
1025	// PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_TYPE" ,
1026	// dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_TYPE" );
1027	PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_FLAGS" ,
1028	dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_FLAGS" );
1029	PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_EXCEPTION" ,
1030	dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_EXCEPTION" );
1031	PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_NO_SEQUENCE" ,
1032	dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_NO_SEQUENCE" );
1033	PORT_MAP(_component ,src ,"out_WRITE_UNIT_OUT_ADDRESS" ,
1034	dest,"out_EXECUTE_LOOP_OUT_"+toString(i)+"_ADDRESS" );
1035	}
1036	// -----[ Interface "gpr_write" ]-------------------------------------
1037	{
1038	// Port map with "read_unit" is ok!
1039
1040	dest = _name+"_register_unit";
1041	#ifdef POSITION
1042	_component->interface_map (src ,"gpr_write",
1043	dest,"gpr_write_"+toString(i));
1044	#endif
1045
1046	PORT_MAP(_component ,src ,"out_GPR_WRITE_0_VAL" ,
1047	dest, "in_GPR_WRITE_"+toString(i)+"_VAL" );
1048	PORT_MAP(_component ,src , "in_GPR_WRITE_0_ACK" ,
1049	dest,"out_GPR_WRITE_"+toString(i)+"_ACK" );
1050	if (_param->_have_port_context_id)
1051	PORT_MAP(_component ,src ,"out_GPR_WRITE_0_OOO_ENGINE_ID",
1052	dest, "in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
1053	PORT_MAP(_component ,src ,"out_GPR_WRITE_0_NUM_REG" ,
1054	dest, "in_GPR_WRITE_"+toString(i)+"_NUM_REG" );
1055	PORT_MAP(_component ,src ,"out_GPR_WRITE_0_DATA" ,
1056	dest, "in_GPR_WRITE_"+toString(i)+"_DATA" );
1057	}
1058
1059	// -----[ Interface "spr_write" ]-------------------------------------
1060	{
1061	// Port map with "read_unit" is ok!
1062
1063	dest = _name+"_register_unit";
1064	#ifdef POSITION
1065	_component->interface_map (src ,"spr_write",
1066	dest,"spr_write_"+toString(i));
1067	#endif
1068
1069	PORT_MAP(_component ,src ,"out_SPR_WRITE_0_VAL" ,
1070	dest, "in_SPR_WRITE_"+toString(i)+"_VAL" );
1071	PORT_MAP(_component ,src , "in_SPR_WRITE_0_ACK" ,
1072	dest,"out_SPR_WRITE_"+toString(i)+"_ACK" );
1073	if (_param->_have_port_context_id)
1074	PORT_MAP(_component ,src ,"out_SPR_WRITE_0_OOO_ENGINE_ID",
1075	dest, "in_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID");
1076	PORT_MAP(_component ,src ,"out_SPR_WRITE_0_NUM_REG" ,
1077	dest, "in_SPR_WRITE_"+toString(i)+"_NUM_REG" );
1078	PORT_MAP(_component ,src ,"out_SPR_WRITE_0_DATA" ,
1079	dest, "in_SPR_WRITE_"+toString(i)+"_DATA" );
1080	}
1081
1082	// -----[ Interface "bypass_write" ]----------------------------------
1083	{
1084	// Port map with "read_unit" is ok!
1085	}
1086	}
1087
1088	// ===================================================================
1089	// =====[ REGISTER_UNIT ]=============================================
1090	// ===================================================================
1091	{
1092	src = _name+"_register_unit";
1093	std::cout << "Instance : " << src << std::endl;
1094
1095	{
1096	dest = _name;
1097	#ifdef POSITION
1098	_component->interface_map (src ,"",
1099	dest,"");
1100	#endif
1101	PORT_MAP(_component ,src , "in_CLOCK" ,dest, "in_CLOCK");
1102	PORT_MAP(_component ,src , "in_NRESET",dest, "in_NRESET");
1103	}
1104
1105	// ~~~~~[ Interface "gpr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1106	for (uint32_t i=0; i<_param->_nb_read_unit; i++)
1107	{
1108	dest = _name+"_read_unit_"+toString(i);
1109	#ifdef POSITION
1110	_component->interface_map (src ,"gpr_read_"+toString(2*i )
1111	dest,"gpr_read_0");
1112	_component->interface_map (src ,"gpr_read_"+toString(2*i+1)
1113	dest,"gpr_read_1");
1114	#endif
1115
1116	PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i )+"_VAL" ,dest,"out_GPR_READ_0_VAL" );
1117	PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i )+"_ACK" ,dest, "in_GPR_READ_0_ACK" );
1118	if (_param->_have_port_context_id)
1119	PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i )+"_OOO_ENGINE_ID",dest,"out_GPR_READ_0_OOO_ENGINE_ID");
1120	PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i )+"_NUM_REG" ,dest,"out_GPR_READ_0_NUM_REG" );
1121	PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i )+"_DATA" ,dest, "in_GPR_READ_0_DATA" );
1122	PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i )+"_DATA_VAL" ,dest, "in_GPR_READ_0_DATA_VAL" );
1123
1124	PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i+1)+"_VAL" ,dest,"out_GPR_READ_1_VAL" );
1125	PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i+1)+"_ACK" ,dest, "in_GPR_READ_1_ACK" );
1126	if (_param->_have_port_context_id)
1127	PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i+1)+"_OOO_ENGINE_ID",dest,"out_GPR_READ_1_OOO_ENGINE_ID");
1128	PORT_MAP(_component ,src , "in_GPR_READ_"+toString(2*i+1)+"_NUM_REG" ,dest,"out_GPR_READ_1_NUM_REG" );
1129	PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i+1)+"_DATA" ,dest, "in_GPR_READ_1_DATA" );
1130	PORT_MAP(_component ,src ,"out_GPR_READ_"+toString(2*i+1)+"_DATA_VAL" ,dest, "in_GPR_READ_1_DATA_VAL" );
1131	}
1132
1133	// ~~~~~[ Interface "gpr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1134	for (uint32_t i=0; i<_param->_nb_write_unit; i++)
1135	{
1136	dest = _name+"_write_unit_"+toString(i);
1137	#ifdef POSITION
1138	_component->interface_map (src ,"gpr_write_"+toString(i)
1139	dest,"gpr_write_0");
1140	#endif
1141
1142	PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_VAL" ,dest,"out_GPR_WRITE_0_VAL" );
1143	PORT_MAP(_component ,src ,"out_GPR_WRITE_"+toString(i)+"_ACK" ,dest, "in_GPR_WRITE_0_ACK" );
1144	if (_param->_have_port_context_id)
1145	PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_GPR_WRITE_0_OOO_ENGINE_ID");
1146	PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_NUM_REG" ,dest,"out_GPR_WRITE_0_NUM_REG" );
1147	PORT_MAP(_component ,src , "in_GPR_WRITE_"+toString(i)+"_DATA" ,dest,"out_GPR_WRITE_0_DATA" );
1148	}
1149
1150	// ~~~~~[ Interface "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1151	for (uint32_t i=0; i<_param->_nb_read_unit; i++)
1152	{
1153	dest = _name+"_read_unit_"+toString(i);
1154	#ifdef POSITION
1155	_component->interface_map (src ,"spr_read_"+toString(i),
1156	dest,"spr_read_0");
1157	#endif
1158
1159	PORT_MAP(_component ,src , "in_SPR_READ_"+toString(i)+"_VAL" ,dest,"out_SPR_READ_0_VAL" );
1160	PORT_MAP(_component ,src ,"out_SPR_READ_"+toString(i)+"_ACK" ,dest, "in_SPR_READ_0_ACK" );
1161	if (_param->_have_port_context_id)
1162	PORT_MAP(_component ,src , "in_SPR_READ_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_SPR_READ_0_OOO_ENGINE_ID");
1163	PORT_MAP(_component ,src , "in_SPR_READ_"+toString(i)+"_NUM_REG" ,dest,"out_SPR_READ_0_NUM_REG" );
1164	PORT_MAP(_component ,src ,"out_SPR_READ_"+toString(i)+"_DATA" ,dest, "in_SPR_READ_0_DATA" );
1165	PORT_MAP(_component ,src ,"out_SPR_READ_"+toString(i)+"_DATA_VAL" ,dest, "in_SPR_READ_0_DATA_VAL" );
1166	}
1167
1168	// ~~~~~[ Interface "spr_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1169	for (uint32_t i=0; i<_param->_nb_write_unit; i++)
1170	{
1171	dest = _name+"_write_unit_"+toString(i);
1172	#ifdef POSITION
1173	_component->interface_map (src ,"spr_write_"+toString(i)
1174	dest,"spr_write_0");
1175	#endif
1176
1177	PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_VAL" ,dest,"out_SPR_WRITE_0_VAL" );
1178	PORT_MAP(_component ,src ,"out_SPR_WRITE_"+toString(i)+"_ACK" ,dest, "in_SPR_WRITE_0_ACK" );
1179	if (_param->_have_port_context_id)
1180	PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_OOO_ENGINE_ID",dest,"out_SPR_WRITE_0_OOO_ENGINE_ID");
1181	PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_NUM_REG" ,dest,"out_SPR_WRITE_0_NUM_REG" );
1182	PORT_MAP(_component ,src , "in_SPR_WRITE_"+toString(i)+"_DATA" ,dest,"out_SPR_WRITE_0_DATA" );
1183	}
1184
1185	// ~~~~~[ Interface "insert_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1186	for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
1187	{
1188	uint32_t x=_param->_nb_inst_insert_rob [i];
1189
1190	for (uint32_t j=0; j<x; j++)
1191	{
1192	dest = _name;
1193	#ifdef POSITION
1194	_component->interface_map (src ,"insert_rob_"+toString(i)+"_"+toString(j),
1195	dest,"insert_rob_"+toString(i)+"_"+toString(j));
1196	#endif
1197
1198	PORT_MAP(_component ,src , "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_VAL" ,
1199	dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_VAL" );
1200	PORT_MAP(_component ,src ,"out_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_ACK" ,
1201	dest,"out_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_ACK" );
1202	PORT_MAP(_component ,src , "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_USE" ,
1203	dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_USE" );
1204	PORT_MAP(_component ,src , "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_NUM_REG",
1205	dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RD_NUM_REG");
1206	PORT_MAP(_component ,src , "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_USE" ,
1207	dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_USE" );
1208	PORT_MAP(_component ,src , "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_NUM_REG",
1209	dest, "in_INSERT_ROB_"+toString(i)+"_"+toString(j)+"_RE_NUM_REG");
1210	}
1211	}
1212
1213	// ~~~~~[ Interface "retire_rob" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1214	for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
1215	{
1216	uint32_t x=_param->_nb_inst_retire_rob [i];
1217
1218	for (uint32_t j=0; j<x; j++)
1219	{
1220	dest = _name;
1221	#ifdef POSITION
1222	_component->interface_map (src ,"retire_rob_"+toString(i)+"_"+toString(j),
1223	dest,"retire_rob_"+toString(i)+"_"+toString(j));
1224	#endif
1225
1226	PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL" ,
1227	dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_VAL" );
1228	PORT_MAP(_component ,src ,"out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK" ,
1229	dest,"out_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_ACK" );
1230	PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE" ,
1231	dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_USE" );
1232	PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_NUM_REG",
1233	dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_OLD_NUM_REG");
1234	PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE" ,
1235	dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_USE" );
1236	PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_NUM_REG",
1237	dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RD_NEW_NUM_REG");
1238	PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE" ,
1239	dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_USE" );
1240	PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_NUM_REG",
1241	dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_OLD_NUM_REG");
1242	PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE" ,
1243	dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_USE" );
1244	PORT_MAP(_component ,src , "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_NUM_REG",
1245	dest, "in_RETIRE_ROB_"+toString(i)+"_"+toString(j)+"_RE_NEW_NUM_REG");
1246	}
1247	}
1248	}
1249
1250	// ===================================================================
1251	// =====[ READ_UNIT_TO_EXECUTION_UNIT ]===============================
1252	// ===================================================================
1253	{
1254	src = _name+"_read_unit_to_execution_unit";
1255	std::cout << "Instance : " << src << std::endl;
1256
1257	{
1258	dest = _name;
1259	#ifdef POSITION
1260	_component->interface_map (src ,"",
1261	dest,"");
1262	#endif
1263	PORT_MAP(_component ,src , "in_CLOCK" ,dest, "in_CLOCK");
1264	PORT_MAP(_component ,src , "in_NRESET",dest, "in_NRESET");
1265	}
1266
1267	// ~~~~~[ Interface "read_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1268	uint32_t it_read_unit_out =0;
1269	for (uint32_t i=0; i < _param->_nb_read_unit; i++)
1270	for (uint32_t j=0; j < _param->_nb_inst_retire[i]; j++)
1271	{
1272	dest = _name+"_read_unit_"+toString(i);
1273
1274	#ifdef POSITION
1275	_component->interface_map (src ,"read_unit_"+toString(it_read_unit_out),
1276	dest,"read_unit_"+toString(j));
1277	#endif
1278
1279	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_VAL" ,
1280	dest,"out_READ_UNIT_OUT_"+toString(j )+"_VAL" );
1281	PORT_MAP(_component ,src ,"out_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_ACK" ,
1282	dest, "in_READ_UNIT_OUT_"+toString(j )+"_ACK" );
1283	if (_param->_have_port_context_id)
1284	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_CONTEXT_ID" ,
1285	dest,"out_READ_UNIT_OUT_"+toString(j )+"_CONTEXT_ID" );
1286	if (_param->_have_port_front_end_id)
1287	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_FRONT_END_ID" ,
1288	dest,"out_READ_UNIT_OUT_"+toString(j )+"_FRONT_END_ID" );
1289	if (_param->_have_port_ooo_engine_id)
1290	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OOO_ENGINE_ID" ,
1291	dest,"out_READ_UNIT_OUT_"+toString(j )+"_OOO_ENGINE_ID" );
1292	if (_param->_have_port_packet_id)
1293	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_PACKET_ID" ,
1294	dest,"out_READ_UNIT_OUT_"+toString(j )+"_PACKET_ID" );
1295	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_OPERATION" ,
1296	dest,"out_READ_UNIT_OUT_"+toString(j )+"_OPERATION" );
1297	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_TYPE" ,
1298	dest,"out_READ_UNIT_OUT_"+toString(j )+"_TYPE" );
1299	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_STORE_QUEUE_PTR_WRITE",
1300	dest,"out_READ_UNIT_OUT_"+toString(j )+"_STORE_QUEUE_PTR_WRITE");
1301	if (_param->_have_port_load_queue_ptr)
1302	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_LOAD_QUEUE_PTR_WRITE" ,
1303	dest,"out_READ_UNIT_OUT_"+toString(j )+"_LOAD_QUEUE_PTR_WRITE" );
1304	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_HAS_IMMEDIAT" ,
1305	dest,"out_READ_UNIT_OUT_"+toString(j )+"_HAS_IMMEDIAT" );
1306	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_IMMEDIAT" ,
1307	dest,"out_READ_UNIT_OUT_"+toString(j )+"_IMMEDIAT" );
1308	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RA" ,
1309	dest,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RA" );
1310	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RB" ,
1311	dest,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RB" );
1312	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_DATA_RC" ,
1313	dest,"out_READ_UNIT_OUT_"+toString(j )+"_DATA_RC" );
1314	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RD" ,
1315	dest,"out_READ_UNIT_OUT_"+toString(j )+"_WRITE_RD" );
1316	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RD" ,
1317	dest,"out_READ_UNIT_OUT_"+toString(j )+"_NUM_REG_RD" );
1318	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_WRITE_RE" ,
1319	dest,"out_READ_UNIT_OUT_"+toString(j )+"_WRITE_RE" );
1320	PORT_MAP(_component ,src , "in_READ_UNIT_OUT_"+toString(it_read_unit_out)+"_NUM_REG_RE" ,
1321	dest,"out_READ_UNIT_OUT_"+toString(j )+"_NUM_REG_RE" );
1322
1323	it_read_unit_out ++;
1324	}
1325
1326	// ~~~~~[ Interface "execute_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1327	for (uint32_t i=0; i<_param->_nb_execute_unit; i++)
1328	{
1329	uint32_t x=_param->_translate_num_execute_unit[i];
1330
1331	if (_param->_is_load_store_unit[i] == false)
1332	{
1333	dest = _name+"_functionnal_unit_"+toString(x);
1334
1335	#ifdef POSITION
1336	_component->interface_map (src ,"execute_unit_in_"+toString(i),
1337	dest,"execute_in");
1338	#endif
1339
1340	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" ,
1341	dest, "in_EXECUTE_IN_VAL" );
1342	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" ,
1343	dest,"out_EXECUTE_IN_ACK" );
1344	if (_param->_have_port_context_id)
1345	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" ,
1346	dest, "in_EXECUTE_IN_CONTEXT_ID" );
1347	if (_param->_have_port_front_end_id)
1348	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" ,
1349	dest, "in_EXECUTE_IN_FRONT_END_ID" );
1350	if (_param->_have_port_ooo_engine_id)
1351	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" ,
1352	dest, "in_EXECUTE_IN_OOO_ENGINE_ID" );
1353	if (_param->_have_port_packet_id)
1354	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" ,
1355	dest, "in_EXECUTE_IN_PACKET_ID" );
1356	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" ,
1357	dest, "in_EXECUTE_IN_OPERATION" );
1358	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" ,
1359	dest, "in_EXECUTE_IN_TYPE" );
1360	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE",
1361	dest, "in_EXECUTE_IN_STORE_QUEUE_PTR_WRITE");
1362	if (_param->_have_port_load_queue_ptr)
1363	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ,
1364	dest, "in_EXECUTE_IN_LOAD_QUEUE_PTR_WRITE" );
1365	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" ,
1366	dest, "in_EXECUTE_IN_HAS_IMMEDIAT" );
1367	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" ,
1368	dest, "in_EXECUTE_IN_IMMEDIAT" );
1369	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" ,
1370	dest, "in_EXECUTE_IN_DATA_RA" );
1371	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" ,
1372	dest, "in_EXECUTE_IN_DATA_RB" );
1373	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" ,
1374	dest, "in_EXECUTE_IN_DATA_RC" );
1375	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" ,
1376	dest, "in_EXECUTE_IN_WRITE_RD" );
1377	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" ,
1378	dest, "in_EXECUTE_IN_NUM_REG_RD" );
1379	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" ,
1380	dest, "in_EXECUTE_IN_WRITE_RE" );
1381	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" ,
1382	dest, "in_EXECUTE_IN_NUM_REG_RE" );
1383	}
1384	else
1385	{
1386	dest = _name+"_load_store_unit_"+toString(x);
1387
1388	#ifdef POSITION
1389	_component->interface_map (src ,"execute_unit_in_"+toString(i),
1390	dest,"memory_in");
1391	#endif
1392
1393	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_VAL" ,
1394	dest, "in_MEMORY_IN_VAL" );
1395	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_IN_"+toString(i)+"_ACK" ,
1396	dest,"out_MEMORY_IN_ACK" );
1397	if (_param->_have_port_context_id)
1398	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" ,
1399	dest, "in_MEMORY_IN_CONTEXT_ID" );
1400	if (_param->_have_port_front_end_id)
1401	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" ,
1402	dest, "in_MEMORY_IN_FRONT_END_ID" );
1403	if (_param->_have_port_ooo_engine_id)
1404	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID" ,
1405	dest, "in_MEMORY_IN_OOO_ENGINE_ID" );
1406	if (_param->_have_port_packet_id)
1407	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_PACKET_ID" ,
1408	dest, "in_MEMORY_IN_PACKET_ID" );
1409	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_OPERATION" ,
1410	dest, "in_MEMORY_IN_OPERATION" );
1411	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_TYPE" ,
1412	dest, "in_MEMORY_IN_TYPE" );
1413	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_STORE_QUEUE_PTR_WRITE",
1414	dest, "in_MEMORY_IN_STORE_QUEUE_PTR_WRITE");
1415	if (_param->_have_port_load_queue_ptr)
1416	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_LOAD_QUEUE_PTR_WRITE" ,
1417	dest, "in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE" );
1418	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_HAS_IMMEDIAT" ,
1419	dest, "in_MEMORY_IN_HAS_IMMEDIAT" );
1420	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_IMMEDIAT" ,
1421	dest, "in_MEMORY_IN_IMMEDIAT" );
1422	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RA" ,
1423	dest, "in_MEMORY_IN_DATA_RA" );
1424	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RB" ,
1425	dest, "in_MEMORY_IN_DATA_RB" );
1426	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_DATA_RC" ,
1427	dest, "in_MEMORY_IN_DATA_RC" );
1428	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RD" ,
1429	dest, "in_MEMORY_IN_WRITE_RD" );
1430	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" ,
1431	dest, "in_MEMORY_IN_NUM_REG_RD" );
1432	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_WRITE_RE" ,
1433	dest, "in_MEMORY_IN_WRITE_RE" );
1434	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" ,
1435	dest, "in_MEMORY_IN_NUM_REG_RE" );
1436	}
1437	}
1438	}
1439
1440	// ===================================================================
1441	// =====[ EXECUTION_UNIT_TO_WRITE_UNIT ]==============================
1442	// ===================================================================
1443	{
1444	src = _name+"_execution_unit_to_write_unit";
1445	std::cout << "Instance : " << src << std::endl;
1446
1447	{
1448	dest = _name;
1449	#ifdef POSITION
1450	_component->interface_map (src ,"",
1451	dest,"");
1452	#endif
1453	PORT_MAP(_component ,src , "in_CLOCK" ,dest, "in_CLOCK");
1454	PORT_MAP(_component ,src , "in_NRESET",dest, "in_NRESET");
1455	}
1456
1457	// ~~~~~[ Interface "execute_unit_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1458	for (uint32_t i=0; i<_param->_nb_execute_unit; i++)
1459	{
1460	uint32_t x=_param->_translate_num_execute_unit[i];
1461
1462	if (_param->_is_load_store_unit[i] == false)
1463	{
1464	dest = _name+"_functionnal_unit_"+toString(x);
1465
1466	#ifdef POSITION
1467	_component->interface_map (src ,"execute_unit_out_"+toString(i),
1468	dest,"execute_out");
1469	#endif
1470	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" ,
1471	dest,"out_EXECUTE_OUT_VAL" );
1472	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" ,
1473	dest, "in_EXECUTE_OUT_ACK" );
1474	if (_param->_have_port_context_id)
1475	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" ,
1476	dest,"out_EXECUTE_OUT_CONTEXT_ID" );
1477	if (_param->_have_port_front_end_id)
1478	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" ,
1479	dest,"out_EXECUTE_OUT_FRONT_END_ID" );
1480	if (_param->_have_port_ooo_engine_id)
1481	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID",
1482	dest,"out_EXECUTE_OUT_OOO_ENGINE_ID");
1483	if (_param->_have_port_packet_id)
1484	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" ,
1485	dest,"out_EXECUTE_OUT_PACKET_ID" );
1486	// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" ,
1487	// dest,"out_EXECUTE_OUT_OPERATION" );
1488	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" ,
1489	dest,"out_EXECUTE_OUT_TYPE" );
1490	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" ,
1491	dest,"out_EXECUTE_OUT_WRITE_RD" );
1492	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" ,
1493	dest,"out_EXECUTE_OUT_NUM_REG_RD" );
1494	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" ,
1495	dest,"out_EXECUTE_OUT_DATA_RD" );
1496	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" ,
1497	dest,"out_EXECUTE_OUT_WRITE_RE" );
1498	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" ,
1499	dest,"out_EXECUTE_OUT_NUM_REG_RE" );
1500	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" ,
1501	dest,"out_EXECUTE_OUT_DATA_RE" );
1502	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" ,
1503	dest,"out_EXECUTE_OUT_EXCEPTION" );
1504	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" ,
1505	dest,"out_EXECUTE_OUT_NO_SEQUENCE" );
1506	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" ,
1507	dest,"out_EXECUTE_OUT_ADDRESS" );
1508	}
1509	else
1510	{
1511	dest = _name+"_load_store_unit_"+toString(x);
1512
1513	#ifdef POSITION
1514	_component->interface_map (src ,"execute_unit_out_"+toString(i),
1515	dest,"memory_out");
1516	#endif
1517	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_VAL" ,
1518	dest,"out_MEMORY_OUT_VAL" );
1519	PORT_MAP(_component ,src ,"out_EXECUTE_UNIT_OUT_"+toString(i)+"_ACK" ,
1520	dest, "in_MEMORY_OUT_ACK" );
1521	if (_param->_have_port_context_id)
1522	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_CONTEXT_ID" ,
1523	dest,"out_MEMORY_OUT_CONTEXT_ID" );
1524	if (_param->_have_port_front_end_id)
1525	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_FRONT_END_ID" ,
1526	dest,"out_MEMORY_OUT_FRONT_END_ID" );
1527	if (_param->_have_port_ooo_engine_id)
1528	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OOO_ENGINE_ID",
1529	dest,"out_MEMORY_OUT_OOO_ENGINE_ID");
1530	if (_param->_have_port_packet_id)
1531	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_PACKET_ID" ,
1532	dest,"out_MEMORY_OUT_PACKET_ID" );
1533	// PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_OPERATION" ,
1534	// dest,"out_MEMORY_OUT_OPERATION" );
1535	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_TYPE" ,
1536	dest,"out_MEMORY_OUT_TYPE" );
1537	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RD" ,
1538	dest,"out_MEMORY_OUT_WRITE_RD" );
1539	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RD" ,
1540	dest,"out_MEMORY_OUT_NUM_REG_RD" );
1541	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RD" ,
1542	dest,"out_MEMORY_OUT_DATA_RD" );
1543	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_WRITE_RE" ,
1544	dest,"out_MEMORY_OUT_WRITE_RE" );
1545	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NUM_REG_RE" ,
1546	dest,"out_MEMORY_OUT_NUM_REG_RE" );
1547	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_DATA_RE" ,
1548	dest,"out_MEMORY_OUT_DATA_RE" );
1549	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_EXCEPTION" ,
1550	dest,"out_MEMORY_OUT_EXCEPTION" );
1551	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_NO_SEQUENCE" ,
1552	dest,"out_MEMORY_OUT_NO_SEQUENCE" );
1553	PORT_MAP(_component ,src , "in_EXECUTE_UNIT_OUT_"+toString(i)+"_ADDRESS" ,
1554	dest,"out_MEMORY_OUT_ADDRESS" );
1555	}
1556	}
1557
1558	// ~~~~~[ Interface "write_unit_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1559	for (uint32_t i=0; i<_param->_nb_write_unit; i++)
1560	{
1561	dest = _name+"_write_unit_"+toString(i);
1562
1563	#ifdef POSITION
1564	_component->interface_map (src ,"write_unit_out_"+toString(i),
1565	dest,"write_out");
1566	#endif
1567
1568	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_VAL" ,
1569	dest, "in_WRITE_UNIT_IN_VAL" );
1570	PORT_MAP(_component ,src , "in_WRITE_UNIT_IN_"+toString(i)+"_ACK" ,
1571	dest,"out_WRITE_UNIT_IN_ACK" );
1572	if (_param->_have_port_context_id)
1573	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_CONTEXT_ID" ,
1574	dest, "in_WRITE_UNIT_IN_CONTEXT_ID" );
1575	if (_param->_have_port_front_end_id)
1576	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_FRONT_END_ID" ,
1577	dest, "in_WRITE_UNIT_IN_FRONT_END_ID" );
1578	if (_param->_have_port_ooo_engine_id)
1579	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_OOO_ENGINE_ID",
1580	dest, "in_WRITE_UNIT_IN_OOO_ENGINE_ID");
1581	if (_param->_have_port_packet_id)
1582	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_PACKET_ID" ,
1583	dest, "in_WRITE_UNIT_IN_PACKET_ID" );
1584	// PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_OPERATION" ,
1585	// dest, "in_WRITE_UNIT_IN_OPERATION" );
1586	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_TYPE" ,
1587	dest, "in_WRITE_UNIT_IN_TYPE" );
1588	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RD" ,
1589	dest, "in_WRITE_UNIT_IN_WRITE_RD" );
1590	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RD" ,
1591	dest, "in_WRITE_UNIT_IN_NUM_REG_RD" );
1592	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RD" ,
1593	dest, "in_WRITE_UNIT_IN_DATA_RD" );
1594	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_WRITE_RE" ,
1595	dest, "in_WRITE_UNIT_IN_WRITE_RE" );
1596	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_NUM_REG_RE" ,
1597	dest, "in_WRITE_UNIT_IN_NUM_REG_RE" );
1598	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_DATA_RE" ,
1599	dest, "in_WRITE_UNIT_IN_DATA_RE" );
1600	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_EXCEPTION" ,
1601	dest, "in_WRITE_UNIT_IN_EXCEPTION" );
1602	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_NO_SEQUENCE" ,
1603	dest, "in_WRITE_UNIT_IN_NO_SEQUENCE" );
1604	PORT_MAP(_component ,src ,"out_WRITE_UNIT_IN_"+toString(i)+"_ADDRESS" ,
1605	dest, "in_WRITE_UNIT_IN_ADDRESS" );
1606	}
1607	}
1608
1609	_component->test_map();
1610	for (uint32_t i=0; i<_param->_nb_read_unit; i++)
1611	_component_read_unit [i]->_component->test_map();
1612	for (uint32_t i=0; i<_param->_nb_functionnal_unit; i++)
1613	_component_functionnal_unit [i]->_component->test_map();
1614	for (uint32_t i=0; i<_param->_nb_load_store_unit; i++)
1615	_component_load_store_unit [i]->_component->test_map();
1616	for (uint32_t i=0; i<_param->_nb_write_unit; i++)
1617	_component_write_unit [i]->_component->test_map();
1618	_component_read_unit_to_execution_unit->_component->test_map();
1619	_component_execution_unit_to_write_unit->_component->test_map();
1620	_component_register_unit->_component->test_map();
1621
1622	#ifdef POSITION
1623	_component->generate_file();
1624	#endif
1625
1626	log_printf(FUNC,Execute_loop,FUNCTION,"End");
1627	};
1628
1629	}; // end namespace execute_loop
1630	}; // end namespace multi_execute_loop
1631	}; // end namespace core
1632
1633	}; // end namespace behavioural
1634	}; // end namespace morpheo

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