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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp @ 83

Last change on this file since 83 was 83, checked in by rosiere, 16 years ago
Add component : Context_State (manage miss prediction, exception , decod_enable, synchronisation instruction ...)
Property svn:keywords set to `Id`
File size: 46.0 KB

Line
1	/*
2	* $Id: test.cpp 83 2008-05-09 18:00:21Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::context_state::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Context_State * _Context_State = new Context_State
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_VAL ," in_DECOD_EVENT_VAL ",Tcontrol_t ,_param->_nb_decod_unit);
51	ALLOC1_SC_SIGNAL(out_DECOD_EVENT_ACK ,"out_DECOD_EVENT_ACK ",Tcontrol_t ,_param->_nb_decod_unit);
52	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ," in_DECOD_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit);
53	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ," in_DECOD_EVENT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit);
54	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_TYPE ," in_DECOD_EVENT_TYPE ",Tevent_type_t,_param->_nb_decod_unit);
55	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ," in_DECOD_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_decod_unit);
56	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ," in_DECOD_EVENT_ADDRESS ",Taddress_t ,_param->_nb_decod_unit);
57	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit);
58
59	ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t ,_param->_nb_ooo_engine);
60	ALLOC1_SC_SIGNAL(out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t ,_param->_nb_ooo_engine);
61	ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_ooo_engine);
62	ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t ,_param->_nb_ooo_engine);
63	ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t,_param->_nb_ooo_engine);
64	ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_ooo_engine);
65	ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t ,_param->_nb_ooo_engine);
66	ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_ooo_engine);
67	ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t ,_param->_nb_ooo_engine);
68	ALLOC1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t ,_param->_nb_ooo_engine);
69
70	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
71	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
72	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
73	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
74	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
75	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ," in_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
76	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ," in_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
77	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ," in_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
78
79
80	ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_decod_unit);
81	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_ooo_engine);
82	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_ooo_engine);
83
84	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
85	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
86	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context );
87	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context );
88	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context );
89	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context );
90
91	ALLOC1_SC_SIGNAL(out_SPR_VAL ,"out_SPR_VAL ",Tcontrol_t ,_param->_nb_context );
92	ALLOC1_SC_SIGNAL( in_SPR_ACK ," in_SPR_ACK ",Tcontrol_t ,_param->_nb_context );
93	ALLOC1_SC_SIGNAL(out_SPR_EPCR ,"out_SPR_EPCR ",Taddress_t ,_param->_nb_context );
94	ALLOC1_SC_SIGNAL(out_SPR_EEAR ,"out_SPR_EEAR ",Taddress_t ,_param->_nb_context );
95	ALLOC1_SC_SIGNAL(out_SPR_EEAR_WEN ,"out_SPR_EEAR_WEN ",Tcontrol_t ,_param->_nb_context );
96	ALLOC1_SC_SIGNAL(out_SPR_SR_DSX ,"out_SPR_SR_DSX ",Tcontrol_t ,_param->_nb_context );
97	ALLOC1_SC_SIGNAL(out_SPR_SR_TO_ESR ,"out_SPR_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context );
98
99	ALLOC1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,"out_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context );
100
101	ALLOC1_SC_SIGNAL( in_DEPTH_TAIL ," in_DEPTH_TAIL ",Tdepth_t ,_param->_nb_context );
102
103	/********************************************************
104	* Instanciation
105	********************************************************/
106
107	msg(_("<%s> : Instanciation of _Context_State.\n"),name.c_str());
108
109	((_Context_State->in_CLOCK)) ((in_CLOCK));
110	((_Context_State->in_NRESET)) ((in_NRESET));
111
112	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
113	INSTANCE1_SC_SIGNAL(_Context_State,out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
114	if (_param->_have_port_context_id)
115	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
116	if (_param->_have_port_max_depth)
117	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
118	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
119	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
120	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
121	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
122
123	INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_VAL ,_param->_nb_ooo_engine);
124	INSTANCE1_SC_SIGNAL(_Context_State,out_COMMIT_EVENT_ACK ,_param->_nb_ooo_engine);
125	if (_param->_have_port_context_id)
126	INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_CONTEXT_ID ,_param->_nb_ooo_engine);
127	if (_param->_have_port_max_depth)
128	INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_DEPTH ,_param->_nb_ooo_engine);
129	INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_TYPE ,_param->_nb_ooo_engine);
130	INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT ,_param->_nb_ooo_engine);
131	INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS ,_param->_nb_ooo_engine);
132	INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_nb_ooo_engine);
133	INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine);
134	INSTANCE1_SC_SIGNAL(_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_nb_ooo_engine);
135
136	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
137	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
138	if (_param->_have_port_context_id)
139	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
140	if (_param->_have_port_max_depth)
141	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
142	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
143	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
144	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
145	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
146
147	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_decod_unit);
148	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_ooo_engine);
149	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_ooo_engine);
150
151	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_VAL ,_param->_nb_context );
152	INSTANCE1_SC_SIGNAL(_Context_State, in_EVENT_ACK ,_param->_nb_context );
153	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS ,_param->_nb_context );
154	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
155	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
156	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context );
157
158	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_VAL ,_param->_nb_context );
159	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_ACK ,_param->_nb_context );
160	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EPCR ,_param->_nb_context );
161	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EEAR ,_param->_nb_context );
162	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EEAR_WEN ,_param->_nb_context );
163	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_SR_DSX ,_param->_nb_context );
164	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_SR_TO_ESR ,_param->_nb_context );
165
166	INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
167
168	for (uint32_t i=0; i<_param->_nb_context; i++)
169	if (_param->_have_port_depth [i])
170	INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_TAIL [i]);
171
172	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
173
174	Time * _time = new Time();
175
176	/********************************************************
177	* Simulation - Begin
178	********************************************************/
179
180	// Initialisation
181
182	const uint32_t seed = 0;
183	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
184
185	srand(seed);
186
187	const int32_t percent_transaction_decod_event = 75;
188	const int32_t percent_transaction_commit_event = 75;
189	const int32_t percent_transaction_branch_complete = 75;
190	const int32_t percent_transaction_event = 75;
191	const int32_t percent_transaction_spr = 75;
192
193	SC_START(0);
194	LABEL("Initialisation");
195
196	LABEL("Reset");
197	in_NRESET->write(0);
198	SC_START(5);
199	in_NRESET->write(1);
200
201	LABEL("Loop of Test");
202
203	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
204	{
205	LABEL("Iteration %d",iteration);
206	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
207	in_DECOD_EVENT_VAL [i]->write(0);
208	for (uint32_t i=0; i<_param->_nb_ooo_engine; i++)
209	in_COMMIT_EVENT_VAL [i]->write(0);
210	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
211	in_BRANCH_COMPLETE_VAL [i]->write(0);
212
213	for (uint32_t i=0; i<_param->_nb_context; i++)
214	{
215	in_EVENT_ACK [i]->write(0);
216	in_SPR_ACK [i]->write(0);
217
218	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[i]->read(), 1);
219	}
220
221	for (uint32_t i=0; i<_param->_nb_context; i++)
222	if (_param->_have_port_depth [i])
223	in_DEPTH_TAIL [i]->write(i%_param->_size_depth[i]);
224
225	uint32_t context = rand()%_param->_nb_context;
226	uint32_t decod_unit = _param->_link_context_to_decod_unit [context];
227	uint32_t ooo_engine = _param->_link_decod_unit_to_ooo_engine [decod_unit];
228
229	if (1)
230	{
231	SC_START(3);
232
233	LABEL("msync (begin)");
234	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
235	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
236	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
237
238	uint32_t port = rand()%_param->_nb_decod_unit;
239
240	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
241	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
242	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
243	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
244	if (_param->_have_port_depth [context])
245	in_DECOD_EVENT_DEPTH [port]->write((context+1)%_param->_size_depth[context]);
246	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC);
247
248	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
249
250	do
251	{
252	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
253
254	SC_START(1);
255	}
256	while (not ( in_DECOD_EVENT_VAL [port]->read() and
257	out_DECOD_EVENT_ACK [port]->read()));
258	in_DECOD_EVENT_VAL [port]->write(0);
259
260	LABEL("msync (wait end)");
261	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
262
263	SC_START(3);
264
265	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
266	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
267	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
268
269	SC_START(1);
270
271	LABEL("msync (send decod)");
272	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
273
274	SC_START(3);
275
276	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
277	SC_START(1);
278
279	LABEL("msync (wait end)");
280	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
281	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
282	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
283
284	SC_START(3);
285
286	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
287	SC_START(1);
288	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
289	}
290
291	if (1)
292	{
293	SC_START(3);
294
295	LABEL("psync (begin)");
296	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
297	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
298	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
299
300	uint32_t port = rand()%_param->_nb_decod_unit;
301
302	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
303	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
304	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
305	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
306	if (_param->_have_port_depth [context])
307	in_DECOD_EVENT_DEPTH [port]->write((context+1)%_param->_size_depth[context]);
308	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC);
309
310	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
311
312	do
313	{
314	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
315
316	SC_START(1);
317	}
318	while (not ( in_DECOD_EVENT_VAL [port]->read() and
319	out_DECOD_EVENT_ACK [port]->read()));
320	in_DECOD_EVENT_VAL [port]->write(0);
321
322	LABEL("psync (wait end)");
323	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
324
325	SC_START(3);
326
327	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
328	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
329	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
330
331	SC_START(1);
332
333	bool find = false;
334	do
335	{
336	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
337
338	SC_START(0);
339
340	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
341	{
342	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
343	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
344	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
345	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
346
347	find = true;
348	}
349
350	SC_START(1);
351	}
352	while (not find);
353
354	in_EVENT_ACK [context]->write(0);
355	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
356	}
357
358	if (1)
359	{
360	SC_START(3);
361
362	LABEL("csync (begin)");
363	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
364	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
365	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
366
367	uint32_t port = rand()%_param->_nb_decod_unit;
368
369	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
370	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
371	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
372	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
373	if (_param->_have_port_depth [context])
374	in_DECOD_EVENT_DEPTH [port]->write((context+1)%_param->_size_depth[context]);
375	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC);
376
377	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
378
379	do
380	{
381	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
382
383	SC_START(1);
384	}
385	while (not ( in_DECOD_EVENT_VAL [port]->read() and
386	out_DECOD_EVENT_ACK [port]->read()));
387	in_DECOD_EVENT_VAL [port]->write(0);
388
389	LABEL("csync (wait end)");
390	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
391
392	SC_START(3);
393
394	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
395	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
396	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
397
398	SC_START(1);
399
400	bool find = false;
401	do
402	{
403	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
404
405	SC_START(0);
406
407	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
408	{
409	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
410	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
411	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
412	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
413
414	find = true;
415	}
416
417	SC_START(1);
418	}
419	while (not find);
420	in_EVENT_ACK [context]->write(0);
421	}
422
423	if (1)
424	{
425	SC_START(3);
426
427	LABEL("spr (begin)");
428	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
429	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
430	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
431
432	uint32_t port = rand()%_param->_nb_decod_unit;
433
434	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
435	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
436	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
437	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
438	if (_param->_have_port_depth [context])
439	in_DECOD_EVENT_DEPTH [port]->write((context+1)%_param->_size_depth[context]);
440	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS);
441
442	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
443
444	do
445	{
446	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
447
448	SC_START(1);
449	}
450	while (not ( in_DECOD_EVENT_VAL [port]->read() and
451	out_DECOD_EVENT_ACK [port]->read()));
452	in_DECOD_EVENT_VAL [port]->write(0);
453
454	LABEL("spr (wait end)");
455	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
456
457	SC_START(3);
458
459	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
460	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
461	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
462
463	SC_START(1);
464
465	LABEL("spr (send decod)");
466	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
467
468	SC_START(3);
469
470	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
471	SC_START(1);
472
473	LABEL("spr (wait end)");
474	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
475	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
476	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
477
478	SC_START(3);
479
480	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
481	SC_START(1);
482	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
483	}
484
485	if (1)
486	{
487	SC_START(3);
488
489	LABEL("miss (begin)");
490	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
491	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
492	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
493
494	uint32_t port = rand()%_param->_nb_inst_branch_complete;
495
496	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
497	if (_param->_have_port_depth [context])
498	in_BRANCH_COMPLETE_DEPTH [port]->write((context+1)%_param->_size_depth[context]);
499	in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400);
500	in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500);
501	in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
502	in_BRANCH_COMPLETE_TAKE [port]->write(0);
503
504	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
505
506	do
507	{
508	in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
509
510	SC_START(1);
511	}
512	while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
513	out_BRANCH_COMPLETE_ACK [port]->read()));
514	in_BRANCH_COMPLETE_VAL [port]->write(0);
515
516	LABEL("miss (wait end)");
517	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
518
519	SC_START(3);
520
521	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
522	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
523	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
524
525	SC_START(1);
526
527	LABEL("miss (wait event)");
528
529
530	bool find = false;
531	do
532	{
533	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
534
535	SC_START(0);
536
537	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
538	{
539	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x401);
540	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x500);
541	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
542	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
543
544	find = true;
545	}
546
547	SC_START(1);
548	}
549	while (not find);
550
551	in_EVENT_ACK [context]->write(0);
552
553	}
554
555	if (1)
556	{
557	SC_START(3);
558
559	LABEL("miss (begin)");
560	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
561	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
562	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
563
564	uint32_t port = rand()%_param->_nb_inst_branch_complete;
565
566	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
567	if (_param->_have_port_depth [context])
568	in_BRANCH_COMPLETE_DEPTH [port]->write((context+1)%_param->_size_depth[context]);
569	in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600);
570	in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700);
571	in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
572	in_BRANCH_COMPLETE_TAKE [port]->write(1);
573
574	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
575
576	do
577	{
578	in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
579
580	SC_START(1);
581	}
582	while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
583	out_BRANCH_COMPLETE_ACK [port]->read()));
584	in_BRANCH_COMPLETE_VAL [port]->write(0);
585
586	LABEL("miss (wait end)");
587	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
588
589	SC_START(3);
590
591	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
592	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
593	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
594
595	SC_START(1);
596
597	LABEL("miss (wait event)");
598
599	bool find = false;
600	do
601	{
602	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
603
604	SC_START(0);
605
606	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
607	{
608	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x601);
609	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x700);
610	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),1);
611	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),1);
612
613	find = true;
614	}
615
616	SC_START(1);
617	}
618	while (not find);
619
620	in_EVENT_ACK [context]->write(0);
621	}
622
623	if (1)
624	{
625	SC_START(3);
626
627	LABEL("exception (begin)");
628	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
629	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
630	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
631
632	uint32_t port = rand()%_param->_nb_ooo_engine;
633
634	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
635	if (_param->_have_port_depth [context])
636	in_DECOD_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]);
637	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
638	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
639	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
640	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
641
642	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
643
644	do
645	{
646	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
647
648	SC_START(1);
649	}
650	while (not ( in_DECOD_EVENT_VAL [port]->read() and
651	out_DECOD_EVENT_ACK [port]->read()));
652	in_DECOD_EVENT_VAL [port]->write(0);
653
654	LABEL("exception (wait end)");
655	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
656
657	SC_START(3);
658
659	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
660	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
661	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
662
663	SC_START(1);
664
665	LABEL("exception (wait event)");
666
667	bool find = false;
668	do
669	{
670	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
671
672	SC_START(0);
673
674	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
675	{
676	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
677	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
678	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
679	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
680
681	find = true;
682	}
683
684	SC_START(1);
685	}
686	while (not find);
687
688	in_EVENT_ACK [context]->write(0);
689
690	LABEL("exception (wait spr)");
691
692	find = false;
693	do
694	{
695	in_SPR_ACK [context]->write(rand()%percent_transaction_spr);
696
697	SC_START(0);
698
699	if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read())
700	{
701	TEST(Taddress_t,out_SPR_EPCR [context]->read(),0x900);
702	//TEST(Taddress_t,out_SPR_EEAR [context]->read(),);
703	TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),0);
704	TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),0);
705	TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1);
706
707	find = true;
708	}
709
710	SC_START(1);
711	}
712	while (not find);
713
714	in_SPR_ACK [context]->write(0);
715	}
716
717	if (1)
718	{
719	SC_START(3);
720
721	LABEL("exception (begin)");
722	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
723	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
724	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
725
726	uint32_t port = rand()%_param->_nb_ooo_engine;
727
728	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
729	if (_param->_have_port_depth [context])
730	in_DECOD_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]);
731	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
732	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1);
733	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
734	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
735
736	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
737
738	do
739	{
740	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
741
742	SC_START(1);
743	}
744	while (not ( in_DECOD_EVENT_VAL [port]->read() and
745	out_DECOD_EVENT_ACK [port]->read()));
746	in_DECOD_EVENT_VAL [port]->write(0);
747
748	LABEL("exception (wait end)");
749	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
750
751	SC_START(3);
752
753	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
754	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
755	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
756
757	SC_START(1);
758
759	LABEL("exception (wait event)");
760
761	bool find = false;
762	do
763	{
764	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
765
766	SC_START(0);
767
768	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
769	{
770	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
771	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
772	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
773	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
774
775	find = true;
776	}
777
778	SC_START(1);
779	}
780	while (not find);
781
782	in_EVENT_ACK [context]->write(0);
783
784	LABEL("exception (wait spr)");
785
786	find = false;
787	do
788	{
789	in_SPR_ACK [context]->write(rand()%percent_transaction_spr);
790
791	SC_START(0);
792
793	if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read())
794	{
795	TEST(Taddress_t,out_SPR_EPCR [context]->read(),0x900);
796	//TEST(Taddress_t,out_SPR_EEAR [context]->read(),);
797	TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),0);
798	TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),1);
799	TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1);
800
801	find = true;
802	}
803
804	SC_START(1);
805	}
806	while (not find);
807
808	in_SPR_ACK [context]->write(0);
809	}
810
811	if (1)
812	{
813	SC_START(3);
814
815	LABEL("exception (begin)");
816	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
817	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
818	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
819
820	uint32_t port = rand()%_param->_nb_ooo_engine;
821
822	in_COMMIT_EVENT_CONTEXT_ID [port]->write(context);
823	if (_param->_have_port_depth [context])
824	in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]);
825	in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
826	in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(0);
827	in_COMMIT_EVENT_ADDRESS [port]->write(0xa00);
828	in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xb00);
829	in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xc00);
830	in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(0);
831
832	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
833
834	do
835	{
836	in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event);
837
838	SC_START(1);
839	}
840	while (not ( in_COMMIT_EVENT_VAL [port]->read() and
841	out_COMMIT_EVENT_ACK [port]->read()));
842	in_COMMIT_EVENT_VAL [port]->write(0);
843
844	LABEL("exception (wait end)");
845	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
846
847	SC_START(3);
848
849	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
850	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
851	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
852
853	SC_START(1);
854
855	LABEL("exception (wait event)");
856
857	bool find = false;
858	do
859	{
860	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
861
862	SC_START(0);
863
864	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
865	{
866	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
867	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
868	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
869	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
870
871	find = true;
872	}
873
874	SC_START(1);
875	}
876	while (not find);
877
878	in_EVENT_ACK [context]->write(0);
879
880	LABEL("exception (wait spr)");
881
882	find = false;
883	do
884	{
885	in_SPR_ACK [context]->write(rand()%percent_transaction_spr);
886
887	SC_START(0);
888
889	if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read())
890	{
891	TEST(Taddress_t,out_SPR_EPCR [context]->read(),0xb00);
892	TEST(Taddress_t,out_SPR_EEAR [context]->read(),0xc00);
893	TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),0);
894	TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),0);
895	TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1);
896
897	find = true;
898	}
899
900	SC_START(1);
901	}
902	while (not find);
903
904	in_SPR_ACK [context]->write(0);
905	}
906
907	if (1)
908	{
909	SC_START(3);
910
911	LABEL("exception (begin)");
912	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
913	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
914	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
915
916	uint32_t port = rand()%_param->_nb_ooo_engine;
917
918	in_COMMIT_EVENT_CONTEXT_ID [port]->write(context);
919	if (_param->_have_port_depth [context])
920	in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]);
921	in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
922	in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(1);
923	in_COMMIT_EVENT_ADDRESS [port]->write(0xd00);
924	in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xe00);
925	in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xf00);
926	in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(0);
927
928	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
929
930	do
931	{
932	in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event);
933
934	SC_START(1);
935	}
936	while (not ( in_COMMIT_EVENT_VAL [port]->read() and
937	out_COMMIT_EVENT_ACK [port]->read()));
938	in_COMMIT_EVENT_VAL [port]->write(0);
939
940	LABEL("exception (wait end)");
941	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
942
943	SC_START(3);
944
945	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
946	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
947	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
948
949	SC_START(1);
950
951	LABEL("exception (wait event)");
952
953	bool find = false;
954	do
955	{
956	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
957
958	SC_START(0);
959
960	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
961	{
962	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
963	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
964	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
965	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
966
967	find = true;
968	}
969
970	SC_START(1);
971	}
972	while (not find);
973
974	in_EVENT_ACK [context]->write(0);
975
976	LABEL("exception (wait spr)");
977
978	find = false;
979	do
980	{
981	in_SPR_ACK [context]->write(rand()%percent_transaction_spr);
982
983	SC_START(0);
984
985	if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read())
986	{
987	TEST(Taddress_t,out_SPR_EPCR [context]->read(),0xe00);
988	TEST(Taddress_t,out_SPR_EEAR [context]->read(),0xf00);
989	TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),0);
990	TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),1);
991	TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1);
992
993	find = true;
994	}
995
996	SC_START(1);
997	}
998	while (not find);
999
1000	in_SPR_ACK [context]->write(0);
1001	}
1002
1003	if (1)
1004	{
1005	SC_START(3);
1006
1007	LABEL("exception (begin)");
1008	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
1009	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
1010	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
1011
1012	uint32_t port = rand()%_param->_nb_ooo_engine;
1013
1014	in_COMMIT_EVENT_CONTEXT_ID [port]->write(context);
1015	if (_param->_have_port_depth [context])
1016	in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]);
1017	in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
1018	in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(0);
1019	in_COMMIT_EVENT_ADDRESS [port]->write(0xa00);
1020	in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xb00);
1021	in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xc00);
1022	in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(1);
1023
1024	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1025
1026	do
1027	{
1028	in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event);
1029
1030	SC_START(1);
1031	}
1032	while (not ( in_COMMIT_EVENT_VAL [port]->read() and
1033	out_COMMIT_EVENT_ACK [port]->read()));
1034	in_COMMIT_EVENT_VAL [port]->write(0);
1035
1036	LABEL("exception (wait end)");
1037	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1038
1039	SC_START(3);
1040
1041	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
1042	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
1043	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
1044
1045	SC_START(1);
1046
1047	LABEL("exception (wait event)");
1048
1049	bool find = false;
1050	do
1051	{
1052	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1053
1054	SC_START(0);
1055
1056	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1057	{
1058	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
1059	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
1060	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1061	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1062
1063	find = true;
1064	}
1065
1066	SC_START(1);
1067	}
1068	while (not find);
1069
1070	in_EVENT_ACK [context]->write(0);
1071
1072	LABEL("exception (wait spr)");
1073
1074	find = false;
1075	do
1076	{
1077	in_SPR_ACK [context]->write(rand()%percent_transaction_spr);
1078
1079	SC_START(0);
1080
1081	if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read())
1082	{
1083	TEST(Taddress_t,out_SPR_EPCR [context]->read(),0xb00);
1084	TEST(Taddress_t,out_SPR_EEAR [context]->read(),0xc00);
1085	TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),1);
1086	TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),0);
1087	TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1);
1088
1089	find = true;
1090	}
1091
1092	SC_START(1);
1093	}
1094	while (not find);
1095
1096	in_SPR_ACK [context]->write(0);
1097	}
1098
1099	if (1)
1100	{
1101	SC_START(3);
1102
1103	LABEL("exception (begin)");
1104	in_NB_INST_DECOD_ALL [decod_unit]->write(1);
1105	in_NB_INST_COMMIT_ALL [ooo_engine]->write(1);
1106	in_NB_INST_COMMIT_MEM [ooo_engine]->write(1);
1107
1108	uint32_t port = rand()%_param->_nb_ooo_engine;
1109
1110	in_COMMIT_EVENT_CONTEXT_ID [port]->write(context);
1111	if (_param->_have_port_depth [context])
1112	in_COMMIT_EVENT_DEPTH [port]->write((context)%_param->_size_depth[context]);
1113	in_COMMIT_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
1114	in_COMMIT_EVENT_IS_DELAY_SLOT [port]->write(1);
1115	in_COMMIT_EVENT_ADDRESS [port]->write(0xd00);
1116	in_COMMIT_EVENT_ADDRESS_EPCR [port]->write(0xe00);
1117	in_COMMIT_EVENT_ADDRESS_EEAR [port]->write(0xf00);
1118	in_COMMIT_EVENT_ADDRESS_EEAR_VAL [port]->write(1);
1119
1120	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1121
1122	do
1123	{
1124	in_COMMIT_EVENT_VAL [port]->write(rand()%percent_transaction_commit_event);
1125
1126	SC_START(1);
1127	}
1128	while (not ( in_COMMIT_EVENT_VAL [port]->read() and
1129	out_COMMIT_EVENT_ACK [port]->read()));
1130	in_COMMIT_EVENT_VAL [port]->write(0);
1131
1132	LABEL("exception (wait end)");
1133	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1134
1135	SC_START(3);
1136
1137	in_NB_INST_DECOD_ALL [decod_unit]->write(0);
1138	in_NB_INST_COMMIT_ALL [ooo_engine]->write(0);
1139	in_NB_INST_COMMIT_MEM [ooo_engine]->write(0);
1140
1141	SC_START(1);
1142
1143	LABEL("exception (wait event)");
1144
1145	bool find = false;
1146	do
1147	{
1148	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1149
1150	SC_START(0);
1151
1152	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1153	{
1154	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1155	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1156	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1157	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1158
1159	find = true;
1160	}
1161
1162	SC_START(1);
1163	}
1164	while (not find);
1165
1166	in_EVENT_ACK [context]->write(0);
1167
1168	LABEL("exception (wait spr)");
1169
1170	find = false;
1171	do
1172	{
1173	in_SPR_ACK [context]->write(rand()%percent_transaction_spr);
1174
1175	SC_START(0);
1176
1177	if (out_SPR_VAL [context]->read() and in_SPR_ACK [context]->read())
1178	{
1179	TEST(Taddress_t,out_SPR_EPCR [context]->read(),0xe00);
1180	TEST(Taddress_t,out_SPR_EEAR [context]->read(),0xf00);
1181	TEST(Tcontrol_t,out_SPR_EEAR_WEN [context]->read(),1);
1182	TEST(Tcontrol_t,out_SPR_SR_DSX [context]->read(),1);
1183	TEST(Tcontrol_t,out_SPR_SR_TO_ESR [context]->read(),1);
1184
1185	find = true;
1186	}
1187
1188	SC_START(1);
1189	}
1190	while (not find);
1191
1192	in_SPR_ACK [context]->write(0);
1193	}
1194
1195
1196	SC_START(1);
1197	}
1198
1199
1200	/********************************************************
1201	* Simulation - End
1202	********************************************************/
1203
1204	TEST_OK ("End of Simulation");
1205	delete _time;
1206
1207	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
1208
1209	delete in_CLOCK;
1210	delete in_NRESET;
1211
1212	DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
1213	DELETE1_SC_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
1214	DELETE1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
1215	DELETE1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
1216	DELETE1_SC_SIGNAL( in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
1217	DELETE1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
1218	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
1219	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
1220	DELETE1_SC_SIGNAL( in_COMMIT_EVENT_VAL ,_param->_nb_ooo_engine);
1221	DELETE1_SC_SIGNAL(out_COMMIT_EVENT_ACK ,_param->_nb_ooo_engine);
1222	DELETE1_SC_SIGNAL( in_COMMIT_EVENT_CONTEXT_ID ,_param->_nb_ooo_engine);
1223	DELETE1_SC_SIGNAL( in_COMMIT_EVENT_DEPTH ,_param->_nb_ooo_engine);
1224	DELETE1_SC_SIGNAL( in_COMMIT_EVENT_TYPE ,_param->_nb_ooo_engine);
1225	DELETE1_SC_SIGNAL( in_COMMIT_EVENT_IS_DELAY_SLOT ,_param->_nb_ooo_engine);
1226	DELETE1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS ,_param->_nb_ooo_engine);
1227	DELETE1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EPCR ,_param->_nb_ooo_engine);
1228	DELETE1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ,_param->_nb_ooo_engine);
1229	DELETE1_SC_SIGNAL( in_COMMIT_EVENT_ADDRESS_EEAR ,_param->_nb_ooo_engine);
1230	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
1231	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
1232	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
1233	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
1234	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
1235	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
1236	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
1237	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
1238	DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_decod_unit);
1239	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_ooo_engine);
1240	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_ooo_engine);
1241	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context );
1242	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context );
1243	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context );
1244	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
1245	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
1246	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context );
1247	DELETE1_SC_SIGNAL(out_SPR_VAL ,_param->_nb_context );
1248	DELETE1_SC_SIGNAL( in_SPR_ACK ,_param->_nb_context );
1249	DELETE1_SC_SIGNAL(out_SPR_EPCR ,_param->_nb_context );
1250	DELETE1_SC_SIGNAL(out_SPR_EEAR ,_param->_nb_context );
1251	DELETE1_SC_SIGNAL(out_SPR_EEAR_WEN ,_param->_nb_context );
1252	DELETE1_SC_SIGNAL(out_SPR_SR_DSX ,_param->_nb_context );
1253	DELETE1_SC_SIGNAL(out_SPR_SR_TO_ESR ,_param->_nb_context );
1254	DELETE1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
1255	DELETE1_SC_SIGNAL( in_DEPTH_TAIL ,_param->_nb_context );
1256	}
1257	#endif
1258
1259	delete _Context_State;
1260	#ifdef STATISTICS
1261	delete _parameters_statistics;
1262	#endif
1263	}

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