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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp @ 95

Last change on this file since 95 was 95, checked in by rosiere, 16 years ago
1) Update Prediction Table - New architecture (systemC) done (and tested) -> need change interface in top level 2) Change documentation on VHDL generation 3) Change VHDL constant (case std_logic and std_logic_vector)
Property svn:keywords set to `Id`
File size: 48.7 KB

Line
1	/*
2	* $Id: test.cpp 95 2008-12-16 16:24:26Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::context_state::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Context_State * _Context_State = new Context_State
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_VAL ," in_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
51	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
52	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
53	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
54	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context);
55	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
56	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ," in_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context);
57	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
58
59	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_VAL ," in_DECOD_EVENT_VAL ",Tcontrol_t ,_param->_nb_decod_unit);
60	ALLOC1_SC_SIGNAL(out_DECOD_EVENT_ACK ,"out_DECOD_EVENT_ACK ",Tcontrol_t ,_param->_nb_decod_unit);
61	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ," in_DECOD_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit);
62	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ," in_DECOD_EVENT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit);
63	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_TYPE ," in_DECOD_EVENT_TYPE ",Tevent_type_t,_param->_nb_decod_unit);
64	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ," in_DECOD_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_decod_unit);
65	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ," in_DECOD_EVENT_ADDRESS ",Taddress_t ,_param->_nb_decod_unit);
66	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit);
67
68	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t );
69	ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t );
70	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );
71	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t );
72	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t);
73	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
74	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t );
75	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );
76	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );
77	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Taddress_t );
78
79	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
80	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
81	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
82	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
83	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
84	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ," in_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
85	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ," in_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
86	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ," in_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
87
88
89	ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context );
90	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context );
91	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context );
92
93	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
94	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
95	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context );
96	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context );
97	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context );
98	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context );
99
100	ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
101	ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
102	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Taddress_t ,_param->_nb_context );
103	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Taddress_t ,_param->_nb_context );
104	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context );
105	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context );
106	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context );
107
108	ALLOC1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,"out_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context );
109
110	ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context );
111
112	ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context );
113	ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context );
114
115	ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context );
116
117	/********************************************************
118	* Instanciation
119	********************************************************/
120
121	msg(_("<%s> : Instanciation of _Context_State.\n"),name.c_str());
122
123	((_Context_State->in_CLOCK)) ((in_CLOCK));
124	((_Context_State->in_NRESET)) ((in_NRESET));
125
126	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_VAL ,_param->_nb_context);
127	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context);
128	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
129	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
130	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
131	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
132	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
133	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
134	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
135	INSTANCE1_SC_SIGNAL(_Context_State,out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
136	if (_param->_have_port_context_id)
137	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
138	if (_param->_have_port_depth)
139	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
140	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
141	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
142	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
143	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
144
145	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_VAL );
146	INSTANCE_SC_SIGNAL (_Context_State,out_COMMIT_EVENT_ACK );
147	if (_param->_have_port_context_id)
148	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_CONTEXT_ID );
149	if (_param->_have_port_depth)
150	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_DEPTH );
151	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_TYPE );
152	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT );
153	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS );
154	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR );
155	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
156	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR );
157
158	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
159	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
160	if (_param->_have_port_context_id)
161	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
162	if (_param->_have_port_depth)
163	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
164	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
165	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
166	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
167	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
168
169	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_context );
170	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_context );
171	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_context );
172
173	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_VAL ,_param->_nb_context );
174	INSTANCE1_SC_SIGNAL(_Context_State, in_EVENT_ACK ,_param->_nb_context );
175	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS ,_param->_nb_context );
176	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
177	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
178	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context );
179
180	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context );
181	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_EVENT_ACK ,_param->_nb_context );
182	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EPCR ,_param->_nb_context );
183	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR ,_param->_nb_context );
184	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
185	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_DSX ,_param->_nb_context );
186	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
187
188	INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
189
190	for (uint32_t i=0; i<_param->_nb_context; i++)
191	if (_param->_have_port_depth)
192	INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_MIN [i]);
193
194	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_IEE ,_param->_nb_context );
195	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_EPH ,_param->_nb_context );
196
197	INSTANCE1_SC_SIGNAL(_Context_State, in_INTERRUPT_ENABLE ,_param->_nb_context );
198
199	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
200
201	Time * _time = new Time();
202
203	/********************************************************
204	* Simulation - Begin
205	********************************************************/
206
207	// Initialisation
208
209	const uint32_t seed = 0;
210	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
211
212	srand(seed);
213
214	const int32_t percent_transaction_decod_event = 75;
215	const int32_t percent_transaction_commit_event = 75;
216	const int32_t percent_transaction_branch_complete = 75;
217	const int32_t percent_transaction_event = 75;
218	const int32_t percent_transaction_spr = 75;
219
220	SC_START(0);
221	LABEL("Initialisation");
222
223	LABEL("Reset");
224	in_NRESET->write(0);
225	SC_START(5);
226	in_NRESET->write(1);
227
228	LABEL("Loop of Test");
229
230	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
231	{
232	LABEL("Iteration %d",iteration);
233	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
234	in_DECOD_EVENT_VAL [i]->write(0);
235	in_COMMIT_EVENT_VAL ->write(0);
236	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
237	in_BRANCH_COMPLETE_VAL [i]->write(0);
238
239	for (uint32_t i=0; i<_param->_nb_context; i++)
240	{
241	in_BRANCH_EVENT_VAL [i]->write(0);
242	in_EVENT_ACK [i]->write(0);
243	in_SPR_EVENT_ACK [i]->write(0);
244	in_SPR_SR_IEE [i]->write(0);
245	in_SPR_SR_EPH [i]->write(0);
246	in_INTERRUPT_ENABLE [i]->write(0);
247
248	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[i]->read(), 1);
249	}
250
251	for (uint32_t i=0; i<_param->_nb_context; i++)
252	if (_param->_have_port_depth)
253	in_DEPTH_MIN [i]->write((_param->_array_size_depth[i]==0)?0:(i%_param->_array_size_depth[i]));
254
255	uint32_t context = rand()%_param->_nb_context;
256
257	if (1)
258	{
259	SC_START(3);
260
261	LABEL("msync (begin)");
262	in_NB_INST_DECOD_ALL [context]->write(1);
263	in_NB_INST_COMMIT_ALL [context]->write(1);
264	in_NB_INST_COMMIT_MEM [context]->write(1);
265
266	uint32_t port = rand()%_param->_nb_decod_unit;
267
268	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
269	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
270	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
271	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
272	if (_param->_have_port_depth)
273	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
274	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC);
275
276	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
277
278	do
279	{
280	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
281
282	SC_START(1);
283	}
284	while (not ( in_DECOD_EVENT_VAL [port]->read() and
285	out_DECOD_EVENT_ACK [port]->read()));
286	in_DECOD_EVENT_VAL [port]->write(0);
287
288	LABEL("msync (wait end)");
289	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
290
291	SC_START(3);
292
293	in_NB_INST_DECOD_ALL [context]->write(0);
294	in_NB_INST_COMMIT_ALL [context]->write(1);
295	in_NB_INST_COMMIT_MEM [context]->write(0);
296
297	SC_START(1);
298
299	LABEL("msync (send decod)");
300	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
301
302	SC_START(3);
303
304	in_NB_INST_DECOD_ALL [context]->write(1);
305	SC_START(1);
306
307	LABEL("msync (wait end)");
308	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
309	in_NB_INST_DECOD_ALL [context]->write(0);
310	in_NB_INST_COMMIT_MEM [context]->write(1);
311
312	SC_START(3);
313
314	in_NB_INST_COMMIT_MEM [context]->write(0);
315	SC_START(1);
316	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
317	}
318
319	if (1)
320	{
321	SC_START(3);
322
323	LABEL("psync (begin)");
324	in_NB_INST_DECOD_ALL [context]->write(1);
325	in_NB_INST_COMMIT_ALL [context]->write(1);
326	in_NB_INST_COMMIT_MEM [context]->write(1);
327
328	uint32_t port = rand()%_param->_nb_decod_unit;
329
330	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
331	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
332	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
333	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
334	if (_param->_have_port_depth)
335	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
336	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC);
337
338	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
339
340	do
341	{
342	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
343
344	SC_START(1);
345	}
346	while (not ( in_DECOD_EVENT_VAL [port]->read() and
347	out_DECOD_EVENT_ACK [port]->read()));
348	in_DECOD_EVENT_VAL [port]->write(0);
349
350	LABEL("psync (wait end)");
351	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
352
353	SC_START(3);
354
355	in_NB_INST_DECOD_ALL [context]->write(0);
356	in_NB_INST_COMMIT_ALL [context]->write(0);
357	in_NB_INST_COMMIT_MEM [context]->write(0);
358
359	SC_START(1);
360
361	bool find = false;
362	do
363	{
364	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
365
366	SC_START(0);
367
368	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
369	{
370	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
371	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
372	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
373	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
374
375	find = true;
376	}
377
378	SC_START(1);
379	}
380	while (not find);
381
382	in_EVENT_ACK [context]->write(0);
383	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
384	}
385
386	if (1)
387	{
388	SC_START(3);
389
390	LABEL("csync (begin)");
391	in_NB_INST_DECOD_ALL [context]->write(1);
392	in_NB_INST_COMMIT_ALL [context]->write(1);
393	in_NB_INST_COMMIT_MEM [context]->write(1);
394
395	uint32_t port = rand()%_param->_nb_decod_unit;
396
397	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
398	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
399	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
400	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
401	if (_param->_have_port_depth)
402	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
403	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC);
404
405	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
406
407	do
408	{
409	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
410
411	SC_START(1);
412	}
413	while (not ( in_DECOD_EVENT_VAL [port]->read() and
414	out_DECOD_EVENT_ACK [port]->read()));
415	in_DECOD_EVENT_VAL [port]->write(0);
416
417	LABEL("csync (wait end)");
418	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
419
420	SC_START(3);
421
422	in_NB_INST_DECOD_ALL [context]->write(0);
423	in_NB_INST_COMMIT_ALL [context]->write(0);
424	in_NB_INST_COMMIT_MEM [context]->write(0);
425
426	SC_START(1);
427
428	bool find = false;
429	do
430	{
431	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
432
433	SC_START(0);
434
435	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
436	{
437	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
438	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
439	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
440	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
441
442	find = true;
443	}
444
445	SC_START(1);
446	}
447	while (not find);
448	in_EVENT_ACK [context]->write(0);
449	}
450
451	if (1)
452	{
453	SC_START(3);
454
455	LABEL("spr (begin)");
456	in_NB_INST_DECOD_ALL [context]->write(1);
457	in_NB_INST_COMMIT_ALL [context]->write(1);
458	in_NB_INST_COMMIT_MEM [context]->write(1);
459
460	uint32_t port = rand()%_param->_nb_decod_unit;
461
462	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
463	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
464	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
465	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
466	if (_param->_have_port_depth)
467	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
468	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS);
469
470	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
471
472	do
473	{
474	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
475
476	SC_START(1);
477	}
478	while (not ( in_DECOD_EVENT_VAL [port]->read() and
479	out_DECOD_EVENT_ACK [port]->read()));
480	in_DECOD_EVENT_VAL [port]->write(0);
481
482	LABEL("spr (wait end)");
483	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
484
485	SC_START(3);
486
487	in_NB_INST_DECOD_ALL [context]->write(0);
488	in_NB_INST_COMMIT_ALL [context]->write(0);
489	in_NB_INST_COMMIT_MEM [context]->write(0);
490
491	SC_START(1);
492
493	LABEL("spr (send decod)");
494	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
495
496	SC_START(3);
497
498	in_NB_INST_DECOD_ALL [context]->write(1);
499	SC_START(1);
500
501	LABEL("spr (wait end)");
502	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
503	in_NB_INST_DECOD_ALL [context]->write(0);
504	in_NB_INST_COMMIT_ALL [context]->write(1);
505
506	SC_START(3);
507
508	in_NB_INST_COMMIT_ALL [context]->write(0);
509	SC_START(1);
510	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
511	}
512
513	if (1)
514	{
515	SC_START(3);
516
517	LABEL("miss (begin)");
518	in_NB_INST_DECOD_ALL [context]->write(1);
519	in_NB_INST_COMMIT_ALL [context]->write(1);
520	in_NB_INST_COMMIT_MEM [context]->write(1);
521
522	uint32_t port = rand()%_param->_nb_inst_branch_complete;
523
524	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
525	if (_param->_have_port_depth)
526	in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
527	in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400);
528	in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500);
529	in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
530	in_BRANCH_COMPLETE_TAKE [port]->write(0);
531
532	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
533
534	do
535	{
536	in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
537
538	SC_START(1);
539	}
540	while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
541	out_BRANCH_COMPLETE_ACK [port]->read()));
542	in_BRANCH_COMPLETE_VAL [port]->write(0);
543
544	LABEL("miss (wait end)");
545	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
546
547	SC_START(3);
548
549	in_NB_INST_DECOD_ALL [context]->write(0);
550	in_NB_INST_COMMIT_ALL [context]->write(0);
551	in_NB_INST_COMMIT_MEM [context]->write(0);
552
553	SC_START(1);
554
555	LABEL("miss (wait event)");
556
557
558	bool find = false;
559	do
560	{
561	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
562
563	SC_START(0);
564
565	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
566	{
567	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x401);
568	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x500);
569	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
570	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
571
572	find = true;
573	}
574
575	SC_START(1);
576	}
577	while (not find);
578
579	in_EVENT_ACK [context]->write(0);
580
581	}
582
583	if (1)
584	{
585	SC_START(3);
586
587	LABEL("miss (begin)");
588	in_NB_INST_DECOD_ALL [context]->write(1);
589	in_NB_INST_COMMIT_ALL [context]->write(1);
590	in_NB_INST_COMMIT_MEM [context]->write(1);
591
592	uint32_t port = rand()%_param->_nb_inst_branch_complete;
593
594	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
595	if (_param->_have_port_depth)
596	in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
597	in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600);
598	in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700);
599	in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
600	in_BRANCH_COMPLETE_TAKE [port]->write(1);
601
602	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
603
604	do
605	{
606	in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
607
608	SC_START(1);
609	}
610	while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
611	out_BRANCH_COMPLETE_ACK [port]->read()));
612	in_BRANCH_COMPLETE_VAL [port]->write(0);
613
614	LABEL("miss (wait end)");
615	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
616
617	SC_START(3);
618
619	in_NB_INST_DECOD_ALL [context]->write(0);
620	in_NB_INST_COMMIT_ALL [context]->write(0);
621	in_NB_INST_COMMIT_MEM [context]->write(0);
622
623	SC_START(1);
624
625	LABEL("miss (wait event)");
626
627	bool find = false;
628	do
629	{
630	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
631
632	SC_START(0);
633
634	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
635	{
636	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x601);
637	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x700);
638	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),1);
639	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),1);
640
641	find = true;
642	}
643
644	SC_START(1);
645	}
646	while (not find);
647
648	in_EVENT_ACK [context]->write(0);
649	}
650
651	if (1)
652	{
653	SC_START(3);
654
655	LABEL("exception (begin)");
656	in_NB_INST_DECOD_ALL [context]->write(1);
657	in_NB_INST_COMMIT_ALL [context]->write(1);
658	in_NB_INST_COMMIT_MEM [context]->write(1);
659
660	uint32_t port = rand()%_param->_nb_decod_unit;
661
662	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
663	if (_param->_have_port_depth)
664	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
665	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
666	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
667	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
668	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
669
670	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
671
672	do
673	{
674	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
675
676	SC_START(1);
677	}
678	while (not ( in_DECOD_EVENT_VAL [port]->read() and
679	out_DECOD_EVENT_ACK [port]->read()));
680	in_DECOD_EVENT_VAL [port]->write(0);
681
682	LABEL("exception (wait end)");
683	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
684
685	SC_START(3);
686
687	in_NB_INST_DECOD_ALL [context]->write(0);
688	in_NB_INST_COMMIT_ALL [context]->write(0);
689	in_NB_INST_COMMIT_MEM [context]->write(0);
690
691	SC_START(1);
692
693	LABEL("exception (wait event)");
694
695	bool find = false;
696	do
697	{
698	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
699
700	SC_START(0);
701
702	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
703	{
704	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
705	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
706	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
707	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
708
709	find = true;
710	}
711
712	SC_START(1);
713	}
714	while (not find);
715
716	in_EVENT_ACK [context]->write(0);
717
718	LABEL("exception (wait spr)");
719
720	find = false;
721	do
722	{
723	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
724
725	SC_START(0);
726
727	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
728	{
729	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
730	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
731	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
732	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
733	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
734
735	find = true;
736	}
737
738	SC_START(1);
739	}
740	while (not find);
741
742	in_SPR_EVENT_ACK [context]->write(0);
743	}
744
745	if (1)
746	{
747	SC_START(3);
748
749	LABEL("exception (begin)");
750	in_NB_INST_DECOD_ALL [context]->write(1);
751	in_NB_INST_COMMIT_ALL [context]->write(1);
752	in_NB_INST_COMMIT_MEM [context]->write(1);
753
754	uint32_t port = rand()%_param->_nb_decod_unit;
755
756	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
757	if (_param->_have_port_depth)
758	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
759	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
760	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1);
761	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
762	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
763
764	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
765
766	do
767	{
768	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
769
770	SC_START(1);
771	}
772	while (not ( in_DECOD_EVENT_VAL [port]->read() and
773	out_DECOD_EVENT_ACK [port]->read()));
774	in_DECOD_EVENT_VAL [port]->write(0);
775
776	LABEL("exception (wait end)");
777	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
778
779	SC_START(3);
780
781	in_NB_INST_DECOD_ALL [context]->write(0);
782	in_NB_INST_COMMIT_ALL [context]->write(0);
783	in_NB_INST_COMMIT_MEM [context]->write(0);
784
785	SC_START(1);
786
787	LABEL("exception (wait event)");
788
789	bool find = false;
790	do
791	{
792	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
793
794	SC_START(0);
795
796	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
797	{
798	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
799	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
800	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
801	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
802
803	find = true;
804	}
805
806	SC_START(1);
807	}
808	while (not find);
809
810	in_EVENT_ACK [context]->write(0);
811
812	LABEL("exception (wait spr)");
813
814	find = false;
815	do
816	{
817	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
818
819	SC_START(0);
820
821	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
822	{
823	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
824	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
825	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
826	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
827	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
828
829	find = true;
830	}
831
832	SC_START(1);
833	}
834	while (not find);
835
836	in_SPR_EVENT_ACK [context]->write(0);
837	}
838
839	if (1)
840	{
841	SC_START(3);
842
843	LABEL("exception (begin)");
844	in_NB_INST_DECOD_ALL [context]->write(1);
845	in_NB_INST_COMMIT_ALL [context]->write(1);
846	in_NB_INST_COMMIT_MEM [context]->write(1);
847
848	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
849	if (_param->_have_port_depth)
850	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
851	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
852	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
853	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
854	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
855	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
856	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
857
858	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
859
860	do
861	{
862	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
863
864	SC_START(1);
865	}
866	while (not ( in_COMMIT_EVENT_VAL ->read() and
867	out_COMMIT_EVENT_ACK ->read()));
868	in_COMMIT_EVENT_VAL ->write(0);
869
870	LABEL("exception (wait end)");
871	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
872
873	SC_START(3);
874
875	in_NB_INST_DECOD_ALL [context]->write(0);
876	in_NB_INST_COMMIT_ALL [context]->write(0);
877	in_NB_INST_COMMIT_MEM [context]->write(0);
878
879	SC_START(1);
880
881	LABEL("exception (wait event)");
882
883	bool find = false;
884	do
885	{
886	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
887
888	SC_START(0);
889
890	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
891	{
892	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
893	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
894	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
895	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
896
897	find = true;
898	}
899
900	SC_START(1);
901	}
902	while (not find);
903
904	in_EVENT_ACK [context]->write(0);
905
906	LABEL("exception (wait spr)");
907
908	find = false;
909	do
910	{
911	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
912
913	SC_START(0);
914
915	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
916	{
917	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
918	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
919	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
920	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
921	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
922
923	find = true;
924	}
925
926	SC_START(1);
927	}
928	while (not find);
929
930	in_SPR_EVENT_ACK [context]->write(0);
931	}
932
933	if (1)
934	{
935	SC_START(3);
936
937	LABEL("exception (begin)");
938	in_NB_INST_DECOD_ALL [context]->write(1);
939	in_NB_INST_COMMIT_ALL [context]->write(1);
940	in_NB_INST_COMMIT_MEM [context]->write(1);
941
942	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
943	if (_param->_have_port_depth)
944	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
945	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
946	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
947	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
948	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
949	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
950	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
951
952	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
953
954	do
955	{
956	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
957
958	SC_START(1);
959	}
960	while (not ( in_COMMIT_EVENT_VAL ->read() and
961	out_COMMIT_EVENT_ACK ->read()));
962	in_COMMIT_EVENT_VAL ->write(0);
963
964	LABEL("exception (wait end)");
965	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
966
967	SC_START(3);
968
969	in_NB_INST_DECOD_ALL [context]->write(0);
970	in_NB_INST_COMMIT_ALL [context]->write(0);
971	in_NB_INST_COMMIT_MEM [context]->write(0);
972
973	SC_START(1);
974
975	LABEL("exception (wait event)");
976
977	bool find = false;
978	do
979	{
980	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
981
982	SC_START(0);
983
984	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
985	{
986	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
987	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
988	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
989	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
990
991	find = true;
992	}
993
994	SC_START(1);
995	}
996	while (not find);
997
998	in_EVENT_ACK [context]->write(0);
999
1000	LABEL("exception (wait spr)");
1001
1002	find = false;
1003	do
1004	{
1005	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1006
1007	SC_START(0);
1008
1009	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1010	{
1011	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1012	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1013	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
1014	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1015	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1016
1017	find = true;
1018	}
1019
1020	SC_START(1);
1021	}
1022	while (not find);
1023
1024	in_SPR_EVENT_ACK [context]->write(0);
1025	}
1026
1027	if (1)
1028	{
1029	SC_START(3);
1030
1031	LABEL("exception (begin)");
1032	in_NB_INST_DECOD_ALL [context]->write(1);
1033	in_NB_INST_COMMIT_ALL [context]->write(1);
1034	in_NB_INST_COMMIT_MEM [context]->write(1);
1035
1036	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1037	if (_param->_have_port_depth)
1038	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1039	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1040	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
1041	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
1042	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
1043	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
1044	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1045
1046	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1047
1048	do
1049	{
1050	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1051
1052	SC_START(1);
1053	}
1054	while (not ( in_COMMIT_EVENT_VAL ->read() and
1055	out_COMMIT_EVENT_ACK ->read()));
1056	in_COMMIT_EVENT_VAL ->write(0);
1057
1058	LABEL("exception (wait end)");
1059	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1060
1061	SC_START(3);
1062
1063	in_NB_INST_DECOD_ALL [context]->write(0);
1064	in_NB_INST_COMMIT_ALL [context]->write(0);
1065	in_NB_INST_COMMIT_MEM [context]->write(0);
1066
1067	SC_START(1);
1068
1069	LABEL("exception (wait event)");
1070
1071	bool find = false;
1072	do
1073	{
1074	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1075
1076	SC_START(0);
1077
1078	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1079	{
1080	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
1081	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
1082	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1083	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1084
1085	find = true;
1086	}
1087
1088	SC_START(1);
1089	}
1090	while (not find);
1091
1092	in_EVENT_ACK [context]->write(0);
1093
1094	LABEL("exception (wait spr)");
1095
1096	find = false;
1097	do
1098	{
1099	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1100
1101	SC_START(0);
1102
1103	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1104	{
1105	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
1106	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
1107	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1108	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
1109	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1110
1111	find = true;
1112	}
1113
1114	SC_START(1);
1115	}
1116	while (not find);
1117
1118	in_SPR_EVENT_ACK [context]->write(0);
1119	}
1120
1121	if (1)
1122	{
1123	SC_START(3);
1124
1125	LABEL("exception (begin)");
1126	in_NB_INST_DECOD_ALL [context]->write(1);
1127	in_NB_INST_COMMIT_ALL [context]->write(1);
1128	in_NB_INST_COMMIT_MEM [context]->write(1);
1129
1130	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1131	if (_param->_have_port_depth)
1132	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1133	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1134	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
1135	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
1136	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
1137	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
1138	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1139
1140	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1141
1142	do
1143	{
1144	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1145
1146	SC_START(1);
1147	}
1148	while (not ( in_COMMIT_EVENT_VAL ->read() and
1149	out_COMMIT_EVENT_ACK ->read()));
1150	in_COMMIT_EVENT_VAL ->write(0);
1151
1152	LABEL("exception (wait end)");
1153	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1154
1155	SC_START(3);
1156
1157	in_NB_INST_DECOD_ALL [context]->write(0);
1158	in_NB_INST_COMMIT_ALL [context]->write(0);
1159	in_NB_INST_COMMIT_MEM [context]->write(0);
1160
1161	SC_START(1);
1162
1163	LABEL("exception (wait event)");
1164
1165	bool find = false;
1166	do
1167	{
1168	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1169
1170	SC_START(0);
1171
1172	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1173	{
1174	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1175	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1176	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1177	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1178
1179	find = true;
1180	}
1181
1182	SC_START(1);
1183	}
1184	while (not find);
1185
1186	in_EVENT_ACK [context]->write(0);
1187
1188	LABEL("exception (wait spr)");
1189
1190	find = false;
1191	do
1192	{
1193	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1194
1195	SC_START(0);
1196
1197	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1198	{
1199	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1200	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1201	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1202	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1203	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1204
1205	find = true;
1206	}
1207
1208	SC_START(1);
1209	}
1210	while (not find);
1211
1212	in_SPR_EVENT_ACK [context]->write(0);
1213	}
1214
1215
1216	SC_START(1);
1217	}
1218
1219
1220	/********************************************************
1221	* Simulation - End
1222	********************************************************/
1223
1224	TEST_OK ("End of Simulation");
1225	delete _time;
1226
1227	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
1228
1229	delete in_CLOCK;
1230	delete in_NRESET;
1231
1232	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_VAL ,_param->_nb_context);
1233	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context);
1234	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
1235	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
1236	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
1237	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
1238	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
1239	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
1240	DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
1241	DELETE1_SC_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
1242	DELETE1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
1243	DELETE1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
1244	DELETE1_SC_SIGNAL( in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
1245	DELETE1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
1246	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
1247	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
1248	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_VAL );
1249	DELETE_SC_SIGNAL (out_COMMIT_EVENT_ACK );
1250	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID );
1251	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH );
1252	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_TYPE );
1253	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT );
1254	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS );
1255	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR );
1256	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
1257	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR );
1258	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
1259	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
1260	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
1261	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
1262	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
1263	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
1264	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
1265	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
1266	DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context );
1267	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context );
1268	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context );
1269	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context );
1270	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context );
1271	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context );
1272	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
1273	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
1274	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context );
1275	DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context );
1276	DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context );
1277	DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context );
1278	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context );
1279	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
1280	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context );
1281	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
1282	DELETE1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
1283	DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context );
1284	DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context );
1285	DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context );
1286
1287	DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context );
1288	}
1289	#endif
1290
1291	delete _Context_State;
1292	#ifdef STATISTICS
1293	delete _parameters_statistics;
1294	#endif
1295	}

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