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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/src/test.cpp @ 98

Last change on this file since 98 was 98, checked in by rosiere, 16 years ago
1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...) 2) Change VHDL Execute_queue -> use Generic/Queue? 3) Complete document on VHDL generation 4) Add soc test
Property svn:keywords set to `Id`
File size: 51.0 KB

Line
1	/*
2	* $Id: test.cpp 98 2008-12-31 10:18:08Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_front_end::front_end::context_state::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	// _usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Context_State * _Context_State = new Context_State
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_VAL ," in_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
51	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,"out_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
52	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
53	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
54	//ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ," in_BRANCH_EVENT_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_context);
55	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ," in_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
56	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ," in_BRANCH_EVENT_ADDRESS_DEST_VAL ",Tcontrol_t ,_param->_nb_context);
57	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ," in_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
58
59	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_VAL ," in_DECOD_EVENT_VAL ",Tcontrol_t ,_param->_nb_decod_unit);
60	ALLOC1_SC_SIGNAL(out_DECOD_EVENT_ACK ,"out_DECOD_EVENT_ACK ",Tcontrol_t ,_param->_nb_decod_unit);
61	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ," in_DECOD_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_decod_unit);
62	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ," in_DECOD_EVENT_DEPTH ",Tdepth_t ,_param->_nb_decod_unit);
63	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_TYPE ," in_DECOD_EVENT_TYPE ",Tevent_type_t,_param->_nb_decod_unit);
64	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ," in_DECOD_EVENT_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_decod_unit);
65	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ," in_DECOD_EVENT_ADDRESS ",Taddress_t ,_param->_nb_decod_unit);
66	ALLOC1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ," in_DECOD_EVENT_ADDRESS_EPCR ",Taddress_t ,_param->_nb_decod_unit);
67
68	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_VAL ," in_COMMIT_EVENT_VAL ",Tcontrol_t );
69	ALLOC_SC_SIGNAL (out_COMMIT_EVENT_ACK ,"out_COMMIT_EVENT_ACK ",Tcontrol_t );
70	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID ," in_COMMIT_EVENT_CONTEXT_ID ",Tcontext_t );
71	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH ," in_COMMIT_EVENT_DEPTH ",Tdepth_t );
72	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_TYPE ," in_COMMIT_EVENT_TYPE ",Tevent_type_t);
73	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT ," in_COMMIT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
74	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS ," in_COMMIT_EVENT_ADDRESS ",Taddress_t );
75	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR ," in_COMMIT_EVENT_ADDRESS_EPCR ",Taddress_t );
76	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL ," in_COMMIT_EVENT_ADDRESS_EEAR_VAL ",Tcontrol_t );
77	ALLOC_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR ," in_COMMIT_EVENT_ADDRESS_EEAR ",Tgeneral_data_t);
78
79	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
80	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
81	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
82	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
83	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION," in_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
84	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ," in_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
85	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ," in_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
86	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ," in_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
87
88
89	ALLOC1_SC_SIGNAL( in_NB_INST_DECOD_ALL ," in_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context );
90	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ," in_NB_INST_COMMIT_ALL ",Tcounter_t ,_param->_nb_context );
91	ALLOC1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ," in_NB_INST_COMMIT_MEM ",Tcounter_t ,_param->_nb_context );
92
93	ALLOC1_SC_SIGNAL(out_EVENT_VAL ,"out_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
94	ALLOC1_SC_SIGNAL( in_EVENT_ACK ," in_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
95	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS ,"out_EVENT_ADDRESS ",Taddress_t ,_param->_nb_context );
96	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,"out_EVENT_ADDRESS_NEXT ",Taddress_t ,_param->_nb_context );
97	ALLOC1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,"out_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ,_param->_nb_context );
98	ALLOC1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,"out_EVENT_IS_DS_TAKE ",Tcontrol_t ,_param->_nb_context );
99	ALLOC1_SC_SIGNAL(out_EVENT_TYPE ,"out_EVENT_TYPE ",Tevent_type_t,_param->_nb_context );
100	ALLOC1_SC_SIGNAL(out_EVENT_DEPTH ,"out_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context );
101
102	ALLOC1_SC_SIGNAL(out_SPR_EVENT_VAL ,"out_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_context );
103	ALLOC1_SC_SIGNAL( in_SPR_EVENT_ACK ," in_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_context );
104	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EPCR ,"out_SPR_EVENT_EPCR ",Taddress_t ,_param->_nb_context );
105	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR ,"out_SPR_EVENT_EEAR ",Taddress_t ,_param->_nb_context );
106	ALLOC1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,"out_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_context );
107	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,"out_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_context );
108	ALLOC1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,"out_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_context );
109
110	ALLOC1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,"out_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context );
111
112	ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context );
113
114	ALLOC1_SC_SIGNAL( in_SPR_SR_IEE ," in_SPR_SR_IEE ",Tcontrol_t ,_param->_nb_context );
115	ALLOC1_SC_SIGNAL( in_SPR_SR_EPH ," in_SPR_SR_EPH ",Tcontrol_t ,_param->_nb_context );
116
117	ALLOC1_SC_SIGNAL( in_INTERRUPT_ENABLE ," in_INTERRUPT_ENABLE ",Tcontrol_t ,_param->_nb_context );
118
119	/********************************************************
120	* Instanciation
121	********************************************************/
122
123	msg(_("<%s> : Instanciation of _Context_State.\n"),name.c_str());
124
125	((_Context_State->in_CLOCK)) ((in_CLOCK));
126	((_Context_State->in_NRESET)) ((in_NRESET));
127
128	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_VAL ,_param->_nb_context);
129	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_EVENT_ACK ,_param->_nb_context);
130	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
131	if (_param->_have_port_depth)
132	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
133	//INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
134	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
135	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
136	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
137	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
138	INSTANCE1_SC_SIGNAL(_Context_State,out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
139	if (_param->_have_port_context_id)
140	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
141	if (_param->_have_port_depth)
142	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
143	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
144	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
145	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
146	INSTANCE1_SC_SIGNAL(_Context_State, in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
147
148	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_VAL );
149	INSTANCE_SC_SIGNAL (_Context_State,out_COMMIT_EVENT_ACK );
150	if (_param->_have_port_context_id)
151	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_CONTEXT_ID );
152	if (_param->_have_port_depth)
153	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_DEPTH );
154	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_TYPE );
155	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_IS_DELAY_SLOT );
156	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS );
157	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EPCR );
158	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
159	INSTANCE_SC_SIGNAL (_Context_State, in_COMMIT_EVENT_ADDRESS_EEAR );
160
161	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
162	INSTANCE1_SC_SIGNAL(_Context_State,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
163	if (_param->_have_port_context_id)
164	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
165	if (_param->_have_port_depth)
166	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
167	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
168	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
169	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
170	INSTANCE1_SC_SIGNAL(_Context_State, in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
171
172	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_DECOD_ALL ,_param->_nb_context );
173	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_ALL ,_param->_nb_context );
174	INSTANCE1_SC_SIGNAL(_Context_State, in_NB_INST_COMMIT_MEM ,_param->_nb_context );
175
176	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_VAL ,_param->_nb_context );
177	INSTANCE1_SC_SIGNAL(_Context_State, in_EVENT_ACK ,_param->_nb_context );
178	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS ,_param->_nb_context );
179	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
180	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
181	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_IS_DS_TAKE ,_param->_nb_context );
182	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_TYPE ,_param->_nb_context );
183	if (_param->_have_port_depth)
184	INSTANCE1_SC_SIGNAL(_Context_State,out_EVENT_DEPTH ,_param->_nb_context );
185
186	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_VAL ,_param->_nb_context );
187	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_EVENT_ACK ,_param->_nb_context );
188	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EPCR ,_param->_nb_context );
189	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR ,_param->_nb_context );
190	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
191	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_DSX ,_param->_nb_context );
192	INSTANCE1_SC_SIGNAL(_Context_State,out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
193
194	INSTANCE1_SC_SIGNAL(_Context_State,out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
195
196	for (uint32_t i=0; i<_param->_nb_context; i++)
197	if (_param->_have_port_depth)
198	INSTANCE_SC_SIGNAL(_Context_State, in_DEPTH_MIN [i]);
199
200	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_IEE ,_param->_nb_context );
201	INSTANCE1_SC_SIGNAL(_Context_State, in_SPR_SR_EPH ,_param->_nb_context );
202
203	INSTANCE1_SC_SIGNAL(_Context_State, in_INTERRUPT_ENABLE ,_param->_nb_context );
204
205	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
206
207	Time * _time = new Time();
208
209	/********************************************************
210	* Simulation - Begin
211	********************************************************/
212
213	// Initialisation
214
215	const uint32_t seed = 0;
216	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
217
218	srand(seed);
219
220	const int32_t percent_transaction_branch_event = 75;
221	const int32_t percent_transaction_decod_event = 75;
222	const int32_t percent_transaction_commit_event = 75;
223	//const int32_t percent_transaction_branch_complete = 75;
224	const int32_t percent_transaction_event = 75;
225	const int32_t percent_transaction_spr = 75;
226
227	SC_START(0);
228	LABEL("Initialisation");
229
230	LABEL("Reset");
231	in_NRESET->write(0);
232	SC_START(5);
233	in_NRESET->write(1);
234
235	LABEL("Loop of Test");
236
237	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
238	{
239	LABEL("Iteration %d",iteration);
240	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
241	in_DECOD_EVENT_VAL [i]->write(0);
242	in_COMMIT_EVENT_VAL ->write(0);
243	// for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
244	// in_BRANCH_COMPLETE_VAL [i]->write(0);
245	for (uint32_t i=0; i<_param->_nb_context; i++)
246	in_BRANCH_EVENT_VAL [i]->write(0);
247
248	for (uint32_t i=0; i<_param->_nb_context; i++)
249	{
250	in_BRANCH_EVENT_VAL [i]->write(0);
251	in_EVENT_ACK [i]->write(0);
252	in_SPR_EVENT_ACK [i]->write(0);
253	in_SPR_SR_IEE [i]->write(0);
254	in_SPR_SR_EPH [i]->write(0);
255	in_INTERRUPT_ENABLE [i]->write(0);
256
257	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[i]->read(), 1);
258	}
259
260	for (uint32_t i=0; i<_param->_nb_context; i++)
261	if (_param->_have_port_depth)
262	in_DEPTH_MIN [i]->write((_param->_array_size_depth[i]==0)?0:(i%_param->_array_size_depth[i]));
263
264	uint32_t context = rand()%_param->_nb_context;
265
266	if (1)
267	{
268	SC_START(3);
269
270	LABEL("msync (begin)");
271	in_NB_INST_DECOD_ALL [context]->write(1);
272	in_NB_INST_COMMIT_ALL [context]->write(1);
273	in_NB_INST_COMMIT_MEM [context]->write(1);
274
275	uint32_t port = rand()%_param->_nb_decod_unit;
276
277	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
278	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
279	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
280	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
281	if (_param->_have_port_depth)
282	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
283	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_MSYNC);
284
285	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
286
287	do
288	{
289	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
290
291	SC_START(1);
292	}
293	while (not ( in_DECOD_EVENT_VAL [port]->read() and
294	out_DECOD_EVENT_ACK [port]->read()));
295	in_DECOD_EVENT_VAL [port]->write(0);
296
297	LABEL("msync (wait end)");
298	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
299
300	SC_START(3);
301
302	in_NB_INST_DECOD_ALL [context]->write(0);
303	in_NB_INST_COMMIT_ALL [context]->write(1);
304	in_NB_INST_COMMIT_MEM [context]->write(0);
305
306	SC_START(1);
307
308	LABEL("msync (send decod)");
309	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
310
311	SC_START(3);
312
313	in_NB_INST_DECOD_ALL [context]->write(1);
314	SC_START(1);
315
316	LABEL("msync (wait end)");
317	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
318	in_NB_INST_DECOD_ALL [context]->write(0);
319	in_NB_INST_COMMIT_MEM [context]->write(1);
320
321	SC_START(3);
322
323	in_NB_INST_COMMIT_MEM [context]->write(0);
324	SC_START(1);
325	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
326	}
327
328	if (1)
329	{
330	SC_START(3);
331
332	LABEL("psync (begin)");
333	in_NB_INST_DECOD_ALL [context]->write(1);
334	in_NB_INST_COMMIT_ALL [context]->write(1);
335	in_NB_INST_COMMIT_MEM [context]->write(1);
336
337	uint32_t port = rand()%_param->_nb_decod_unit;
338
339	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
340	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
341	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
342	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
343	if (_param->_have_port_depth)
344	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
345	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_PSYNC);
346
347	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
348
349	do
350	{
351	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
352
353	SC_START(1);
354	}
355	while (not ( in_DECOD_EVENT_VAL [port]->read() and
356	out_DECOD_EVENT_ACK [port]->read()));
357	in_DECOD_EVENT_VAL [port]->write(0);
358
359	LABEL("psync (wait end)");
360	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
361
362	SC_START(3);
363
364	in_NB_INST_DECOD_ALL [context]->write(0);
365	in_NB_INST_COMMIT_ALL [context]->write(0);
366	in_NB_INST_COMMIT_MEM [context]->write(0);
367
368	SC_START(1);
369
370	bool find = false;
371	do
372	{
373	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
374
375	SC_START(0);
376
377	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
378	{
379	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
380	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
381	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
382	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
383
384	find = true;
385	}
386
387	SC_START(1);
388	}
389	while (not find);
390
391	in_EVENT_ACK [context]->write(0);
392	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
393	}
394
395	if (1)
396	{
397	SC_START(3);
398
399	LABEL("csync (begin)");
400	in_NB_INST_DECOD_ALL [context]->write(1);
401	in_NB_INST_COMMIT_ALL [context]->write(1);
402	in_NB_INST_COMMIT_MEM [context]->write(1);
403
404	uint32_t port = rand()%_param->_nb_decod_unit;
405
406	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
407	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
408	in_DECOD_EVENT_ADDRESS [port]->write(0x200);
409	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbebe);
410	if (_param->_have_port_depth)
411	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
412	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_CSYNC);
413
414	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
415
416	do
417	{
418	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
419
420	SC_START(1);
421	}
422	while (not ( in_DECOD_EVENT_VAL [port]->read() and
423	out_DECOD_EVENT_ACK [port]->read()));
424	in_DECOD_EVENT_VAL [port]->write(0);
425
426	LABEL("csync (wait end)");
427	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
428
429	SC_START(3);
430
431	in_NB_INST_DECOD_ALL [context]->write(0);
432	in_NB_INST_COMMIT_ALL [context]->write(0);
433	in_NB_INST_COMMIT_MEM [context]->write(0);
434
435	SC_START(1);
436
437	bool find = false;
438	do
439	{
440	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
441
442	SC_START(0);
443
444	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
445	{
446	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x201);
447	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xdeadbebe);
448	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
449	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
450
451	find = true;
452	}
453
454	SC_START(1);
455	}
456	while (not find);
457	in_EVENT_ACK [context]->write(0);
458	}
459
460	if (1)
461	{
462	SC_START(3);
463
464	LABEL("spr (begin)");
465	in_NB_INST_DECOD_ALL [context]->write(1);
466	in_NB_INST_COMMIT_ALL [context]->write(1);
467	in_NB_INST_COMMIT_MEM [context]->write(1);
468
469	uint32_t port = rand()%_param->_nb_decod_unit;
470
471	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
472	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
473	in_DECOD_EVENT_ADDRESS [port]->write(0x100);
474	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0xdeadbeef);
475	if (_param->_have_port_depth)
476	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
477	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_SPR_ACCESS);
478
479	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
480
481	do
482	{
483	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
484
485	SC_START(1);
486	}
487	while (not ( in_DECOD_EVENT_VAL [port]->read() and
488	out_DECOD_EVENT_ACK [port]->read()));
489	in_DECOD_EVENT_VAL [port]->write(0);
490
491	LABEL("spr (wait end)");
492	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
493
494	SC_START(3);
495
496	in_NB_INST_DECOD_ALL [context]->write(0);
497	in_NB_INST_COMMIT_ALL [context]->write(0);
498	in_NB_INST_COMMIT_MEM [context]->write(0);
499
500	SC_START(1);
501
502	LABEL("spr (send decod)");
503	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
504
505	SC_START(3);
506
507	in_NB_INST_DECOD_ALL [context]->write(1);
508	SC_START(1);
509
510	LABEL("spr (wait end)");
511	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
512	in_NB_INST_DECOD_ALL [context]->write(0);
513	in_NB_INST_COMMIT_ALL [context]->write(1);
514
515	SC_START(3);
516
517	in_NB_INST_COMMIT_ALL [context]->write(0);
518	SC_START(1);
519	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
520	}
521
522	if (1)
523	{
524	SC_START(3);
525
526	LABEL("miss (begin)");
527	in_NB_INST_DECOD_ALL [context]->write(1);
528	in_NB_INST_COMMIT_ALL [context]->write(1);
529	in_NB_INST_COMMIT_MEM [context]->write(1);
530
531	// uint32_t port = rand()%_param->_nb_inst_branch_complete;
532
533	// in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
534	// if (_param->_have_port_depth)
535	// in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
536	// in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x400);
537	// in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x500);
538	// in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
539	// in_BRANCH_COMPLETE_TAKE [port]->write(0);
540
541	// TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
542
543	// do
544	// {
545	// in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
546
547	// SC_START(1);
548	// }
549	// while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
550	// out_BRANCH_COMPLETE_ACK [port]->read()));
551	// in_BRANCH_COMPLETE_VAL [port]->write(0);
552
553	uint32_t port = context;
554
555	if (_param->_have_port_depth)
556	in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
557	in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x400);
558	in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x500);
559	in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(0);
560
561	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
562
563	do
564	{
565	in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event);
566
567	SC_START(1);
568	}
569	while (not ( in_BRANCH_EVENT_VAL [port]->read() and
570	out_BRANCH_EVENT_ACK [port]->read()));
571	in_BRANCH_EVENT_VAL [port]->write(0);
572
573	LABEL("miss (wait end)");
574	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
575
576	SC_START(3);
577
578	in_NB_INST_DECOD_ALL [context]->write(0);
579	in_NB_INST_COMMIT_ALL [context]->write(0);
580	in_NB_INST_COMMIT_MEM [context]->write(0);
581
582	SC_START(1);
583
584	LABEL("miss (wait event)");
585
586
587	bool find = false;
588	do
589	{
590	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
591
592	SC_START(0);
593
594	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
595	{
596	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x401);
597	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x500);
598	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
599	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
600
601	find = true;
602	}
603
604	SC_START(1);
605	}
606	while (not find);
607
608	in_EVENT_ACK [context]->write(0);
609
610	}
611
612	if (1)
613	{
614	SC_START(3);
615
616	LABEL("miss (begin)");
617	in_NB_INST_DECOD_ALL [context]->write(1);
618	in_NB_INST_COMMIT_ALL [context]->write(1);
619	in_NB_INST_COMMIT_MEM [context]->write(1);
620
621	// uint32_t port = rand()%_param->_nb_inst_branch_complete;
622
623	// in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(context);
624	// if (_param->_have_port_depth)
625	// in_BRANCH_COMPLETE_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
626	// in_BRANCH_COMPLETE_ADDRESS_SRC [port]->write(0x600);
627	// in_BRANCH_COMPLETE_ADDRESS_DEST [port]->write(0x700);
628	// in_BRANCH_COMPLETE_MISS_PREDICTION [port]->write(1);
629	// in_BRANCH_COMPLETE_TAKE [port]->write(1);
630
631	// TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
632
633	// do
634	// {
635	// in_BRANCH_COMPLETE_VAL [port]->write(rand()%percent_transaction_branch_complete);
636
637	// SC_START(1);
638	// }
639	// while (not ( in_BRANCH_COMPLETE_VAL [port]->read() and
640	// out_BRANCH_COMPLETE_ACK [port]->read()));
641	// in_BRANCH_COMPLETE_VAL [port]->write(0);
642
643	uint32_t port = context;
644
645	in_BRANCH_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context+1)%_param->_array_size_depth[context]));
646	in_BRANCH_EVENT_ADDRESS_SRC [port]->write(0x600);
647	in_BRANCH_EVENT_ADDRESS_DEST [port]->write(0x700);
648	in_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->write(1);
649
650	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
651
652	do
653	{
654	in_BRANCH_EVENT_VAL [port]->write(rand()%percent_transaction_branch_event);
655
656	SC_START(1);
657	}
658	while (not ( in_BRANCH_EVENT_VAL [port]->read() and
659	out_BRANCH_EVENT_ACK [port]->read()));
660	in_BRANCH_EVENT_VAL [port]->write(0);
661
662	LABEL("miss (wait end)");
663	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
664
665	SC_START(3);
666
667	in_NB_INST_DECOD_ALL [context]->write(0);
668	in_NB_INST_COMMIT_ALL [context]->write(0);
669	in_NB_INST_COMMIT_MEM [context]->write(0);
670
671	SC_START(1);
672
673	LABEL("miss (wait event)");
674
675	bool find = false;
676	do
677	{
678	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
679
680	SC_START(0);
681
682	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
683	{
684	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x601);
685	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x700);
686	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),1);
687	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),1);
688
689	find = true;
690	}
691
692	SC_START(1);
693	}
694	while (not find);
695
696	in_EVENT_ACK [context]->write(0);
697	}
698
699	if (1)
700	{
701	SC_START(3);
702
703	LABEL("exception (begin)");
704	in_NB_INST_DECOD_ALL [context]->write(1);
705	in_NB_INST_COMMIT_ALL [context]->write(1);
706	in_NB_INST_COMMIT_MEM [context]->write(1);
707
708	uint32_t port = rand()%_param->_nb_decod_unit;
709
710	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
711	if (_param->_have_port_depth)
712	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
713	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
714	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(0);
715	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
716	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
717
718	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
719
720	do
721	{
722	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
723
724	SC_START(1);
725	}
726	while (not ( in_DECOD_EVENT_VAL [port]->read() and
727	out_DECOD_EVENT_ACK [port]->read()));
728	in_DECOD_EVENT_VAL [port]->write(0);
729
730	LABEL("exception (wait end)");
731	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
732
733	SC_START(3);
734
735	in_NB_INST_DECOD_ALL [context]->write(0);
736	in_NB_INST_COMMIT_ALL [context]->write(0);
737	in_NB_INST_COMMIT_MEM [context]->write(0);
738
739	SC_START(1);
740
741	LABEL("exception (wait event)");
742
743	bool find = false;
744	do
745	{
746	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
747
748	SC_START(0);
749
750	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
751	{
752	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
753	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
754	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
755	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
756
757	find = true;
758	}
759
760	SC_START(1);
761	}
762	while (not find);
763
764	in_EVENT_ACK [context]->write(0);
765
766	LABEL("exception (wait spr)");
767
768	find = false;
769	do
770	{
771	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
772
773	SC_START(0);
774
775	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
776	{
777	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
778	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
779	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
780	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
781	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
782
783	find = true;
784	}
785
786	SC_START(1);
787	}
788	while (not find);
789
790	in_SPR_EVENT_ACK [context]->write(0);
791	}
792
793	if (1)
794	{
795	SC_START(3);
796
797	LABEL("exception (begin)");
798	in_NB_INST_DECOD_ALL [context]->write(1);
799	in_NB_INST_COMMIT_ALL [context]->write(1);
800	in_NB_INST_COMMIT_MEM [context]->write(1);
801
802	uint32_t port = rand()%_param->_nb_decod_unit;
803
804	in_DECOD_EVENT_CONTEXT_ID [port]->write(context);
805	if (_param->_have_port_depth)
806	in_DECOD_EVENT_DEPTH [port]->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
807	in_DECOD_EVENT_TYPE [port]->write(EVENT_TYPE_EXCEPTION);
808	in_DECOD_EVENT_IS_DELAY_SLOT [port]->write(1);
809	in_DECOD_EVENT_ADDRESS [port]->write(0x800);
810	in_DECOD_EVENT_ADDRESS_EPCR [port]->write(0x900);
811
812	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
813
814	do
815	{
816	in_DECOD_EVENT_VAL [port]->write(rand()%percent_transaction_decod_event);
817
818	SC_START(1);
819	}
820	while (not ( in_DECOD_EVENT_VAL [port]->read() and
821	out_DECOD_EVENT_ACK [port]->read()));
822	in_DECOD_EVENT_VAL [port]->write(0);
823
824	LABEL("exception (wait end)");
825	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
826
827	SC_START(3);
828
829	in_NB_INST_DECOD_ALL [context]->write(0);
830	in_NB_INST_COMMIT_ALL [context]->write(0);
831	in_NB_INST_COMMIT_MEM [context]->write(0);
832
833	SC_START(1);
834
835	LABEL("exception (wait event)");
836
837	bool find = false;
838	do
839	{
840	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
841
842	SC_START(0);
843
844	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
845	{
846	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0x800);
847	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0x900);
848	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
849	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
850
851	find = true;
852	}
853
854	SC_START(1);
855	}
856	while (not find);
857
858	in_EVENT_ACK [context]->write(0);
859
860	LABEL("exception (wait spr)");
861
862	find = false;
863	do
864	{
865	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
866
867	SC_START(0);
868
869	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
870	{
871	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0x900);
872	//TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),);
873	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
874	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
875	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
876
877	find = true;
878	}
879
880	SC_START(1);
881	}
882	while (not find);
883
884	in_SPR_EVENT_ACK [context]->write(0);
885	}
886
887	if (1)
888	{
889	SC_START(3);
890
891	LABEL("exception (begin)");
892	in_NB_INST_DECOD_ALL [context]->write(1);
893	in_NB_INST_COMMIT_ALL [context]->write(1);
894	in_NB_INST_COMMIT_MEM [context]->write(1);
895
896	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
897	if (_param->_have_port_depth)
898	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
899	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
900	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
901	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
902	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
903	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
904	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
905
906	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
907
908	do
909	{
910	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
911
912	SC_START(1);
913	}
914	while (not ( in_COMMIT_EVENT_VAL ->read() and
915	out_COMMIT_EVENT_ACK ->read()));
916	in_COMMIT_EVENT_VAL ->write(0);
917
918	LABEL("exception (wait end)");
919	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
920
921	SC_START(3);
922
923	in_NB_INST_DECOD_ALL [context]->write(0);
924	in_NB_INST_COMMIT_ALL [context]->write(0);
925	in_NB_INST_COMMIT_MEM [context]->write(0);
926
927	SC_START(1);
928
929	LABEL("exception (wait event)");
930
931	bool find = false;
932	do
933	{
934	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
935
936	SC_START(0);
937
938	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
939	{
940	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
941	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
942	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
943	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
944
945	find = true;
946	}
947
948	SC_START(1);
949	}
950	while (not find);
951
952	in_EVENT_ACK [context]->write(0);
953
954	LABEL("exception (wait spr)");
955
956	find = false;
957	do
958	{
959	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
960
961	SC_START(0);
962
963	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
964	{
965	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
966	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
967	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
968	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
969	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
970
971	find = true;
972	}
973
974	SC_START(1);
975	}
976	while (not find);
977
978	in_SPR_EVENT_ACK [context]->write(0);
979	}
980
981	if (1)
982	{
983	SC_START(3);
984
985	LABEL("exception (begin)");
986	in_NB_INST_DECOD_ALL [context]->write(1);
987	in_NB_INST_COMMIT_ALL [context]->write(1);
988	in_NB_INST_COMMIT_MEM [context]->write(1);
989
990	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
991	if (_param->_have_port_depth)
992	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
993	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
994	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
995	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
996	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
997	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
998	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(0);
999
1000	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1001
1002	do
1003	{
1004	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1005
1006	SC_START(1);
1007	}
1008	while (not ( in_COMMIT_EVENT_VAL ->read() and
1009	out_COMMIT_EVENT_ACK ->read()));
1010	in_COMMIT_EVENT_VAL ->write(0);
1011
1012	LABEL("exception (wait end)");
1013	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1014
1015	SC_START(3);
1016
1017	in_NB_INST_DECOD_ALL [context]->write(0);
1018	in_NB_INST_COMMIT_ALL [context]->write(0);
1019	in_NB_INST_COMMIT_MEM [context]->write(0);
1020
1021	SC_START(1);
1022
1023	LABEL("exception (wait event)");
1024
1025	bool find = false;
1026	do
1027	{
1028	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1029
1030	SC_START(0);
1031
1032	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1033	{
1034	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1035	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1036	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1037	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1038
1039	find = true;
1040	}
1041
1042	SC_START(1);
1043	}
1044	while (not find);
1045
1046	in_EVENT_ACK [context]->write(0);
1047
1048	LABEL("exception (wait spr)");
1049
1050	find = false;
1051	do
1052	{
1053	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1054
1055	SC_START(0);
1056
1057	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1058	{
1059	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1060	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1061	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),0);
1062	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1063	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1064
1065	find = true;
1066	}
1067
1068	SC_START(1);
1069	}
1070	while (not find);
1071
1072	in_SPR_EVENT_ACK [context]->write(0);
1073	}
1074
1075	if (1)
1076	{
1077	SC_START(3);
1078
1079	LABEL("exception (begin)");
1080	in_NB_INST_DECOD_ALL [context]->write(1);
1081	in_NB_INST_COMMIT_ALL [context]->write(1);
1082	in_NB_INST_COMMIT_MEM [context]->write(1);
1083
1084	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1085	if (_param->_have_port_depth)
1086	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1087	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1088	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(0);
1089	in_COMMIT_EVENT_ADDRESS ->write(0xa00);
1090	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xb00);
1091	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xc00);
1092	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1093
1094	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1095
1096	do
1097	{
1098	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1099
1100	SC_START(1);
1101	}
1102	while (not ( in_COMMIT_EVENT_VAL ->read() and
1103	out_COMMIT_EVENT_ACK ->read()));
1104	in_COMMIT_EVENT_VAL ->write(0);
1105
1106	LABEL("exception (wait end)");
1107	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1108
1109	SC_START(3);
1110
1111	in_NB_INST_DECOD_ALL [context]->write(0);
1112	in_NB_INST_COMMIT_ALL [context]->write(0);
1113	in_NB_INST_COMMIT_MEM [context]->write(0);
1114
1115	SC_START(1);
1116
1117	LABEL("exception (wait event)");
1118
1119	bool find = false;
1120	do
1121	{
1122	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1123
1124	SC_START(0);
1125
1126	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1127	{
1128	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xa00);
1129	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xb00);
1130	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1131	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1132
1133	find = true;
1134	}
1135
1136	SC_START(1);
1137	}
1138	while (not find);
1139
1140	in_EVENT_ACK [context]->write(0);
1141
1142	LABEL("exception (wait spr)");
1143
1144	find = false;
1145	do
1146	{
1147	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1148
1149	SC_START(0);
1150
1151	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1152	{
1153	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xb00);
1154	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xc00);
1155	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1156	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),0);
1157	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1158
1159	find = true;
1160	}
1161
1162	SC_START(1);
1163	}
1164	while (not find);
1165
1166	in_SPR_EVENT_ACK [context]->write(0);
1167	}
1168
1169	if (1)
1170	{
1171	SC_START(3);
1172
1173	LABEL("exception (begin)");
1174	in_NB_INST_DECOD_ALL [context]->write(1);
1175	in_NB_INST_COMMIT_ALL [context]->write(1);
1176	in_NB_INST_COMMIT_MEM [context]->write(1);
1177
1178	in_COMMIT_EVENT_CONTEXT_ID ->write(context);
1179	if (_param->_have_port_depth)
1180	in_COMMIT_EVENT_DEPTH ->write((_param->_array_size_depth[context]==0)?0:((context)%_param->_array_size_depth[context]));
1181	in_COMMIT_EVENT_TYPE ->write(EVENT_TYPE_EXCEPTION);
1182	in_COMMIT_EVENT_IS_DELAY_SLOT ->write(1);
1183	in_COMMIT_EVENT_ADDRESS ->write(0xd00);
1184	in_COMMIT_EVENT_ADDRESS_EPCR ->write(0xe00);
1185	in_COMMIT_EVENT_ADDRESS_EEAR ->write(0xf00);
1186	in_COMMIT_EVENT_ADDRESS_EEAR_VAL ->write(1);
1187
1188	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 1);
1189
1190	do
1191	{
1192	in_COMMIT_EVENT_VAL ->write(rand()%percent_transaction_commit_event);
1193
1194	SC_START(1);
1195	}
1196	while (not ( in_COMMIT_EVENT_VAL ->read() and
1197	out_COMMIT_EVENT_ACK ->read()));
1198	in_COMMIT_EVENT_VAL ->write(0);
1199
1200	LABEL("exception (wait end)");
1201	TEST(Tcontrol_t, out_CONTEXT_DECOD_ENABLE[context]->read(), 0);
1202
1203	SC_START(3);
1204
1205	in_NB_INST_DECOD_ALL [context]->write(0);
1206	in_NB_INST_COMMIT_ALL [context]->write(0);
1207	in_NB_INST_COMMIT_MEM [context]->write(0);
1208
1209	SC_START(1);
1210
1211	LABEL("exception (wait event)");
1212
1213	bool find = false;
1214	do
1215	{
1216	in_EVENT_ACK [context]->write(rand()%percent_transaction_event);
1217
1218	SC_START(0);
1219
1220	if (out_EVENT_VAL [context]->read() and in_EVENT_ACK [context]->read())
1221	{
1222	TEST(Taddress_t,out_EVENT_ADDRESS [context]->read(),0xd00);
1223	TEST(Taddress_t,out_EVENT_ADDRESS_NEXT [context]->read(),0xe00);
1224	TEST(Tcontrol_t,out_EVENT_ADDRESS_NEXT_VAL [context]->read(),0);
1225	TEST(Tcontrol_t,out_EVENT_IS_DS_TAKE [context]->read(),0);
1226
1227	find = true;
1228	}
1229
1230	SC_START(1);
1231	}
1232	while (not find);
1233
1234	in_EVENT_ACK [context]->write(0);
1235
1236	LABEL("exception (wait spr)");
1237
1238	find = false;
1239	do
1240	{
1241	in_SPR_EVENT_ACK [context]->write(rand()%percent_transaction_spr);
1242
1243	SC_START(0);
1244
1245	if (out_SPR_EVENT_VAL [context]->read() and in_SPR_EVENT_ACK [context]->read())
1246	{
1247	TEST(Taddress_t,out_SPR_EVENT_EPCR [context]->read(),0xe00);
1248	TEST(Taddress_t,out_SPR_EVENT_EEAR [context]->read(),0xf00);
1249	TEST(Tcontrol_t,out_SPR_EVENT_EEAR_WEN [context]->read(),1);
1250	TEST(Tcontrol_t,out_SPR_EVENT_SR_DSX [context]->read(),1);
1251	TEST(Tcontrol_t,out_SPR_EVENT_SR_TO_ESR [context]->read(),1);
1252
1253	find = true;
1254	}
1255
1256	SC_START(1);
1257	}
1258	while (not find);
1259
1260	in_SPR_EVENT_ACK [context]->write(0);
1261	}
1262
1263
1264	SC_START(1);
1265	}
1266
1267
1268	/********************************************************
1269	* Simulation - End
1270	********************************************************/
1271
1272	TEST_OK ("End of Simulation");
1273	delete _time;
1274
1275	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
1276
1277	delete in_CLOCK;
1278	delete in_NRESET;
1279
1280	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_VAL ,_param->_nb_context);
1281	DELETE1_SC_SIGNAL(out_BRANCH_EVENT_ACK ,_param->_nb_context);
1282	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
1283	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
1284	//DELETE1_SC_SIGNAL( in_BRANCH_EVENT_MISS_PREDICTION ,_param->_nb_context);
1285	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
1286	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST_VAL ,_param->_nb_context);
1287	DELETE1_SC_SIGNAL( in_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
1288	DELETE1_SC_SIGNAL( in_DECOD_EVENT_VAL ,_param->_nb_decod_unit);
1289	DELETE1_SC_SIGNAL(out_DECOD_EVENT_ACK ,_param->_nb_decod_unit);
1290	DELETE1_SC_SIGNAL( in_DECOD_EVENT_CONTEXT_ID ,_param->_nb_decod_unit);
1291	DELETE1_SC_SIGNAL( in_DECOD_EVENT_DEPTH ,_param->_nb_decod_unit);
1292	DELETE1_SC_SIGNAL( in_DECOD_EVENT_TYPE ,_param->_nb_decod_unit);
1293	DELETE1_SC_SIGNAL( in_DECOD_EVENT_IS_DELAY_SLOT ,_param->_nb_decod_unit);
1294	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS ,_param->_nb_decod_unit);
1295	DELETE1_SC_SIGNAL( in_DECOD_EVENT_ADDRESS_EPCR ,_param->_nb_decod_unit);
1296	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_VAL );
1297	DELETE_SC_SIGNAL (out_COMMIT_EVENT_ACK );
1298	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_CONTEXT_ID );
1299	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_DEPTH );
1300	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_TYPE );
1301	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_IS_DELAY_SLOT );
1302	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS );
1303	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EPCR );
1304	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
1305	DELETE_SC_SIGNAL ( in_COMMIT_EVENT_ADDRESS_EEAR );
1306	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
1307	DELETE1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
1308	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
1309	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
1310	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
1311	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
1312	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
1313	DELETE1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
1314	DELETE1_SC_SIGNAL( in_NB_INST_DECOD_ALL ,_param->_nb_context );
1315	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_ALL ,_param->_nb_context );
1316	DELETE1_SC_SIGNAL( in_NB_INST_COMMIT_MEM ,_param->_nb_context );
1317	DELETE1_SC_SIGNAL(out_EVENT_VAL ,_param->_nb_context );
1318	DELETE1_SC_SIGNAL( in_EVENT_ACK ,_param->_nb_context );
1319	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS ,_param->_nb_context );
1320	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT ,_param->_nb_context );
1321	DELETE1_SC_SIGNAL(out_EVENT_ADDRESS_NEXT_VAL ,_param->_nb_context );
1322	DELETE1_SC_SIGNAL(out_EVENT_IS_DS_TAKE ,_param->_nb_context );
1323	DELETE1_SC_SIGNAL(out_EVENT_TYPE ,_param->_nb_context );
1324	DELETE1_SC_SIGNAL(out_EVENT_DEPTH ,_param->_nb_context );
1325	DELETE1_SC_SIGNAL(out_SPR_EVENT_VAL ,_param->_nb_context );
1326	DELETE1_SC_SIGNAL( in_SPR_EVENT_ACK ,_param->_nb_context );
1327	DELETE1_SC_SIGNAL(out_SPR_EVENT_EPCR ,_param->_nb_context );
1328	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR ,_param->_nb_context );
1329	DELETE1_SC_SIGNAL(out_SPR_EVENT_EEAR_WEN ,_param->_nb_context );
1330	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_DSX ,_param->_nb_context );
1331	DELETE1_SC_SIGNAL(out_SPR_EVENT_SR_TO_ESR ,_param->_nb_context );
1332	DELETE1_SC_SIGNAL(out_CONTEXT_DECOD_ENABLE ,_param->_nb_context );
1333	DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context );
1334	DELETE1_SC_SIGNAL( in_SPR_SR_IEE ,_param->_nb_context );
1335	DELETE1_SC_SIGNAL( in_SPR_SR_EPH ,_param->_nb_context );
1336
1337	DELETE1_SC_SIGNAL( in_INTERRUPT_ENABLE ,_param->_nb_context );
1338	}
1339	#endif
1340
1341	delete _Context_State;
1342	#ifdef STATISTICS
1343	delete _parameters_statistics;
1344	#endif
1345	}

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