source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp @ 83

Last change on this file since 83 was 83, checked in by rosiere, 16 years ago

Add component : Context_State (manage miss prediction, exception , decod_enable, synchronisation instruction ...)

  • Property svn:keywords set to Id
File size: 3.1 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id: Context_State_genMoore.cpp 83 2008-05-09 18:00:21Z rosiere $
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace context_state {
17
18
19#undef  FUNCTION
20#define FUNCTION "Context_State::genMoore"
21  void Context_State::genMoore (void)
22  {
23    log_begin(Context_State,FUNCTION);
24
25    // -------------------------------------------------------------------
26    // -----[ EVENT ]-----------------------------------------------------
27    // -------------------------------------------------------------------
28    for (uint32_t i=0; i<_param->_nb_context; i++)
29      {
30        context_state_t state = reg_STATE [i];
31
32        internal_EVENT_VAL [i] = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or
33                                  (state == CONTEXT_STATE_KO_MISS_ADDR ) or
34                                  (state == CONTEXT_STATE_KO_PSYNC_ADDR) or
35                                  (state == CONTEXT_STATE_KO_CSYNC_ADDR));
36
37        // excep : address exception
38        // miss  : address delay_slot, and address dest
39        // psync : address next
40        // csync : address next
41        PORT_WRITE(out_EVENT_VAL              [i], internal_EVENT_VAL     [i]);
42        PORT_WRITE(out_EVENT_ADDRESS          [i], reg_EVENT_ADDRESS      [i]);
43        PORT_WRITE(out_EVENT_ADDRESS_NEXT     [i], reg_EVENT_ADDRESS_EPCR [i]); 
44        PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]));
45        PORT_WRITE(out_EVENT_IS_DS_TAKE       [i], (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]));
46      }
47
48    // -------------------------------------------------------------------
49    // -----[ SPR ]-------------------------------------------------------
50    // -------------------------------------------------------------------
51    for (uint32_t i=0; i<_param->_nb_context; i++)
52      {
53        context_state_t state = reg_STATE [i];
54
55        internal_SPR_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR  );
56
57        PORT_WRITE(out_SPR_VAL       [i], internal_SPR_VAL           [i]);
58        PORT_WRITE(out_SPR_EPCR      [i], reg_EVENT_ADDRESS_EPCR     [i]);
59        PORT_WRITE(out_SPR_EEAR      [i], reg_EVENT_ADDRESS_EEAR     [i]);
60        PORT_WRITE(out_SPR_EEAR_WEN  [i], reg_EVENT_ADDRESS_EEAR_VAL [i]);
61        PORT_WRITE(out_SPR_SR_DSX    [i], reg_EVENT_IS_DELAY_SLOT    [i]);
62        PORT_WRITE(out_SPR_SR_TO_ESR [i], 1);
63      }
64
65    // -------------------------------------------------------------------
66    // -----[ CONTEXT ]---------------------------------------------------
67    // -------------------------------------------------------------------
68    for (uint32_t i=0; i<_param->_nb_context; i++)
69      {
70        context_state_t state = reg_STATE [i];
71
72        PORT_WRITE(out_CONTEXT_DECOD_ENABLE [i], ((state==CONTEXT_STATE_OK            ) or
73                                                  (state==CONTEXT_STATE_KO_MSYNC_ISSUE) or
74                                                  (state==CONTEXT_STATE_KO_SPR_ISSUE  )));
75      }
76
77    log_end(Context_State,FUNCTION);
78  };
79
80}; // end namespace context_state
81}; // end namespace front_end
82}; // end namespace multi_front_end
83}; // end namespace core
84
85}; // end namespace behavioural
86}; // end namespace morpheo             
87#endif
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