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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_transition.cpp @ 117

Last change on this file since 117 was 117, checked in by rosiere, 15 years ago
1) Platforms : add new organization for test 2) Load_Store_Unit : add array to count nb_check in store_queue 3) Issue_queue and Core_Glue : rewrite the issue network 4) Special_Register_Unit : add reset value to register CID 5) Softwares : add multicontext test 6) Softwares : add SPECINT 7) Softwares : add MiBench? 7) Read_queue : inhib access for r0 8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
Property svn:keywords set to `Id`
File size: 34.2 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Context_State_transition.cpp 117 2009-05-16 14:42:39Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Context_State/include/Context_State.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace context_state {
17
18
19	#define get_priority(x) \
20	(((state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or \
21	(state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or \
22	(state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or \
23	(state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND ) or \
24	(state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE))?3: \
25	(((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or \
26	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or \
27	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ))?2: \
28	((state == EVENT_TYPE_EXCEPTION)?1: \
29	0)))
30
31	#undef FUNCTION
32	#define FUNCTION "Context_State::transition"
33	void Context_State::transition (void)
34	{
35	log_begin(Context_State,FUNCTION);
36	log_function(Context_State,FUNCTION,_name.c_str());
37
38	if (PORT_READ(in_NRESET) == 0)
39	{
40	for (uint32_t i=0; i<_param->_nb_context; i++)
41	{
42	reg_STATE [i] = CONTEXT_STATE_OK;
43	reg_INTERRUPT_ENABLE [i] = 0;
44	}
45	}
46	else
47	{
48	// -------------------------------------------------------------------
49	// -----[ next state ]------------------------------------------------
50	// -------------------------------------------------------------------
51	for (uint32_t i=0; i<_param->_nb_context; i++)
52	{
53	// uint32_t x = _param->_link_context_to_decod_unit [i];
54
55	Tcounter_t inst_all = PORT_READ(in_NB_INST_COMMIT_ALL[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
56	// Tcounter_t inst_mem = PORT_READ(in_NB_INST_COMMIT_MEM[i]) + PORT_READ(in_NB_INST_DECOD_ALL [i]);
57
58	context_state_t state = reg_STATE [i];
59
60	switch (state)
61	{
62	case CONTEXT_STATE_OK :
63	{
64	// nothing, wait an event
65	break;
66	}
67	case CONTEXT_STATE_KO_EXCEP :
68	{
69	// Wait end of all instruction
70	if (inst_all == 0)
71	state = CONTEXT_STATE_KO_EXCEP_ADDR;
72	break;
73	}
74	case CONTEXT_STATE_KO_EXCEP_ADDR :
75	{
76	// nothing, wait the update of internal register (pc)
77	break;
78	}
79	case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE :
80	{
81	// nothing : wait end of update upt
82	break;
83	}
84	case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND :
85	{
86	// Wait end of all instruction
87	if (inst_all == 0)
88
89	// state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
90	state = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
91	break;
92	}
93	case CONTEXT_STATE_KO_MISS_LOAD_WAITEND :
94	{
95	// Wait end of all instruction
96	if (inst_all == 0)
97	state = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
98
99	break;
100	}
101	case CONTEXT_STATE_KO_EXCEP_SPR :
102	{
103	// nothing, wait the update of internal register (epcr, eear, sr, esr)
104	break;
105	}
106	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR :
107	{
108	// nothing, wait the update of internal register (pc)
109	break;
110	}
111	case CONTEXT_STATE_KO_MISS_LOAD_ADDR :
112	{
113	// nothing, wait the update of internal register (pc)
114	break;
115	}
116	case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE :
117	{
118	// nothing : wait end of update upt
119	break;
120	}
121	case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR :
122	{
123	// nothing, wait the update of internal register (pc)
124	break;
125	}
126	case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND :
127	{
128	// Wait end of all instruction
129	if (inst_all == 0)
130
131	// state = CONTEXT_STATE_OK; // @@@ TODO : make MISS fast (miss decod)
132	state = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR;
133	break;
134	}
135	// case CONTEXT_STATE_KO_PSYNC :
136	// {
137	// // Wait end of all instruction
138	// if (inst_all == 0)
139	// state = CONTEXT_STATE_KO_PSYNC_FLUSH;
140	// break;
141	// }
142	case CONTEXT_STATE_KO_PSYNC_FLUSH :
143	{
144	// nothing, wait end of flush (ifetch)
145	if (inst_all == 0)
146	// state = CONTEXT_STATE_KO_PSYNC_ADDR;
147	state = CONTEXT_STATE_OK;
148
149	break;
150	}
151	case CONTEXT_STATE_KO_PSYNC_ADDR :
152	{
153	// nothing, wait the pc write
154	break;
155	}
156	// case CONTEXT_STATE_KO_CSYNC :
157	// {
158	// // Wait end of all instruction
159	// if (inst_all == 0)
160	// state = CONTEXT_STATE_KO_CSYNC_FLUSH;
161	// break;
162	// }
163	case CONTEXT_STATE_KO_CSYNC_FLUSH :
164	{
165	// nothing, wait end of flush (all internal structure)
166	if (inst_all == 0)
167	state = CONTEXT_STATE_KO_CSYNC_ADDR;
168	break;
169	}
170	case CONTEXT_STATE_KO_CSYNC_ADDR :
171	{
172	// nothing, wait the pc write
173	break;
174	}
175	// case CONTEXT_STATE_KO_MSYNC :
176	// {
177	// // Wait end of memory instruction
178	// if (inst_mem == 0)
179	// state = CONTEXT_STATE_KO_MSYNC_ISSUE;
180	// break;
181	// }
182	// case CONTEXT_STATE_KO_MSYNC_ISSUE :
183	// {
184	// // Wait the msync issue
185	// if (inst_mem != 0)
186	// state = CONTEXT_STATE_KO_MSYNC_EXEC;
187	// break;
188	// }
189	case CONTEXT_STATE_KO_MSYNC_EXEC :
190	{
191	// Wait the end of msync
192	if (inst_all == 0)
193	state = CONTEXT_STATE_OK;
194	break;
195	}
196	// case CONTEXT_STATE_KO_SPR :
197	// {
198	// // Wait end of all instruction
199	// if (inst_all == 0)
200	// state = CONTEXT_STATE_KO_SPR_ISSUE;
201	// break;
202	// }
203	// case CONTEXT_STATE_KO_SPR_ISSUE :
204	// {
205	// // Wait the spr_access issue
206	// if (inst_all != 0)
207	// state = CONTEXT_STATE_KO_SPR_EXEC;
208	// break;
209	// }
210	case CONTEXT_STATE_KO_SPR_EXEC :
211	{
212	// Wait the spr_access execution
213	if (inst_all == 0)
214	state = CONTEXT_STATE_OK;
215	break;
216	}
217
218	default :
219	{
220	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Unknow state : %s.\n"),i,toString(state).c_str()));
221	}
222	}
223	reg_STATE [i] = state;
224	}
225
226	// -------------------------------------------------------------------
227	// -----[ EVENT ]-----------------------------------------------------
228	// -------------------------------------------------------------------
229	for (uint32_t i=0; i<_param->_nb_context; i++)
230	if (internal_EVENT_VAL [i] and PORT_READ(in_EVENT_ACK [i]))
231	{
232	log_printf(TRACE,Context_State,FUNCTION," * EVENT [%d]",i);
233	// Write pc
234	context_state_t state = reg_STATE [i];
235
236	switch (state)
237	{
238	case CONTEXT_STATE_KO_EXCEP_ADDR :
239	{
240	reg_STATE [i] = CONTEXT_STATE_KO_EXCEP_SPR;
241	break;
242	}
243	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR:
244
245	// {
246	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_WAITEND; //@@@ TODO : make MISS fast (miss decod)
247	// break;
248	// }
249	case CONTEXT_STATE_KO_MISS_LOAD_ADDR :
250	case CONTEXT_STATE_KO_PSYNC_ADDR :
251	case CONTEXT_STATE_KO_CSYNC_ADDR :
252	{
253	reg_STATE [i] = CONTEXT_STATE_OK;
254	break;
255	}
256	case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR:
257	{
258	reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_ADDR;
259	break;
260	}
261	default :
262	{
263	#ifdef DEBUG_TEST
264	throw ERRORMORPHEO(FUNCTION,toString(_("SPR[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
265	#endif
266	break;
267	}
268	}
269	}
270
271	// -------------------------------------------------------------------
272	// -----[ BRANCH_EVENT ]----------------------------------------------
273	// -------------------------------------------------------------------
274	for (uint32_t i=0; i<_param->_nb_context; ++i)
275	if (PORT_READ(in_BRANCH_EVENT_VAL [i]) and internal_BRANCH_EVENT_ACK [i])
276	{
277	log_printf(TRACE,Context_State,FUNCTION," * BRANCH_EVENT [%d]",i);
278
279	context_state_t state = reg_STATE [i];
280
281	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_EVENT_DEPTH [i]):0;
282	Tdepth_t depth_cur = reg_EVENT_DEPTH [i];
283	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [i]):0;
284	Tdepth_t depth_max = _param->_nb_inst_branch_speculated [i];
285
286	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
287	Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
288	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
289	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
290
291	// priority : miss_load > miss_branch > excep > spr/sync
292	uint8_t priority0 = get_priority(state);
293	uint8_t priority1 = 2; // miss
294
295	// is_valid = can modify local information
296	// if context_state_ok : yes
297	// if context_state_ko : test the depth, and the priority of event
298	bool is_valid = ((state == CONTEXT_STATE_OK) or
299	(state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) or
300	(state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE) or
301	(depth1< depth0) or
302	((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
303
304	#ifdef DEBUG_TEST
305	if ((state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE) and
306	(depth0 != depth1))
307	throw ERRORMORPHEO(FUNCTION,toString(_("BRANCH_EVENT[%d] : Invalid state : %s.\n"),i,toString(state).c_str()));
308	#endif
309
310	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
311	log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
312	log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
313	log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
314	log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
315	log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
316	log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
317	log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
318	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
319
320	if (is_valid)
321	{
322	// reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
323
324	if (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE)
325	{
326	reg_STATE [i] = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;
327	}
328	else
329	{
330	reg_STATE [i] = CONTEXT_STATE_KO_MISS_BRANCH_WAITEND; //@@@ TODO : make MISS fast (miss decod)
331
332	Tcontrol_t dest_val = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST_VAL[i]);
333	reg_EVENT_ADDRESS [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_SRC [i])+1; // address delay slot
334	reg_EVENT_ADDRESS_EPCR [i] = PORT_READ(in_BRANCH_EVENT_ADDRESS_DEST [i]); // address_next
335	reg_EVENT_ADDRESS_EPCR_VAL [i] = dest_val;
336	//reg_EVENT_ADDRESS_EEAR [i] = 0;
337	reg_EVENT_ADDRESS_EEAR_VAL [i] = 0;
338	reg_EVENT_IS_DELAY_SLOT [i] = 1;
339	reg_EVENT_IS_DS_TAKE [i] = dest_val;
340	reg_EVENT_DEPTH [i] = depth;
341	}
342	}
343	}
344
345	// -------------------------------------------------------------------
346	// -----[ BRANCH_COMPLETE ]----------------------------------------------
347	// -------------------------------------------------------------------
348	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
349	if (PORT_READ(in_BRANCH_COMPLETE_VAL [i]) and internal_BRANCH_COMPLETE_ACK [i]
350	and PORT_READ(in_BRANCH_COMPLETE_MISS_PREDICTION [i]))
351	{
352	log_printf(TRACE,Context_State,FUNCTION," * BRANCH_COMPLETE [%d]",i);
353
354	Tcontext_t context_id = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
355
356	context_state_t state = reg_STATE [context_id];
357
358	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
359	Tdepth_t depth_cur = reg_EVENT_DEPTH [context_id];
360	Tdepth_t depth_min = (_param->_have_port_depth)?PORT_READ(in_DEPTH_MIN [context_id]):0;
361	Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context_id];
362
363	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
364	Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
365	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
366	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
367
368	// priority : miss_load > miss_branch > excep > spr/sync
369	uint8_t priority0 = get_priority(state);
370	uint8_t priority1 = 2; // miss
371
372	// is_valid = can modify local information
373	// if context_state_ok : yes
374	// if context_state_ko : test the depth, and the priority of event
375	bool is_valid = ((state == CONTEXT_STATE_OK) or
376	(depth1< depth0) or
377	((depth1==depth0) and (priority1>=priority0))); // >= because another branch can be a miss prediction with same depth
378
379	log_printf(TRACE,Context_State,FUNCTION," * context_id: %d",context_id);
380	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
381	log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
382	log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
383	log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
384	log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
385	log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
386	log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
387	log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
388	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
389
390	if (is_valid)
391	{
392	// reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_ADDR;
393	reg_STATE [context_id] = CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE;
394	reg_EVENT_DEPTH [context_id] = depth;
395	}
396	}
397
398	// -------------------------------------------------------------------
399	// -----[ DECOD_EVENT ]-----------------------------------------------
400	// -------------------------------------------------------------------
401
402	for (uint32_t i=0; i<_param->_nb_decod_unit; i++)
403	if (PORT_READ(in_DECOD_EVENT_VAL [i]) and internal_DECOD_EVENT_ACK [i])
404	{
405	log_printf(TRACE,Context_State,FUNCTION," * DECOD_EVENT [%d]",i);
406
407	Tcontext_t context = (_param->_have_port_context_id )?PORT_READ(in_DECOD_EVENT_CONTEXT_ID [i]):0;
408	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_DECOD_EVENT_DEPTH [i]):0;
409	Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
410	Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
411	Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context];
412
413	Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
414	Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
415	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
416	// Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
417
418	context_state_t state = reg_STATE [context];
419	Tevent_type_t type = PORT_READ(in_DECOD_EVENT_TYPE [i]);
420
421	// miss_load > miss_branch > excep > spr/sync
422	uint8_t priority0 = get_priority(state);
423	uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:0;
424
425	// is_valid = can modify local information
426	// if context_state_ok : yes
427	// if context_state_ko : test the depth, and the priority of envent
428
429	bool is_valid = ((state == CONTEXT_STATE_OK) or
430	(depth1< depth0) or
431	((depth1==depth0) and (priority1>=priority0)));
432
433	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
434	log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
435	log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
436	log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
437	log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
438	log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
439	log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
440	log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
441	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
442
443	if (is_valid)
444	{
445	log_printf(TRACE,Context_State,FUNCTION," * is_valid");
446
447	// decod :
448	// type : csync, psync, msync, spr_access (l.mac, l.maci, l.macrc, l.msb, l.mfspr, l.mtspr), exception (l.sys)
449	context_state_t state_next = state;
450	Taddress_t address = PORT_READ(in_DECOD_EVENT_ADDRESS [i]);
451	Tcontrol_t is_delay_slot = PORT_READ(in_DECOD_EVENT_IS_DELAY_SLOT [i]);
452
453	switch (type)
454	{
455	case EVENT_TYPE_EXCEPTION :
456	{
457	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_EXCEPTION");
458
459	state_next = CONTEXT_STATE_KO_EXCEP;
460
461	break;
462	}
463	case EVENT_TYPE_SPR_ACCESS :
464	{
465	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_SPR_ACCESS");
466
467	// state_next = CONTEXT_STATE_KO_SPR ;
468	state_next = CONTEXT_STATE_KO_SPR_EXEC;
469	address++; // take next address
470	// if (is_delay_slot)
471	// throw ERRORMORPHEO(FUNCTION,"SPR access in delay slot, not supported.\n");
472	break;
473	}
474	case EVENT_TYPE_MSYNC :
475	{
476	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_MSYNC");
477
478	// state_next = CONTEXT_STATE_KO_MSYNC;
479	state_next = CONTEXT_STATE_KO_MSYNC_EXEC;
480	address++; // take next address
481	// if (is_delay_slot)
482	// throw ERRORMORPHEO(FUNCTION,"MSYNC in delay slot, not supported.\n");
483	break;
484	}
485	case EVENT_TYPE_PSYNC :
486	{
487	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_PSYNC");
488
489	// state_next = CONTEXT_STATE_KO_PSYNC;
490	state_next = CONTEXT_STATE_KO_PSYNC_FLUSH;
491	address++; // take next address
492	if (is_delay_slot)
493	throw ERRORMORPHEO(FUNCTION,"PSYNC in delay slot, not supported.\n");
494	break;
495	}
496	case EVENT_TYPE_CSYNC :
497	{
498	log_printf(TRACE,Context_State,FUNCTION," * EVENT_TYPE_CSYNC");
499
500	// state_next = CONTEXT_STATE_KO_CSYNC;
501	state_next = CONTEXT_STATE_KO_CSYNC_FLUSH;
502	address++; // take next address
503	if (is_delay_slot)
504	throw ERRORMORPHEO(FUNCTION,"CSYNC in delay slot, not supported.\n");
505	break;
506	}
507	case EVENT_TYPE_NONE :
508	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
509	case EVENT_TYPE_LOAD_MISS_SPECULATION :
510	// case EVENT_TYPE_BRANCH_NO_ACCURATE :
511	default :
512	{
513	throw ERRORMORPHEO(FUNCTION,toString(_("DECOD_EVENT [%d] : invalid event_type : %s.\n"),i,toString(type).c_str()));
514	}
515	}
516
517	reg_STATE [context] = state_next;
518	reg_EVENT_ADDRESS [context] = address;
519	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_DECOD_EVENT_ADDRESS_EPCR [i]);
520	reg_EVENT_ADDRESS_EPCR_VAL [context] = 1;
521	//reg_EVENT_ADDRESS_EEAR [context]
522	reg_EVENT_ADDRESS_EEAR_VAL [context] = 0;
523	reg_EVENT_IS_DELAY_SLOT [context] = is_delay_slot;
524	//reg_EVENT_IS_DS_TAKE [context] = 0;
525	reg_EVENT_DEPTH [context] = depth;
526	}
527	}
528
529	// -------------------------------------------------------------------
530	// -----[ COMMIT_EVENT ]----------------------------------------------
531	// -------------------------------------------------------------------
532
533	if (PORT_READ(in_COMMIT_EVENT_VAL ) and internal_COMMIT_EVENT_ACK )
534	{
535	log_printf(TRACE,Context_State,FUNCTION," * COMMIT_EVENT");
536
537	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_COMMIT_EVENT_CONTEXT_ID ):0;
538	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_COMMIT_EVENT_DEPTH ):0;
539	// Tdepth_t depth_cur = reg_EVENT_DEPTH [context];
540	// Tdepth_t depth_min = (_param->_have_port_depth )?PORT_READ(in_DEPTH_MIN [context]):0;
541	// Tdepth_t depth_max = _param->_nb_inst_branch_speculated [context];
542
543	// Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur-depth_min):((depth_cur+depth_max-depth_min));
544	// Tdepth_t depth1 = (depth >=depth_min)?(depth -depth_min):((depth +depth_max-depth_min));
545	// // Tdepth_t depth0 = (depth_cur>=depth_min)?(depth_cur):((depth_cur+depth_max));
546	// // Tdepth_t depth1 = (depth >=depth_min)?(depth ):((depth +depth_max));
547
548	context_state_t state = reg_STATE [context];
549	Tevent_type_t type = PORT_READ(in_COMMIT_EVENT_TYPE );
550
551	// // miss > excep > spr/sync
552	// uint8_t priority0 = ((state == CONTEXT_STATE_KO_MISS_BRANCH_ADDR ) or
553	// (state == CONTEXT_STATE_KO_MISS_LOAD_ADDR ) or
554	// (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR ) or
555	// (state == CONTEXT_STATE_KO_MISS_BRANCH_WAITEND ) or
556	// (state == CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE ) or
557	// (state == CONTEXT_STATE_KO_MISS_LOAD_WAITEND ) or
558	// (state == CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND))?2:((state == CONTEXT_STATE_KO_EXCEP)?1:0);
559	// uint8_t priority1 = (state == EVENT_TYPE_EXCEPTION)?1:2; // else load_miss_speculation (EVENT_TYPE_MISS_SPECULATION)
560
561	// // is_valid = can modify local information
562	// // if context_state_ok : yes
563	// // if context_state_ko : test the depth, and the priority of envent
564
565	// bool is_valid = ((state == CONTEXT_STATE_OK) or
566	// (depth1< depth0) or
567	// ((depth1==depth0) and (priority1>=priority0)));
568
569	// if commit send an event, also they have not yet event previous this instruction
570	bool is_valid = true;
571
572	log_printf(TRACE,Context_State,FUNCTION," * depth : %d",depth );
573	// log_printf(TRACE,Context_State,FUNCTION," * depth_cur : %d",depth_cur );
574	// log_printf(TRACE,Context_State,FUNCTION," * depth_min : %d",depth_min );
575	// log_printf(TRACE,Context_State,FUNCTION," * depth_max : %d",depth_max );
576	// log_printf(TRACE,Context_State,FUNCTION," * depth0 : %d",depth0 );
577	// log_printf(TRACE,Context_State,FUNCTION," * depth1 : %d",depth1 );
578	// log_printf(TRACE,Context_State,FUNCTION," * priority0 : %d",priority0 );
579	// log_printf(TRACE,Context_State,FUNCTION," * priority1 : %d",priority1 );
580	log_printf(TRACE,Context_State,FUNCTION," * is_valid : %d",is_valid );
581
582	if (is_valid)
583	{
584	// commit
585	// type : exception
586	context_state_t state_next = state;
587	switch (type)
588	{
589	case EVENT_TYPE_EXCEPTION : {state_next = CONTEXT_STATE_KO_EXCEP; break;}
590	case EVENT_TYPE_LOAD_MISS_SPECULATION :
591	{
592	// Test if previous branch occure
593	switch (state)
594	{
595	case CONTEXT_STATE_KO_MISS_BRANCH_WAIT_UPDATE :
596	{
597	state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAIT_UPDATE;
598	break;
599	}
600	case CONTEXT_STATE_KO_MISS_BRANCH_ADDR :
601	case CONTEXT_STATE_KO_MISS_BRANCH_WAITEND :
602	case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_ADDR :
603	case CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND :
604	{
605	state_next = CONTEXT_STATE_KO_MISS_LOAD_AND_BRANCH_WAITEND;
606	break;
607	}
608	default :
609	{
610	state_next = CONTEXT_STATE_KO_MISS_LOAD_WAITEND;
611	break;
612	}
613	}
614	break;
615	}
616	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
617	case EVENT_TYPE_SPR_ACCESS :
618	case EVENT_TYPE_MSYNC :
619	case EVENT_TYPE_PSYNC :
620	case EVENT_TYPE_CSYNC :
621	case EVENT_TYPE_NONE :
622	// case EVENT_TYPE_BRANCH_NO_ACCURATE :
623	default :
624	{
625	throw ERRORMORPHEO(FUNCTION,toString(_("COMMIT_EVENT : invalid event_type : %s.\n"),toString(type).c_str()));
626	}
627	}
628	reg_STATE [context] = state_next;
629	reg_EVENT_ADDRESS [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS );
630	reg_EVENT_ADDRESS_EPCR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR );
631	reg_EVENT_ADDRESS_EPCR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EPCR_VAL );
632	reg_EVENT_ADDRESS_EEAR [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR );
633	reg_EVENT_ADDRESS_EEAR_VAL [context] = PORT_READ(in_COMMIT_EVENT_ADDRESS_EEAR_VAL );
634	reg_EVENT_IS_DELAY_SLOT [context] = PORT_READ(in_COMMIT_EVENT_IS_DELAY_SLOT );
635	reg_EVENT_IS_DS_TAKE [context] = 0;
636	reg_EVENT_DEPTH [context] = depth;
637	}
638	}
639
640	// -------------------------------------------------------------------
641	// -----[ SPR_EVENT ]-------------------------------------------------
642	// -------------------------------------------------------------------
643	for (uint32_t i=0; i<_param->_nb_context; i++)
644	if (internal_SPR_EVENT_VAL [i] and PORT_READ(in_SPR_EVENT_ACK [i]))
645	{
646	log_printf(TRACE,Context_State,FUNCTION," * SPR_EVENT [%d]",i);
647
648	// Write spr
649	#ifdef DEBUG_TEST
650	context_state_t state = reg_STATE [i];
651
652	if (state != CONTEXT_STATE_KO_EXCEP_SPR)
653	throw ERRORMORPHEO(FUNCTION,toString(_("SPR_EVENT[%d], Invalid state : %s.\n"),i,toString(state).c_str()));
654	#endif
655
656	reg_STATE [i] = CONTEXT_STATE_OK;
657	}
658
659	for (uint32_t i=0; i<_param->_nb_context; ++i)
660	{
661	reg_INTERRUPT_ENABLE [i] = PORT_READ(in_INTERRUPT_ENABLE [i]) and PORT_READ(in_SPR_SR_IEE [i]);
662
663	if (reg_INTERRUPT_ENABLE [i])
664	throw ERRORMORPHEO(FUNCTION,toString(_("Context[%d], Have an interruption, Not yet supported (Comming Soon).\n"),i));
665	}
666	}
667
668	#if DEBUG >= DEBUG_TRACE
669	for (uint32_t i=0; i<_param->_nb_context; i++)
670	{
671	log_printf(TRACE,Context_State,FUNCTION," * Dump Context State [%d]",i);
672	log_printf(TRACE,Context_State,FUNCTION," * reg_STATE : %s" ,toString(reg_STATE [i]).c_str());
673	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS : 0x%x (0x%x)",reg_EVENT_ADDRESS [i],reg_EVENT_ADDRESS [i]<<2);
674	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EPCR [i],reg_EVENT_ADDRESS_EPCR [i]<<2);
675	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EPCR_VAL : %d" ,reg_EVENT_ADDRESS_EPCR_VAL [i]);
676	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR : 0x%x (0x%x)",reg_EVENT_ADDRESS_EEAR [i],reg_EVENT_ADDRESS_EEAR [i]<<2);
677	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_ADDRESS_EEAR_VAL : %d" ,reg_EVENT_ADDRESS_EEAR_VAL [i]);
678	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DELAY_SLOT : %d" ,reg_EVENT_IS_DELAY_SLOT [i]);
679	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_IS_DS_TAKE : %d" ,reg_EVENT_IS_DS_TAKE [i]);
680	log_printf(TRACE,Context_State,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
681	}
682	#endif
683
684	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
685	end_cycle ();
686	#endif
687
688	log_end(Context_State,FUNCTION);
689	};
690
691	}; // end namespace context_state
692	}; // end namespace front_end
693	}; // end namespace multi_front_end
694	}; // end namespace core
695
696	}; // end namespace behavioural
697	}; // end namespace morpheo
698	#endif

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