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Instruction.cpp

Last change on this file was 137, checked in by rosiere, 14 years ago
Various modif (add test, and vhdl)
Property svn:keywords set to `Id`
File size: 147.5 KB

Line
1	/*
2	* $Id: Instruction.cpp 137 2010-02-16 12:35:48Z rosiere $
3	*
4	* [ Description ]
5	*
6	* instruction MAC_UNIT (l.mac, l.maci, l.macrc, l.msb) throw a context event. Also is sequential.
7	* If your program need intensive mac_unit, you can change the implementation of this unit :
8	* 1) "decod" : inst->_event_type = EVENT_TYPE_NONE;
9	* 2) "rename" : add component as load_store_unit pointer management
10	* 3) "functionnal_unit" : test type instruction, if type=MAC_UNIT, insert in queue, the localisation is the ptr give by rename stage. Retire in this queue in sequence (as the store queue).
11	*
12	*/
13
14	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Instruction.h"
15	#include "Behavioural/include/Constants.h"
16	#include "Behavioural/include/Operation.h"
17
18	namespace morpheo {
19	namespace behavioural {
20	namespace core {
21	namespace multi_front_end {
22	namespace front_end {
23	namespace decod_unit {
24	namespace decod {
25
26	#define EXTENDS(x,nb_bits) extend<Tgeneral_data_t>(param->_size_data, x,true ,nb_bits)
27	#define EXTENDZ(x,nb_bits) extend<Tgeneral_data_t>(param->_size_data, x,false,nb_bits)
28
29	void instruction_decod (decod_instruction_t * inst, decod_param_t * param)
30	{
31	log_printf(TRACE,Decod,"instruction_decod"," * instruction : decod");
32
33	// instruction_decod_type_0 (inst,param);
34
35	uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
36
37	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
38
39	(* param->_function_decod[ 0][opcod]) (inst,param);
40	}
41
42	// void instruction_decod_type_0 (decod_instruction_t * inst, decod_param_t * param)
43	// {
44	// uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
45	// (* param->_function_decod[ 0][opcod]) (inst,param);
46	// }
47
48	void instruction_decod_type_1 (decod_instruction_t * inst, decod_param_t * param)
49	{
50	log_printf(TRACE,Decod,"instruction_decod_type_1"," * instruction : decod type_1");
51
52	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
53
54	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
55
56	(* param->_function_decod[ 1][opcod]) (inst,param);
57	}
58
59	void instruction_decod_type_2 (decod_instruction_t * inst, decod_param_t * param)
60	{
61	log_printf(TRACE,Decod,"instruction_decod_type_2"," * instruction : decod type_2");
62
63	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
64
65	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
66
67	(* param->_function_decod[ 2][opcod]) (inst,param);
68	}
69
70	void instruction_decod_type_3 (decod_instruction_t * inst, decod_param_t * param)
71	{
72	log_printf(TRACE,Decod,"instruction_decod_type_3"," * instruction : decod type_3");
73
74	uint32_t opcod = ((range<uint32_t>(inst->_instruction, 9, 8)<<4) \|
75	(range<uint32_t>(inst->_instruction, 3, 0)));
76
77	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
78
79	(* param->_function_decod[ 3][opcod]) (inst,param);
80	}
81
82	void instruction_decod_type_4 (decod_instruction_t * inst, decod_param_t * param)
83	{
84	log_printf(TRACE,Decod,"instruction_decod_type_4"," * instruction : decod type_4");
85
86	uint32_t opcod = range<uint32_t>(inst->_instruction,25,21);
87
88	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
89
90	(* param->_function_decod[ 4][opcod]) (inst,param);
91	}
92
93	void instruction_decod_type_5 (decod_instruction_t * inst, decod_param_t * param)
94	{
95	log_printf(TRACE,Decod,"instruction_decod_type_5"," * instruction : decod type_5");
96
97	uint32_t opcod = range<uint32_t>(inst->_instruction,25,21);
98
99	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
100
101	(* param->_function_decod[ 5][opcod]) (inst,param);
102	}
103
104	void instruction_decod_type_6 (decod_instruction_t * inst, decod_param_t * param)
105	{
106	log_printf(TRACE,Decod,"instruction_decod_type_6"," * instruction : decod type_6");
107
108	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
109
110	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
111
112	(* param->_function_decod[ 6][opcod]) (inst,param);
113	}
114
115	void instruction_decod_type_7 (decod_instruction_t * inst, decod_param_t * param)
116	{
117	log_printf(TRACE,Decod,"instruction_decod_type_7"," * instruction : decod type_7");
118
119	uint32_t opcod = range<uint32_t>(inst->_instruction, 3, 0);
120
121	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
122
123	(* param->_function_decod[ 7][opcod]) (inst,param);
124	}
125
126	void instruction_decod_type_8 (decod_instruction_t * inst, decod_param_t * param)
127	{
128	log_printf(TRACE,Decod,"instruction_decod_type_8"," * instruction : decod type_8");
129
130	uint32_t opcod = range<uint32_t>(inst->_instruction,16,16);
131
132	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
133
134	(* param->_function_decod[ 8][opcod]) (inst,param);
135	}
136
137	void instruction_decod_type_9 (decod_instruction_t * inst, decod_param_t * param)
138	{
139	log_printf(TRACE,Decod,"instruction_decod_type_9"," * instruction : decod type_9");
140
141	uint32_t opcod = range<uint32_t>(inst->_instruction,25,23);
142
143	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
144
145	(* param->_function_decod[ 9][opcod]) (inst,param);
146	}
147
148	void instruction_decod_type_10 (decod_instruction_t * inst, decod_param_t * param)
149	{
150	log_printf(TRACE,Decod,"instruction_decod_type_10"," * instruction : decod type_10");
151
152	uint32_t opcod = range<uint32_t>(inst->_instruction,25,24);
153
154	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
155
156	(* param->_function_decod[10][opcod]) (inst,param);
157	}
158
159	void instruction_decod_type_11 (decod_instruction_t * inst, decod_param_t * param)
160	{
161	log_printf(TRACE,Decod,"instruction_decod_type_11"," * instruction : decod type_11");
162
163	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
164
165	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
166
167	(* param->_function_decod[11][opcod]) (inst,param);
168	}
169
170	void instruction_decod_type_12 (decod_instruction_t * inst, decod_param_t * param)
171	{
172	log_printf(TRACE,Decod,"instruction_decod_type_12"," * instruction : decod type_12");
173
174	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
175
176	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
177
178	(* param->_function_decod[12][opcod]) (inst,param);
179	}
180
181	void instruction_decod_type_13 (decod_instruction_t * inst, decod_param_t * param)
182	{
183	log_printf(TRACE,Decod,"instruction_decod_type_13"," * instruction : decod type_13");
184
185	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 6);
186
187	log_printf(TRACE,Decod,"instruction_decod"," * opcod : %d (0x%x)",opcod,opcod);
188
189	(* param->_function_decod[13][opcod]) (inst,param);
190	}
191
192	void instruction_illegal (decod_instruction_t * inst, decod_param_t * param)
193	{
194	log_printf(TRACE,Decod,"instruction_illegal"," * instruction : illegal");
195
196	msgWarning(_("Instruction \"%.8x\" at address \"%.8x\" is illegal.\n"),inst->_instruction,inst->_address);
197
198	inst->_exception_use = EXCEPTION_USE_ILLEGAL_INSTRUCTION;
199	inst->_exception = EXCEPTION_ILLEGAL_INSTRUCTION;
200
201	if (inst->_is_delay_slot)
202	inst->_address_next = inst->_address_previous;
203	else
204	inst->_address_next = inst->_address;
205
206	inst->_event_type = EVENT_TYPE_EXCEPTION;
207	}
208
209	void instruction_l_custom (decod_instruction_t * inst, decod_param_t * param)
210	{
211	log_printf(TRACE,Decod,"instruction_l_custom"," * instruction : custom");
212
213	uint32_t opcod = range<uint32_t>(inst->_instruction,31,26);
214
215	switch (opcod)
216	{
217	case OPCOD_L_CUST1 :
218	{
219	#ifdef STATISTICS
220	inst->_opcod = INSTRUCTION_L_CUST1;
221	#endif
222	inst->_type = instruction_information(INSTRUCTION_L_CUST1)._type;
223	inst->_operation = instruction_information(INSTRUCTION_L_CUST1)._operation;
224	break;
225	}
226	case OPCOD_L_CUST2 :
227	{
228	#ifdef STATISTICS
229	inst->_opcod = INSTRUCTION_L_CUST2;
230	#endif
231	inst->_type = instruction_information(INSTRUCTION_L_CUST2)._type;
232	inst->_operation = instruction_information(INSTRUCTION_L_CUST2)._operation;
233	break;
234	}
235	case OPCOD_L_CUST3 :
236	{
237	#ifdef STATISTICS
238	inst->_opcod = INSTRUCTION_L_CUST3;
239	#endif
240	inst->_type = instruction_information(INSTRUCTION_L_CUST3)._type;
241	inst->_operation = instruction_information(INSTRUCTION_L_CUST3)._operation;
242	break;
243	}
244	case OPCOD_L_CUST4 :
245	{
246	#ifdef STATISTICS
247	inst->_opcod = INSTRUCTION_L_CUST4;
248	#endif
249	inst->_type = instruction_information(INSTRUCTION_L_CUST4)._type;
250	inst->_operation = instruction_information(INSTRUCTION_L_CUST4)._operation;
251	break;
252	}
253	case OPCOD_L_CUST5 :
254	{
255	#ifdef STATISTICS
256	inst->_opcod = INSTRUCTION_L_CUST5;
257	#endif
258	inst->_type = instruction_information(INSTRUCTION_L_CUST5)._type;
259	inst->_operation = instruction_information(INSTRUCTION_L_CUST5)._operation;
260	break;
261	}
262	case OPCOD_L_CUST6 :
263	{
264	#ifdef STATISTICS
265	inst->_opcod = INSTRUCTION_L_CUST6;
266	#endif
267	inst->_type = instruction_information(INSTRUCTION_L_CUST6)._type;
268	inst->_operation = instruction_information(INSTRUCTION_L_CUST6)._operation;
269	break;
270	}
271	case OPCOD_L_CUST7 :
272	{
273	#ifdef STATISTICS
274	inst->_opcod = INSTRUCTION_L_CUST7;
275	#endif
276	inst->_type = instruction_information(INSTRUCTION_L_CUST7)._type;
277	inst->_operation = instruction_information(INSTRUCTION_L_CUST7)._operation;
278	break;
279	}
280	case OPCOD_L_CUST8 :
281	{
282	#ifdef STATISTICS
283	inst->_opcod = INSTRUCTION_L_CUST8;
284	#endif
285	inst->_type = instruction_information(INSTRUCTION_L_CUST8)._type;
286	inst->_operation = instruction_information(INSTRUCTION_L_CUST8)._operation;
287	break;
288	}
289
290	default : {throw ERRORMORPHEO("instruction_l_custom",_("Invalid Custom Opcod."));}
291	}
292
293	(* param->_function_custom[ 0][opcod]) (inst,param);
294
295	instruction_custom(inst,param);
296	}
297
298	void instruction_lf_custom (decod_instruction_t * inst, decod_param_t * param)
299	{
300	log_printf(TRACE,Decod,"instruction_lf_custom"," * instruction : custom");
301
302	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
303
304	switch (opcod)
305	{
306	// case OPCOD_LF_CUST1_D :
307	// {
308	// #ifdef STATISTICS
309	// inst->_opcod = INSTRUCTION_LF_CUST1_D;
310	// #endif
311	// inst->_type = instruction_information(INSTRUCTION_LF_CUST1_D)._type;
312	// inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_D)._operation;
313	// break;
314	// }
315	// case OPCOD_LF_CUST1_S :
316	// {
317	// #ifdef STATISTICS
318	// inst->_opcod = INSTRUCTION_LF_CUST1_S;
319	// #endif
320	// inst->_type = instruction_information(INSTRUCTION_LF_CUST1_S)._type;
321	// inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_S)._operation;
322	// break;
323	// }
324	default : {throw ERRORMORPHEO("instruction_lf_custom",_("Invalid Custom Opcod."));}
325	}
326
327	(* param->_function_custom[ 1][opcod]) (inst,param);
328
329	instruction_custom(inst,param);
330	}
331
332	void instruction_lv_custom (decod_instruction_t * inst, decod_param_t * param)
333	{
334	log_printf(TRACE,Decod,"instruction_lv_custom"," * instruction : custom");
335
336	uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0);
337
338	switch (opcod)
339	{
340	// case OPCOD_LV_CUST1 :
341	// {
342	// #ifdef STATISTICS
343	// inst->_opcod = INSTRUCTION_LV_CUST1;
344	// #endif
345	// inst->_type = instruction_information(INSTRUCTION_LV_CUST1)._type;
346	// inst->_operation = instruction_information(INSTRUCTION_LV_CUST1)._operation;
347	// break;
348	// }
349	// case OPCOD_LV_CUST2 :
350	// {
351	// #ifdef STATISTICS
352	// inst->_opcod = INSTRUCTION_LV_CUST2;
353	// #endif
354	// inst->_type = instruction_information(INSTRUCTION_LV_CUST2)._type;
355	// inst->_operation = instruction_information(INSTRUCTION_LV_CUST2)._operation;
356	// break;
357	// }
358	// case OPCOD_LV_CUST3 :
359	// {
360	// #ifdef STATISTICS
361	// inst->_opcod = INSTRUCTION_LV_CUST3;
362	// #endif
363	// inst->_type = instruction_information(INSTRUCTION_LV_CUST3)._type;
364	// inst->_operation = instruction_information(INSTRUCTION_LV_CUST3)._operation;
365	// break;
366	// }
367	// case OPCOD_LV_CUST4 :
368	// {
369	// #ifdef STATISTICS
370	// inst->_opcod = INSTRUCTION_LV_CUST4;
371	// #endif
372	// inst->_type = instruction_information(INSTRUCTION_LV_CUST4)._type;
373	// inst->_operation = instruction_information(INSTRUCTION_LV_CUST4)._operation;
374	// break;
375	// }
376	default : {throw ERRORMORPHEO("instruction_lv_custom",_("Invalid Custom Opcod."));}
377	}
378
379	(* param->_function_custom[ 2][opcod]) (inst,param);
380
381	instruction_custom(inst,param);
382	}
383
384	void instruction_custom (decod_instruction_t * inst, decod_param_t * param)
385	{
386	// Test custom operation
387
388	std::string msg = "";
389
390	if (inst->_exception_use != EXCEPTION_USE_ILLEGAL_INSTRUCTION)
391	{
392	if (inst->_type != TYPE_CUSTOM)
393	msg += _("Invalid Type.\n");
394
395	if ((inst->_operation != OPERATION_CUSTOM_L_1 ) and
396	(inst->_operation != OPERATION_CUSTOM_L_2 ) and
397	(inst->_operation != OPERATION_CUSTOM_L_3 ) and
398	(inst->_operation != OPERATION_CUSTOM_L_4 ) and
399	(inst->_operation != OPERATION_CUSTOM_L_5 ) and
400	(inst->_operation != OPERATION_CUSTOM_L_6 ) and
401	(inst->_operation != OPERATION_CUSTOM_L_7 ) and
402	(inst->_operation != OPERATION_CUSTOM_L_8 ) and
403	(inst->_operation != OPERATION_CUSTOM_LF_1_D) and
404	(inst->_operation != OPERATION_CUSTOM_LF_1_S) and
405	(inst->_operation != OPERATION_CUSTOM_LV_1 ) and
406	(inst->_operation != OPERATION_CUSTOM_LV_2 ) and
407	(inst->_operation != OPERATION_CUSTOM_LV_3 ) and
408	(inst->_operation != OPERATION_CUSTOM_LV_4 ))
409	msg += _("Invalid Operation.\n");
410
411	if ((inst->_exception_use != EXCEPTION_USE_NONE ) and
412	(inst->_exception_use != EXCEPTION_USE_RANGE ) and
413	(inst->_exception_use != EXCEPTION_USE_CUSTOM_0 ) and
414	(inst->_exception_use != EXCEPTION_USE_CUSTOM_1 ) and
415	(inst->_exception_use != EXCEPTION_USE_CUSTOM_2 ) and
416	(inst->_exception_use != EXCEPTION_USE_CUSTOM_3 ) and
417	(inst->_exception_use != EXCEPTION_USE_CUSTOM_4 ) and
418	(inst->_exception_use != EXCEPTION_USE_CUSTOM_5 ) and
419	(inst->_exception_use != EXCEPTION_USE_CUSTOM_6 ))
420	msg += _("Invalid Exception.\n");
421
422	if ((inst->_event_type != EVENT_TYPE_NONE ) and
423	(inst->_event_type != EVENT_TYPE_SPR_ACCESS))
424	msg += _("Invalid Event_type.\n");
425
426	if (inst->_address_next != (inst->_address+1))
427	msg += _("Address must be in sequence.\n");
428
429	if (msg != "")
430	throw ERRORMORPHEO("instruction_custom","Invalid decod : "+msg);
431	}
432	}
433
434	// ORBIS
435	void instruction_l_add (decod_instruction_t * inst, decod_param_t * param)
436	{
437	log_printf(TRACE,Decod,"instruction_l_add"," * instruction : l.add");
438	#ifdef STATISTICS
439	inst->_opcod = INSTRUCTION_L_ADD;
440	#endif
441	inst->_type = instruction_information(INSTRUCTION_L_ADD)._type ; //TYPE_ALU;
442	inst->_operation = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD;
443	inst->_has_immediat = 0;
444	inst->_immediat = 0; // unnecessary
445	inst->_read_ra = 1;
446	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
447	inst->_read_rb = 1;
448	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
449	inst->_read_rc = 0;
450	inst->_num_reg_rc = 0; //unnecessary
451	inst->_write_rd = 1;
452	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
453	inst->_write_re = 1;
454	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
455	inst->_exception_use = EXCEPTION_USE_RANGE;
456	inst->_exception = EXCEPTION_DECOD_NONE;
457	// inst->_branch_condition = ;
458	// inst->_branch_stack_write = ;
459	// inst->_branch_direction = ;
460	// inst->_address_next = ; // already define : PC+4
461	inst->_no_execute = 0;
462	inst->_event_type = EVENT_TYPE_NONE;
463	}
464
465	void instruction_l_addc (decod_instruction_t * inst, decod_param_t * param)
466	{
467	log_printf(TRACE,Decod,"instruction_l_addc"," * instruction : l.addc");
468
469	#ifdef STATISTICS
470	inst->_opcod = INSTRUCTION_L_ADDC;
471	#endif
472	inst->_type = instruction_information(INSTRUCTION_L_ADDC)._type ; //TYPE_ALU;
473	inst->_operation = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD;
474	inst->_has_immediat = 0;
475	inst->_immediat = 0; // unnecessary
476	inst->_read_ra = 1;
477	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
478	inst->_read_rb = 1;
479	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
480	inst->_read_rc = 1;
481	inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV;
482	inst->_write_rd = 1;
483	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
484	inst->_write_re = 1;
485	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
486	inst->_exception_use = EXCEPTION_USE_RANGE;
487	inst->_exception = EXCEPTION_DECOD_NONE;
488	// inst->_branch_condition = ;
489	// inst->_branch_stack_write = ;
490	// inst->_branch_direction = ;
491	// inst->_address_next = ; // already define : PC+4
492	inst->_no_execute = 0;
493	inst->_event_type = EVENT_TYPE_NONE;
494	}
495
496	void instruction_l_addi (decod_instruction_t * inst, decod_param_t * param)
497	{
498	log_printf(TRACE,Decod,"instruction_l_addi"," * instruction : l.addi");
499
500	#ifdef STATISTICS
501	inst->_opcod = INSTRUCTION_L_ADDI;
502	#endif
503	inst->_type = instruction_information(INSTRUCTION_L_ADDI)._type ; //TYPE_ALU;
504	inst->_operation = instruction_information(INSTRUCTION_L_ADDI)._operation; //OPERATION_ALU_L_ADD;
505	inst->_has_immediat = 1;
506	inst->_immediat = EXTENDS(inst->_instruction,16);
507	inst->_read_ra = 1;
508	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
509	inst->_read_rb = 0;
510	inst->_num_reg_rb = 0; //unnecessary
511	inst->_read_rc = 0;
512	inst->_num_reg_rc = 0; //unnecessary
513	inst->_write_rd = 1;
514	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
515	inst->_write_re = 1;
516	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
517	inst->_exception_use = EXCEPTION_USE_RANGE;
518	inst->_exception = EXCEPTION_DECOD_NONE;
519	// inst->_branch_condition = ;
520	// inst->_branch_stack_write = ;
521	// inst->_branch_direction = ;
522	// inst->_address_next = ; // already define : PC+4
523	inst->_no_execute = 0;
524	inst->_event_type = EVENT_TYPE_NONE;
525	}
526
527	void instruction_l_addic (decod_instruction_t * inst, decod_param_t * param)
528	{
529	log_printf(TRACE,Decod,"instruction_l_addic"," * instruction : l.addic");
530
531	#ifdef STATISTICS
532	inst->_opcod = INSTRUCTION_L_ADDIC;
533	#endif
534	inst->_type = instruction_information(INSTRUCTION_L_ADDIC)._type ; //TYPE_ALU;
535	inst->_operation = instruction_information(INSTRUCTION_L_ADDIC)._operation; //OPERATION_ALU_L_ADD;
536	inst->_has_immediat = 1;
537	inst->_immediat = EXTENDS(inst->_instruction,16);
538	inst->_read_ra = 1;
539	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
540	inst->_read_rb = 0;
541	inst->_num_reg_rb = 0; //unnecessary
542	inst->_read_rc = 1;
543	inst->_num_reg_rc = SPR_LOGIC_SR_CY_OV;
544	inst->_write_rd = 1;
545	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
546	inst->_write_re = 1;
547	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
548	inst->_exception_use = EXCEPTION_USE_RANGE;
549	inst->_exception = EXCEPTION_DECOD_NONE;
550	// inst->_branch_condition = ;
551	// inst->_branch_stack_write = ;
552	// inst->_branch_direction = ;
553	// inst->_address_next = ; // already define : PC+4
554	inst->_no_execute = 0;
555	inst->_event_type = EVENT_TYPE_NONE;
556	}
557
558	void instruction_l_and (decod_instruction_t * inst, decod_param_t * param)
559	{
560	log_printf(TRACE,Decod,"instruction_l_and"," * instruction : l.and");
561
562	#ifdef STATISTICS
563	inst->_opcod = INSTRUCTION_L_AND;
564	#endif
565	inst->_type = instruction_information(INSTRUCTION_L_AND)._type ; //TYPE_ALU;
566	inst->_operation = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND;
567	inst->_has_immediat = 0;
568	inst->_immediat = 0; // unnecessary
569	inst->_read_ra = 1;
570	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
571	inst->_read_rb = 1;
572	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
573	inst->_read_rc = 0;
574	inst->_num_reg_rc = 0; //unnecessary
575	inst->_write_rd = 1;
576	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
577	inst->_write_re = 0;
578	inst->_num_reg_re = 0; //unnecessary
579	inst->_exception_use = EXCEPTION_USE_NONE;
580	inst->_exception = EXCEPTION_DECOD_NONE;
581	// inst->_branch_condition = ;
582	// inst->_branch_stack_write = ;
583	// inst->_branch_direction = ;
584	// inst->_address_next = ; // already define : PC+4
585	inst->_no_execute = 0;
586	inst->_event_type = EVENT_TYPE_NONE;
587	}
588
589	void instruction_l_andi (decod_instruction_t * inst, decod_param_t * param)
590	{
591	log_printf(TRACE,Decod,"instruction_l_andi"," * instruction : l.andi");
592
593	#ifdef STATISTICS
594	inst->_opcod = INSTRUCTION_L_ANDI;
595	#endif
596	inst->_type = instruction_information(INSTRUCTION_L_ANDI)._type ; //TYPE_ALU;
597	inst->_operation = instruction_information(INSTRUCTION_L_ANDI)._operation; //OPERATION_ALU_L_AND;
598	inst->_has_immediat = 1;
599	inst->_immediat = EXTENDZ(inst->_instruction,16);
600	inst->_read_ra = 1;
601	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
602	inst->_read_rb = 0;
603	inst->_num_reg_rb = 0; //unnecessary
604	inst->_read_rc = 0;
605	inst->_num_reg_rc = 0; //unnecessary
606	inst->_write_rd = 1;
607	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
608	inst->_write_re = 0;
609	inst->_num_reg_re = 0; //unnecessary
610	inst->_exception_use = EXCEPTION_USE_NONE;
611	inst->_exception = EXCEPTION_DECOD_NONE;
612	// inst->_branch_condition = ;
613	// inst->_branch_stack_write = ;
614	// inst->_branch_direction = ;
615	// inst->_address_next = ; // already define : PC+4
616	inst->_no_execute = 0;
617	inst->_event_type = EVENT_TYPE_NONE;
618	}
619
620	void instruction_l_bf (decod_instruction_t * inst, decod_param_t * param)
621	{
622	log_printf(TRACE,Decod,"instruction_l_bf"," * instruction : l.bf");
623
624	Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
625	);
626
627	#ifdef STATISTICS
628	inst->_opcod = INSTRUCTION_L_BF;
629	#endif
630	inst->_type = instruction_information(INSTRUCTION_L_BF)._type ; //TYPE_BRANCH;
631	inst->_operation = instruction_information(INSTRUCTION_L_BF)._operation; //OPERATION_BRANCH_L_TEST_F;
632	inst->_has_immediat = 1;
633	inst->_immediat = address_next;
634	inst->_read_ra = 0;
635	inst->_num_reg_ra = 0; //unnecessary
636	inst->_read_rb = 0;
637	inst->_num_reg_rb = 0; //unnecessary
638	inst->_read_rc = 1;
639	inst->_num_reg_rc = SPR_LOGIC_SR_F;
640	inst->_write_rd = 0;
641	inst->_num_reg_rd = 0; //unnecessary
642	inst->_write_re = 0;
643	inst->_num_reg_re = 0; //unnecessary
644	inst->_exception_use = EXCEPTION_USE_NONE;
645	inst->_exception = EXCEPTION_DECOD_NONE;
646	inst->_branch_condition = BRANCH_CONDITION_FLAG_SET;
647	// inst->_branch_stack_write = 0;
648
649	inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25);
650	inst->_address_next = address_next;
651	inst->_no_execute = 0;
652	inst->_event_type = EVENT_TYPE_NONE;
653	}
654
655	void instruction_l_bnf (decod_instruction_t * inst, decod_param_t * param)
656	{
657	log_printf(TRACE,Decod,"instruction_l_bnf"," * instruction : l.bnf");
658
659	Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
660	);
661
662	#ifdef STATISTICS
663	inst->_opcod = INSTRUCTION_L_BNF;
664	#endif
665	inst->_type = instruction_information(INSTRUCTION_L_BNF)._type ; //TYPE_BRANCH;
666	inst->_operation = instruction_information(INSTRUCTION_L_BNF)._operation; //OPERATION_BRANCH_L_TEST_NF;
667	inst->_has_immediat = 1;
668	inst->_immediat = address_next;
669	inst->_read_ra = 0;
670	inst->_num_reg_ra = 0; //unnecessary
671	inst->_read_rb = 0;
672	inst->_num_reg_rb = 0; //unnecessary
673	inst->_read_rc = 1;
674	inst->_num_reg_rc = SPR_LOGIC_SR_F;
675	inst->_write_rd = 0;
676	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
677	inst->_write_re = 0;
678	inst->_num_reg_re = 0; //unnecessary
679	inst->_exception_use = EXCEPTION_USE_NONE;
680	inst->_exception = EXCEPTION_DECOD_NONE;
681	inst->_branch_condition = BRANCH_CONDITION_FLAG_UNSET;
682	// inst->_branch_stack_write = 0;
683	inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25);
684	inst->_address_next = address_next;
685	inst->_no_execute = 0;
686	inst->_event_type = EVENT_TYPE_NONE;
687	}
688
689	void instruction_l_cmov (decod_instruction_t * inst, decod_param_t * param)
690	{
691	log_printf(TRACE,Decod,"instruction_l_cmov"," * instruction : l.cmov");
692
693	#ifdef STATISTICS
694	inst->_opcod = INSTRUCTION_L_CMOV;
695	#endif
696	inst->_type = instruction_information(INSTRUCTION_L_CMOV)._type ; //TYPE_MOVE;
697	inst->_operation = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV;
698	inst->_has_immediat = 0;
699	inst->_immediat = 0; // unnecessary
700	inst->_read_ra = 1;
701	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
702	inst->_read_rb = 1;
703	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
704	inst->_read_rc = 1;
705	inst->_num_reg_rc = SPR_LOGIC_SR_F;
706	inst->_write_rd = 1;
707	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
708	inst->_write_re = 0;
709	inst->_num_reg_re = 0; //unnecessary
710	inst->_exception_use = EXCEPTION_USE_NONE;
711	inst->_exception = EXCEPTION_DECOD_NONE;
712	// inst->_branch_condition = ;
713	// inst->_branch_stack_write = ;
714	// inst->_branch_direction = ;
715	// inst->_address_next = ; // already define : PC+4
716	inst->_no_execute = 0;
717	inst->_event_type = EVENT_TYPE_NONE;
718	}
719
720	void instruction_l_csync (decod_instruction_t * inst, decod_param_t * param)
721	{
722	log_printf(TRACE,Decod,"instruction_l_csync"," * instruction : l.csync");
723
724	if (range<Tinstruction_t>(inst->_instruction,23) != 0)
725	{
726	instruction_illegal (inst, param);
727	}
728	else
729	{
730	#ifdef STATISTICS
731	inst->_opcod = INSTRUCTION_L_CSYNC;
732	#endif
733	inst->_type = instruction_information(INSTRUCTION_L_CSYNC)._type ; //TYPE_SPECIAL;
734	inst->_operation = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC;
735	inst->_has_immediat = 0;
736	inst->_immediat = 0; // unnecessary
737	inst->_read_ra = 0;
738	inst->_num_reg_ra = 0; //unnecessary
739	inst->_read_rb = 0;
740	inst->_num_reg_rb = 0; //unnecessary
741	inst->_read_rc = 0;
742	inst->_num_reg_rc = 0; //unnecessary
743	inst->_write_rd = 0;
744	inst->_num_reg_rd = 0; //unnecessary
745	inst->_write_re = 0;
746	inst->_num_reg_re = 0; //unnecessary
747	inst->_exception_use = EXCEPTION_USE_NONE;
748	inst->_exception = EXCEPTION_DECOD_NONE;
749	// inst->_branch_condition = ;
750	// inst->_branch_stack_write = ;
751	// inst->_branch_direction = ;
752	// inst->_address_next = ; // already define : PC+4 // don't change
753	inst->_no_execute = 0;
754	inst->_event_type = EVENT_TYPE_CSYNC;
755	}
756	}
757
758	// void instruction_l_cust1 (decod_instruction_t * inst, decod_param_t * param)
759	// void instruction_l_cust2 (decod_instruction_t * inst, decod_param_t * param)
760	// void instruction_l_cust3 (decod_instruction_t * inst, decod_param_t * param)
761	// void instruction_l_cust4 (decod_instruction_t * inst, decod_param_t * param)
762	// void instruction_l_cust5 (decod_instruction_t * inst, decod_param_t * param)
763	// void instruction_l_cust6 (decod_instruction_t * inst, decod_param_t * param)
764	// void instruction_l_cust7 (decod_instruction_t * inst, decod_param_t * param)
765	// void instruction_l_cust8 (decod_instruction_t * inst, decod_param_t * param)
766
767	void instruction_l_div (decod_instruction_t * inst, decod_param_t * param)
768	{
769	log_printf(TRACE,Decod,"instruction_l_div"," * instruction : l.div");
770
771	#ifdef STATISTICS
772	inst->_opcod = INSTRUCTION_L_DIV;
773	#endif
774	inst->_type = instruction_information(INSTRUCTION_L_DIV)._type ; //TYPE_DIV;
775	inst->_operation = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV;
776	inst->_has_immediat = 0;
777	inst->_immediat = 0; // unnecessary
778	inst->_read_ra = 1;
779	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
780	inst->_read_rb = 1;
781	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
782	inst->_read_rc = 0;
783	inst->_num_reg_rc = 0; //unnecessary
784	inst->_write_rd = 1;
785	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
786	inst->_write_re = 1;
787	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
788	inst->_exception_use = EXCEPTION_USE_RANGE;
789	inst->_exception = EXCEPTION_DECOD_NONE;
790	// inst->_branch_condition = ;
791	// inst->_branch_stack_write = ;
792	// inst->_branch_direction = ;
793	// inst->_address_next = ; // already define : PC+4
794	inst->_no_execute = 0;
795	inst->_event_type = EVENT_TYPE_NONE;
796	}
797
798	void instruction_l_divu (decod_instruction_t * inst, decod_param_t * param)
799	{
800	log_printf(TRACE,Decod,"instruction_l_divu"," * instruction : l.divu");
801
802	#ifdef STATISTICS
803	inst->_opcod = INSTRUCTION_L_DIVU;
804	#endif
805	inst->_type = instruction_information(INSTRUCTION_L_DIVU)._type ; //TYPE_DIV;
806	inst->_operation = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU;
807	inst->_has_immediat = 0;
808	inst->_immediat = 0; // unnecessary
809	inst->_read_ra = 1;
810	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
811	inst->_read_rb = 1;
812	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
813	inst->_read_rc = 0;
814	inst->_num_reg_rc = 0; //unnecessary
815	inst->_write_rd = 1;
816	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
817	inst->_write_re = 1;
818	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
819	inst->_exception_use = EXCEPTION_USE_RANGE;
820	inst->_exception = EXCEPTION_DECOD_NONE;
821	// inst->_branch_condition = ;
822	// inst->_branch_stack_write = ;
823	// inst->_branch_direction = ;
824	// inst->_address_next = ; // already define : PC+4
825	inst->_no_execute = 0;
826	inst->_event_type = EVENT_TYPE_NONE;
827	}
828
829	void instruction_l_extbs (decod_instruction_t * inst, decod_param_t * param)
830	{
831	log_printf(TRACE,Decod,"instruction_l_extbs"," * instruction : l.extbs");
832
833	#ifdef STATISTICS
834	inst->_opcod = INSTRUCTION_L_EXTBS;
835	#endif
836	inst->_type = instruction_information(INSTRUCTION_L_EXTBS)._type ; //TYPE_EXTEND;
837	inst->_operation = instruction_information(INSTRUCTION_L_EXTBS)._operation; //OPERATION_EXTEND_L_EXTEND_S;
838	inst->_has_immediat = 1;
839	inst->_immediat = 8;
840	inst->_read_ra = 1;
841	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
842	inst->_read_rb = 0;
843	inst->_num_reg_rb = 0; //unnecessary
844	inst->_read_rc = 0;
845	inst->_num_reg_rc = 0; //unnecessary
846	inst->_write_rd = 1;
847	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
848	inst->_write_re = 0;
849	inst->_num_reg_re = 0; //unnecessary
850	inst->_exception_use = EXCEPTION_USE_NONE;
851	inst->_exception = EXCEPTION_DECOD_NONE;
852	// inst->_branch_condition = ;
853	// inst->_branch_stack_write = ;
854	// inst->_branch_direction = ;
855	// inst->_address_next = ; // already define : PC+4
856	inst->_no_execute = 0;
857	inst->_event_type = EVENT_TYPE_NONE;
858	}
859
860	void instruction_l_extbz (decod_instruction_t * inst, decod_param_t * param)
861	{
862	log_printf(TRACE,Decod,"instruction_l_extbz"," * instruction : l.extbz");
863
864	#ifdef STATISTICS
865	inst->_opcod = INSTRUCTION_L_EXTBZ;
866	#endif
867	inst->_type = instruction_information(INSTRUCTION_L_EXTBZ)._type ; //TYPE_EXTEND;
868	inst->_operation = instruction_information(INSTRUCTION_L_EXTBZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z;
869	inst->_has_immediat = 1;
870	inst->_immediat = 8;
871	inst->_read_ra = 1;
872	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
873	inst->_read_rb = 0;
874	inst->_num_reg_rb = 0; //unnecessary
875	inst->_read_rc = 0;
876	inst->_num_reg_rc = 0; //unnecessary
877	inst->_write_rd = 1;
878	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
879	inst->_write_re = 0;
880	inst->_num_reg_re = 0; //unnecessary
881	inst->_exception_use = EXCEPTION_USE_NONE;
882	inst->_exception = EXCEPTION_DECOD_NONE;
883	// inst->_branch_condition = ;
884	// inst->_branch_stack_write = ;
885	// inst->_branch_direction = ;
886	// inst->_address_next = ; // already define : PC+4
887	inst->_no_execute = 0;
888	inst->_event_type = EVENT_TYPE_NONE;
889	}
890
891	void instruction_l_exths (decod_instruction_t * inst, decod_param_t * param)
892	{
893	log_printf(TRACE,Decod,"instruction_l_exths"," * instruction : l.exths");
894
895	#ifdef STATISTICS
896	inst->_opcod = INSTRUCTION_L_EXTHS;
897	#endif
898	inst->_type = instruction_information(INSTRUCTION_L_EXTHS)._type ; //TYPE_EXTEND;
899	inst->_operation = instruction_information(INSTRUCTION_L_EXTHS)._operation; //OPERATION_EXTEND_L_EXTEND_S;
900	inst->_has_immediat = 1;
901	inst->_immediat = 16;
902	inst->_read_ra = 1;
903	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
904	inst->_read_rb = 0;
905	inst->_num_reg_rb = 0; //unnecessary
906	inst->_read_rc = 0;
907	inst->_num_reg_rc = 0; //unnecessary
908	inst->_write_rd = 1;
909	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
910	inst->_write_re = 0;
911	inst->_num_reg_re = 0; //unnecessary
912	inst->_exception_use = EXCEPTION_USE_NONE;
913	inst->_exception = EXCEPTION_DECOD_NONE;
914	// inst->_branch_condition = ;
915	// inst->_branch_stack_write = ;
916	// inst->_branch_direction = ;
917	// inst->_address_next = ; // already define : PC+4
918	inst->_no_execute = 0;
919	inst->_event_type = EVENT_TYPE_NONE;
920	}
921
922	void instruction_l_exthz (decod_instruction_t * inst, decod_param_t * param)
923	{
924	log_printf(TRACE,Decod,"instruction_l_exthz"," * instruction : l.exthz");
925
926	#ifdef STATISTICS
927	inst->_opcod = INSTRUCTION_L_EXTHZ;
928	#endif
929	inst->_type = instruction_information(INSTRUCTION_L_EXTHZ)._type ; //TYPE_EXTEND;
930	inst->_operation = instruction_information(INSTRUCTION_L_EXTHZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z;
931	inst->_has_immediat = 1;
932	inst->_immediat = 16;
933	inst->_read_ra = 1;
934	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
935	inst->_read_rb = 0;
936	inst->_num_reg_rb = 0; //unnecessary
937	inst->_read_rc = 0;
938	inst->_num_reg_rc = 0; //unnecessary
939	inst->_write_rd = 1;
940	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
941	inst->_write_re = 0;
942	inst->_num_reg_re = 0; //unnecessary
943	inst->_exception_use = EXCEPTION_USE_NONE;
944	inst->_exception = EXCEPTION_DECOD_NONE;
945	// inst->_branch_condition = ;
946	// inst->_branch_stack_write = ;
947	// inst->_branch_direction = ;
948	// inst->_address_next = ; // already define : PC+4
949	inst->_no_execute = 0;
950	inst->_event_type = EVENT_TYPE_NONE;
951	}
952
953	void instruction_l_extws (decod_instruction_t * inst, decod_param_t * param)
954	{
955	log_printf(TRACE,Decod,"instruction_l_extws"," * instruction : l.extws");
956
957	#ifdef STATISTICS
958	inst->_opcod = INSTRUCTION_L_EXTWS;
959	#endif
960	inst->_type = instruction_information(INSTRUCTION_L_EXTWS)._type ; //TYPE_EXTEND;
961	inst->_operation = instruction_information(INSTRUCTION_L_EXTWS)._operation; //OPERATION_EXTEND_L_EXTEND_S;
962	inst->_has_immediat = 1;
963	inst->_immediat = 32;
964	inst->_read_ra = 1;
965	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
966	inst->_read_rb = 0;
967	inst->_num_reg_rb = 0; //unnecessary
968	inst->_read_rc = 0;
969	inst->_num_reg_rc = 0; //unnecessary
970	inst->_write_rd = 1;
971	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
972	inst->_write_re = 0;
973	inst->_num_reg_re = 0; //unnecessary
974	inst->_exception_use = EXCEPTION_USE_NONE;
975	inst->_exception = EXCEPTION_DECOD_NONE;
976	// inst->_branch_condition = ;
977	// inst->_branch_stack_write = ;
978	// inst->_branch_direction = ;
979	// inst->_address_next = ; // already define : PC+4
980	inst->_no_execute = 0;
981	inst->_event_type = EVENT_TYPE_NONE;
982	}
983
984	void instruction_l_extwz (decod_instruction_t * inst, decod_param_t * param)
985	{
986	log_printf(TRACE,Decod,"instruction_l_extwz"," * instruction : l.extwz");
987
988	#ifdef STATISTICS
989	inst->_opcod = INSTRUCTION_L_EXTWZ;
990	#endif
991	inst->_type = instruction_information(INSTRUCTION_L_EXTWZ)._type ; //TYPE_EXTEND;
992	inst->_operation = instruction_information(INSTRUCTION_L_EXTWZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z;
993	inst->_has_immediat = 1;
994	inst->_immediat = 32;
995	inst->_read_ra = 1;
996	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
997	inst->_read_rb = 0;
998	inst->_num_reg_rb = 0; //unnecessary
999	inst->_read_rc = 0;
1000	inst->_num_reg_rc = 0; //unnecessary
1001	inst->_write_rd = 1;
1002	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1003	inst->_write_re = 0;
1004	inst->_num_reg_re = 0; //unnecessary
1005	inst->_exception_use = EXCEPTION_USE_NONE;
1006	inst->_exception = EXCEPTION_DECOD_NONE;
1007	// inst->_branch_condition = ;
1008	// inst->_branch_stack_write = ;
1009	// inst->_branch_direction = ;
1010	// inst->_address_next = ; // already define : PC+4
1011	inst->_no_execute = 0;
1012	inst->_event_type = EVENT_TYPE_NONE;
1013	}
1014
1015	void instruction_l_ff1 (decod_instruction_t * inst, decod_param_t * param)
1016	{
1017	log_printf(TRACE,Decod,"instruction_l_ff1"," * instruction : l.ff1");
1018
1019	#ifdef STATISTICS
1020	inst->_opcod = INSTRUCTION_L_FF1;
1021	#endif
1022	inst->_type = instruction_information(INSTRUCTION_L_FF1)._type ; //TYPE_FIND;
1023	inst->_operation = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1;
1024	inst->_has_immediat = 0;
1025	inst->_immediat = 0; // unnecessary
1026	inst->_read_ra = 1;
1027	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1028	inst->_read_rb = 0;
1029	inst->_num_reg_rb = 0; //unnecessary
1030	inst->_read_rc = 0;
1031	inst->_num_reg_rc = 0; //unnecessary
1032	inst->_write_rd = 1;
1033	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1034	inst->_write_re = 0;
1035	inst->_num_reg_re = 0; //unnecessary
1036	inst->_exception_use = EXCEPTION_USE_NONE;
1037	inst->_exception = EXCEPTION_DECOD_NONE;
1038	// inst->_branch_condition = ;
1039	// inst->_branch_stack_write = ;
1040	// inst->_branch_direction = ;
1041	// inst->_address_next = ; // already define : PC+4
1042	inst->_no_execute = 0;
1043	inst->_event_type = EVENT_TYPE_NONE;
1044	}
1045
1046	void instruction_l_fl1 (decod_instruction_t * inst, decod_param_t * param)
1047	{
1048	log_printf(TRACE,Decod,"instruction_l_fl1"," * instruction : l.fl1");
1049
1050	#ifdef STATISTICS
1051	inst->_opcod = INSTRUCTION_L_FL1;
1052	#endif
1053	inst->_type = instruction_information(INSTRUCTION_L_FL1)._type ; //TYPE_FIND;
1054	inst->_operation = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1;
1055	inst->_has_immediat = 0;
1056	inst->_immediat = 0; // unnecessary
1057	inst->_read_ra = 1;
1058	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1059	inst->_read_rb = 0;
1060	inst->_num_reg_rb = 0; //unnecessary
1061	inst->_read_rc = 0;
1062	inst->_num_reg_rc = 0; //unnecessary
1063	inst->_write_rd = 1;
1064	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1065	inst->_write_re = 0;
1066	inst->_num_reg_re = 0; //unnecessary
1067	inst->_exception_use = EXCEPTION_USE_NONE;
1068	inst->_exception = EXCEPTION_DECOD_NONE;
1069	// inst->_branch_condition = ;
1070	// inst->_branch_stack_write = ;
1071	// inst->_branch_direction = ;
1072	// inst->_address_next = ; // already define : PC+4
1073	inst->_no_execute = 0;
1074	inst->_event_type = EVENT_TYPE_NONE;
1075	}
1076
1077	void instruction_l_j (decod_instruction_t * inst, decod_param_t * param)
1078	{
1079	log_printf(TRACE,Decod,"instruction_l_j"," * instruction : l.j");
1080
1081	#ifdef STATISTICS
1082	inst->_opcod = INSTRUCTION_L_J;
1083	#endif
1084	inst->_type = instruction_information(INSTRUCTION_L_J)._type ; //TYPE_BRANCH;
1085	inst->_operation = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE;
1086	inst->_has_immediat = 0;
1087	inst->_immediat = 0; // unnecessary
1088	inst->_read_ra = 0;
1089	inst->_num_reg_ra = 0; //unnecessary
1090	inst->_read_rb = 0;
1091	inst->_num_reg_rb = 0; //unnecessary
1092	inst->_read_rc = 0;
1093	inst->_num_reg_rc = 0; //unnecessary
1094	inst->_write_rd = 0;
1095	inst->_num_reg_rd = 0; //unnecessary
1096	inst->_write_re = 0;
1097	inst->_num_reg_re = 0; //unnecessary
1098	inst->_exception_use = EXCEPTION_USE_NONE;
1099	inst->_exception = EXCEPTION_DECOD_NONE;
1100	inst->_branch_condition = BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK;
1101	// inst->_branch_stack_write = 0;
1102	inst->_branch_direction = 1;
1103	inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
1104	);
1105	inst->_no_execute = 1;
1106	inst->_event_type = EVENT_TYPE_NONE;
1107	}
1108
1109	void instruction_l_jal (decod_instruction_t * inst, decod_param_t * param)
1110	{
1111	log_printf(TRACE,Decod,"instruction_l_jal"," * instruction : l.jal");
1112
1113	#ifdef STATISTICS
1114	inst->_opcod = INSTRUCTION_L_JAL;
1115	#endif
1116	inst->_type = instruction_information(INSTRUCTION_L_JAL)._type ; //TYPE_BRANCH;
1117	inst->_operation = instruction_information(INSTRUCTION_L_JAL)._operation; //OPERATION_BRANCH_L_JALR;
1118	inst->_has_immediat = 1;
1119	inst->_immediat = inst->_address_next+1;
1120	inst->_read_ra = 0;
1121	inst->_num_reg_ra = 0; //unnecessary
1122	inst->_read_rb = 0;
1123	inst->_num_reg_rb = 0; //unnecessary
1124	inst->_read_rc = 0;
1125	inst->_num_reg_rc = 0; //unnecessary
1126	inst->_write_rd = 1;
1127	inst->_num_reg_rd = 9; // Link register
1128	inst->_write_re = 0;
1129	inst->_num_reg_re = 0; //unnecessary
1130	inst->_exception_use = EXCEPTION_USE_NONE;
1131	inst->_exception = EXCEPTION_DECOD_NONE;
1132	inst->_branch_condition = BRANCH_CONDITION_NONE_WITH_WRITE_STACK; // Always jump
1133	// inst->_branch_stack_write = 1;
1134	inst->_branch_direction = 1;
1135	inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2
1136	);
1137	inst->_no_execute = 0;
1138	inst->_event_type = EVENT_TYPE_NONE;
1139	}
1140
1141	void instruction_l_jalr (decod_instruction_t * inst, decod_param_t * param)
1142	{
1143	log_printf(TRACE,Decod,"instruction_l_jalr"," * instruction : l.jalr");
1144
1145	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1146
1147	if (inst->_num_reg_rb == 9)
1148	{
1149	instruction_illegal (inst, param);
1150	}
1151	else
1152	{
1153	#ifdef STATISTICS
1154	inst->_opcod = INSTRUCTION_L_JALR;
1155	#endif
1156	inst->_type = instruction_information(INSTRUCTION_L_JALR)._type ; //TYPE_BRANCH;
1157	inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR;
1158	inst->_has_immediat = 1;
1159	inst->_immediat = inst->_address_next+1;
1160	inst->_read_ra = 0;
1161	inst->_num_reg_ra = 0; //unnecessary
1162	inst->_read_rb = 1;
1163	// inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1164	inst->_read_rc = 0;
1165	inst->_num_reg_rc = 0; //unnecessary
1166	inst->_write_rd = 1;
1167	inst->_num_reg_rd = 9; // Link register
1168	inst->_write_re = 0;
1169	inst->_num_reg_re = 0; //unnecessary
1170	inst->_exception_use = EXCEPTION_USE_NONE;
1171	inst->_exception = EXCEPTION_DECOD_NONE;
1172	// inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER;
1173	inst->_branch_condition = BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK;
1174	// inst->_branch_stack_write = 1;
1175	inst->_branch_direction = 1;
1176	// inst->_address_next = ; // already define : PC+4
1177	inst->_no_execute = 0;
1178	inst->_event_type = EVENT_TYPE_NONE;
1179	}
1180	}
1181
1182	void instruction_l_jr (decod_instruction_t * inst, decod_param_t * param)
1183	{
1184	log_printf(TRACE,Decod,"instruction_l_jr"," * instruction : l.jr");
1185
1186	#ifdef STATISTICS
1187	inst->_opcod = INSTRUCTION_L_JR;
1188	#endif
1189	inst->_type = instruction_information(INSTRUCTION_L_JR)._type ; //TYPE_BRANCH;
1190	inst->_operation = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR;
1191	inst->_has_immediat = 0;
1192	inst->_immediat = 0; // unnecessary
1193	inst->_read_ra = 0;
1194	inst->_num_reg_ra = 0; //unnecessary
1195	inst->_read_rb = 1;
1196	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1197	inst->_read_rc = 0;
1198	inst->_num_reg_rc = 0; //unnecessary
1199	inst->_write_rd = 0;
1200	inst->_num_reg_rd = 0; //unnecessary
1201	inst->_write_re = 0;
1202	inst->_num_reg_re = 0; //unnecessary
1203	inst->_exception_use = EXCEPTION_USE_NONE;
1204	inst->_exception = EXCEPTION_DECOD_NONE;
1205	inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK;
1206	// inst->_branch_stack_write = 0;
1207	inst->_branch_direction = 1;
1208	// inst->_address_next = ; // already define : PC+4
1209	inst->_no_execute = 0;
1210	inst->_event_type = EVENT_TYPE_NONE;
1211	}
1212
1213	void instruction_l_lbs (decod_instruction_t * inst, decod_param_t * param)
1214	{
1215	log_printf(TRACE,Decod,"instruction_l_lbs"," * instruction : l.lbs");
1216
1217	#ifdef STATISTICS
1218	inst->_opcod = INSTRUCTION_L_LBS;
1219	#endif
1220	inst->_type = instruction_information(INSTRUCTION_L_LBS)._type ; //TYPE_MEMORY;
1221	inst->_operation = instruction_information(INSTRUCTION_L_LBS)._operation; //OPERATION_MEMORY_LOAD_8_S;
1222	inst->_has_immediat = 1;
1223	inst->_immediat = EXTENDS(inst->_instruction,16);
1224	inst->_read_ra = 1;
1225	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1226	inst->_read_rb = 0;
1227	inst->_num_reg_rb = 0; //unnecessary
1228	inst->_read_rc = 0;
1229	inst->_num_reg_rc = 0; //unnecessary
1230	inst->_write_rd = 1;
1231	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1232	inst->_write_re = 0;
1233	inst->_num_reg_re = 0; //unnecessary
1234	inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
1235	inst->_exception = EXCEPTION_DECOD_NONE;
1236	// inst->_branch_condition = ;
1237	// inst->_branch_stack_write = ;
1238	// inst->_branch_direction = ;
1239	// inst->_address_next = ; // already define : PC+4
1240	inst->_no_execute = 0;
1241	inst->_event_type = EVENT_TYPE_NONE;
1242	}
1243
1244	void instruction_l_lbz (decod_instruction_t * inst, decod_param_t * param)
1245	{
1246	log_printf(TRACE,Decod,"instruction_l_lbz"," * instruction : l.lbz");
1247
1248	#ifdef STATISTICS
1249	inst->_opcod = INSTRUCTION_L_LBZ;
1250	#endif
1251	inst->_type = instruction_information(INSTRUCTION_L_LBZ)._type ; //TYPE_MEMORY;
1252	inst->_operation = instruction_information(INSTRUCTION_L_LBZ)._operation; //OPERATION_MEMORY_LOAD_8_Z;
1253	inst->_has_immediat = 1;
1254	inst->_immediat = EXTENDS(inst->_instruction,16);
1255	inst->_read_ra = 1;
1256	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1257	inst->_read_rb = 0;
1258	inst->_num_reg_rb = 0; //unnecessary
1259	inst->_read_rc = 0;
1260	inst->_num_reg_rc = 0; //unnecessary
1261	inst->_write_rd = 1;
1262	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1263	inst->_write_re = 0;
1264	inst->_num_reg_re = 0; //unnecessary
1265	inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
1266	inst->_exception = EXCEPTION_DECOD_NONE;
1267	// inst->_branch_condition = ;
1268	// inst->_branch_stack_write = ;
1269	// inst->_branch_direction = ;
1270	// inst->_address_next = ; // already define : PC+4
1271	inst->_no_execute = 0;
1272	inst->_event_type = EVENT_TYPE_NONE;
1273	}
1274
1275	void instruction_l_ld (decod_instruction_t * inst, decod_param_t * param)
1276	{
1277	log_printf(TRACE,Decod,"instruction_l_ld"," * instruction : l.ld");
1278
1279	#ifdef STATISTICS
1280	inst->_opcod = INSTRUCTION_L_LD;
1281	#endif
1282	inst->_type = instruction_information(INSTRUCTION_L_LD)._type ; //TYPE_MEMORY;
1283	inst->_operation = instruction_information(INSTRUCTION_L_LD)._operation; //OPERATION_MEMORY_LOAD_64_S;
1284	inst->_has_immediat = 1;
1285	inst->_immediat = EXTENDS(inst->_instruction,16);
1286	inst->_read_ra = 1;
1287	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1288	inst->_read_rb = 0;
1289	inst->_num_reg_rb = 0; //unnecessary
1290	inst->_read_rc = 0;
1291	inst->_num_reg_rc = 0; //unnecessary
1292	inst->_write_rd = 1;
1293	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1294	inst->_write_re = 0;
1295	inst->_num_reg_re = 0; //unnecessary
1296	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1297	inst->_exception = EXCEPTION_DECOD_NONE;
1298	// inst->_branch_condition = ;
1299	// inst->_branch_stack_write = ;
1300	// inst->_branch_direction = ;
1301	// inst->_address_next = ; // already define : PC+4
1302	inst->_no_execute = 0;
1303	inst->_event_type = EVENT_TYPE_NONE;
1304	}
1305
1306	void instruction_l_lhs (decod_instruction_t * inst, decod_param_t * param)
1307	{
1308	log_printf(TRACE,Decod,"instruction_l_lhs"," * instruction : l.lhs");
1309
1310	#ifdef STATISTICS
1311	inst->_opcod = INSTRUCTION_L_LHS;
1312	#endif
1313	inst->_type = instruction_information(INSTRUCTION_L_LHS)._type ; //TYPE_MEMORY;
1314	inst->_operation = instruction_information(INSTRUCTION_L_LHS)._operation; //OPERATION_MEMORY_LOAD_16_S;
1315	inst->_has_immediat = 1;
1316	inst->_immediat = EXTENDS(inst->_instruction,16);
1317	inst->_read_ra = 1;
1318	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1319	inst->_read_rb = 0;
1320	inst->_num_reg_rb = 0; //unnecessary
1321	inst->_read_rc = 0;
1322	inst->_num_reg_rc = 0; //unnecessary
1323	inst->_write_rd = 1;
1324	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1325	inst->_write_re = 0;
1326	inst->_num_reg_re = 0; //unnecessary
1327	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1328	inst->_exception = EXCEPTION_DECOD_NONE;
1329	// inst->_branch_condition = ;
1330	// inst->_branch_stack_write = ;
1331	// inst->_branch_direction = ;
1332	// inst->_address_next = ; // already define : PC+4
1333	inst->_no_execute = 0;
1334	inst->_event_type = EVENT_TYPE_NONE;
1335	}
1336
1337	void instruction_l_lhz (decod_instruction_t * inst, decod_param_t * param)
1338	{
1339	log_printf(TRACE,Decod,"instruction_l_lhz"," * instruction : l.lhz");
1340
1341	#ifdef STATISTICS
1342	inst->_opcod = INSTRUCTION_L_LHZ;
1343	#endif
1344	inst->_type = instruction_information(INSTRUCTION_L_LHZ)._type ; //TYPE_MEMORY;
1345	inst->_operation = instruction_information(INSTRUCTION_L_LHZ)._operation; //OPERATION_MEMORY_LOAD_16_Z;
1346	inst->_has_immediat = 1;
1347	inst->_immediat = EXTENDS(inst->_instruction,16);
1348	inst->_read_ra = 1;
1349	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1350	inst->_read_rb = 0;
1351	inst->_num_reg_rb = 0; //unnecessary
1352	inst->_read_rc = 0;
1353	inst->_num_reg_rc = 0; //unnecessary
1354	inst->_write_rd = 1;
1355	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1356	inst->_write_re = 0;
1357	inst->_num_reg_re = 0; //unnecessary
1358	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1359	inst->_exception = EXCEPTION_DECOD_NONE;
1360	// inst->_branch_condition = ;
1361	// inst->_branch_stack_write = ;
1362	// inst->_branch_direction = ;
1363	// inst->_address_next = ; // already define : PC+4
1364	inst->_no_execute = 0;
1365	inst->_event_type = EVENT_TYPE_NONE;
1366	}
1367
1368	void instruction_l_lws (decod_instruction_t * inst, decod_param_t * param)
1369	{
1370	log_printf(TRACE,Decod,"instruction_l_lws"," * instruction : l.lws");
1371
1372	#ifdef STATISTICS
1373	inst->_opcod = INSTRUCTION_L_LWS;
1374	#endif
1375	inst->_type = instruction_information(INSTRUCTION_L_LWS)._type ; //TYPE_MEMORY;
1376	inst->_operation = instruction_information(INSTRUCTION_L_LWS)._operation; //OPERATION_MEMORY_LOAD_32_S;
1377	inst->_has_immediat = 1;
1378	inst->_immediat = EXTENDS(inst->_instruction,16);
1379	inst->_read_ra = 1;
1380	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1381	inst->_read_rb = 0;
1382	inst->_num_reg_rb = 0; //unnecessary
1383	inst->_read_rc = 0;
1384	inst->_num_reg_rc = 0; //unnecessary
1385	inst->_write_rd = 1;
1386	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1387	inst->_write_re = 0;
1388	inst->_num_reg_re = 0; //unnecessary
1389	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1390	inst->_exception = EXCEPTION_DECOD_NONE;
1391	// inst->_branch_condition = ;
1392	// inst->_branch_stack_write = ;
1393	// inst->_branch_direction = ;
1394	// inst->_address_next = ; // already define : PC+4
1395	inst->_no_execute = 0;
1396	inst->_event_type = EVENT_TYPE_NONE;
1397	}
1398
1399	void instruction_l_lwz (decod_instruction_t * inst, decod_param_t * param)
1400	{
1401	log_printf(TRACE,Decod,"instruction_l_lwz"," * instruction : l.lwz");
1402
1403	#ifdef STATISTICS
1404	inst->_opcod = INSTRUCTION_L_LWZ;
1405	#endif
1406	inst->_type = instruction_information(INSTRUCTION_L_LWZ)._type ; //TYPE_MEMORY;
1407	inst->_operation = instruction_information(INSTRUCTION_L_LWZ)._operation; //OPERATION_MEMORY_LOAD_32_Z;
1408	inst->_has_immediat = 1;
1409	inst->_immediat = EXTENDS(inst->_instruction,16);
1410	inst->_read_ra = 1;
1411	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1412	inst->_read_rb = 0;
1413	inst->_num_reg_rb = 0; //unnecessary
1414	inst->_read_rc = 0;
1415	inst->_num_reg_rc = 0; //unnecessary
1416	inst->_write_rd = 1;
1417	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1418	inst->_write_re = 0;
1419	inst->_num_reg_re = 0; //unnecessary
1420	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
1421	inst->_exception = EXCEPTION_DECOD_NONE;
1422	// inst->_branch_condition = ;
1423	// inst->_branch_stack_write = ;
1424	// inst->_branch_direction = ;
1425	// inst->_address_next = ; // already define : PC+4
1426	inst->_no_execute = 0;
1427	inst->_event_type = EVENT_TYPE_NONE;
1428	}
1429
1430	void instruction_l_mac (decod_instruction_t * inst, decod_param_t * param)
1431	{
1432	log_printf(TRACE,Decod,"instruction_l_mac"," * instruction : l.mac");
1433
1434	#ifdef STATISTICS
1435	inst->_opcod = INSTRUCTION_L_MAC;
1436	#endif
1437	inst->_type = instruction_information(INSTRUCTION_L_MAC)._type ; //TYPE_SPECIAL;
1438	inst->_operation = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC;
1439	inst->_has_immediat = 0;
1440	inst->_immediat = 0; // unnecessary
1441	inst->_read_ra = 1;
1442	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1443	inst->_read_rb = 1;
1444	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1445	inst->_read_rc = 0;
1446	inst->_num_reg_rc = 0; //unnecessary
1447	inst->_write_rd = 0;
1448	inst->_num_reg_rd = 0; //unnecessary
1449	inst->_write_re = 0;
1450	inst->_num_reg_re = 0; //unnecessary
1451	inst->_exception_use = EXCEPTION_USE_NONE;
1452	inst->_exception = EXCEPTION_DECOD_NONE;
1453	// inst->_branch_condition = ;
1454	// inst->_branch_stack_write = ;
1455	// inst->_branch_direction = ;
1456	// inst->_address_next = ; // already define : PC+4 // don't change
1457	inst->_no_execute = 0;
1458	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1459	}
1460
1461	void instruction_l_maci (decod_instruction_t * inst, decod_param_t * param)
1462	{
1463	log_printf(TRACE,Decod,"instruction_l_maci"," * instruction : l.maci");
1464
1465	#ifdef STATISTICS
1466	inst->_opcod = INSTRUCTION_L_MACI;
1467	#endif
1468	inst->_type = instruction_information(INSTRUCTION_L_MACI)._type ; //TYPE_SPECIAL;
1469	inst->_operation = instruction_information(INSTRUCTION_L_MACI)._operation; //OPERATION_SPECIAL_L_MAC;
1470	inst->_has_immediat = 1;
1471	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
1472	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
1473	inst->_read_ra = 1;
1474	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1475	inst->_read_rb = 0;
1476	inst->_num_reg_rb = 0; //unnecessary
1477	inst->_read_rc = 0;
1478	inst->_num_reg_rc = 0; //unnecessary
1479	inst->_write_rd = 0;
1480	inst->_num_reg_rd = 0; //unnecessary
1481	inst->_write_re = 0;
1482	inst->_num_reg_re = 0; //unnecessary
1483	inst->_exception_use = EXCEPTION_USE_NONE;
1484	inst->_exception = EXCEPTION_DECOD_NONE;
1485	// inst->_branch_condition = ;
1486	// inst->_branch_stack_write = ;
1487	// inst->_branch_direction = ;
1488	// inst->_address_next = ; // already define : PC+4 // don't change
1489	inst->_no_execute = 0;
1490	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1491	}
1492
1493	void instruction_l_macrc (decod_instruction_t * inst, decod_param_t * param)
1494	{
1495	log_printf(TRACE,Decod,"instruction_l_macrc"," * instruction : l.macrc");
1496
1497	if (range<uint32_t>(inst->_instruction,15, 0) != 0)
1498	{
1499	instruction_illegal (inst, param);
1500	}
1501	else
1502	{
1503	#ifdef STATISTICS
1504	inst->_opcod = INSTRUCTION_L_MACRC;
1505	#endif
1506	inst->_type = instruction_information(INSTRUCTION_L_MACRC)._type ; //TYPE_SPECIAL;
1507	inst->_operation = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC;
1508	inst->_has_immediat = 0;
1509	inst->_immediat = 0; // unnecessary
1510	inst->_read_ra = 0;
1511	inst->_num_reg_ra = 0; //unnecessary
1512	inst->_read_rb = 0;
1513	inst->_num_reg_rb = 0; //unnecessary
1514	inst->_read_rc = 0;
1515	inst->_num_reg_rc = 0; //unnecessary
1516	inst->_write_rd = 1;
1517	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1518	inst->_write_re = 0;
1519	inst->_num_reg_re = 0; //unnecessary
1520	inst->_exception_use = EXCEPTION_USE_NONE;
1521	inst->_exception = EXCEPTION_DECOD_NONE;
1522	// inst->_branch_condition = ;
1523	// inst->_branch_stack_write = ;
1524	// inst->_branch_direction = ;
1525	// inst->_address_next = ; // already define : PC+4 // don't change
1526	inst->_no_execute = 0;
1527	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1528	}
1529	}
1530
1531	void instruction_l_mfspr (decod_instruction_t * inst, decod_param_t * param)
1532	{
1533	log_printf(TRACE,Decod,"instruction_l_mfspr"," * instruction : l.mfspr");
1534
1535	#ifdef STATISTICS
1536	inst->_opcod = INSTRUCTION_L_MFSPR;
1537	#endif
1538	inst->_type = instruction_information(INSTRUCTION_L_MFSPR)._type ; //TYPE_SPECIAL;
1539	inst->_operation = instruction_information(INSTRUCTION_L_MFSPR)._operation; //OPERATION_SPECIAL_L_MFSPR;
1540	inst->_has_immediat = 1;
1541	inst->_immediat = EXTENDZ(inst->_instruction,16);
1542	inst->_read_ra = 1;
1543	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1544	inst->_read_rb = 0;
1545	inst->_num_reg_rb = 0; //unnecessary
1546	inst->_read_rc = 0;
1547	inst->_num_reg_rc = 0; //unnecessary
1548	inst->_write_rd = 1;
1549	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1550	inst->_write_re = 0;
1551	inst->_num_reg_re = 0; //unnecessary
1552	inst->_exception_use = EXCEPTION_USE_NONE;
1553	inst->_exception = EXCEPTION_DECOD_NONE;
1554	// inst->_branch_condition = ;
1555	// inst->_branch_stack_write = ;
1556	// inst->_branch_direction = ;
1557	// inst->_address_next = ; // already define : PC+4 // don't change
1558	inst->_no_execute = 0;
1559	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1560	}
1561
1562	void instruction_l_movhi (decod_instruction_t * inst, decod_param_t * param)
1563	{
1564	log_printf(TRACE,Decod,"instruction_l_movhi"," * instruction : l.movhi");
1565
1566	#ifdef STATISTICS
1567	inst->_opcod = INSTRUCTION_L_MOVHI;
1568	#endif
1569	inst->_type = instruction_information(INSTRUCTION_L_MOVHI)._type ; //TYPE_MOVE;
1570	inst->_operation = instruction_information(INSTRUCTION_L_MOVHI)._operation; //OPERATION_MOVE_L_MOVHI;
1571	inst->_has_immediat = 1;
1572	inst->_immediat = EXTENDZ(inst->_instruction,16);
1573	inst->_read_ra = 0;
1574	inst->_num_reg_ra = 0; //unnecessary
1575	inst->_read_rb = 0;
1576	inst->_num_reg_rb = 0; //unnecessary
1577	inst->_read_rc = 0;
1578	inst->_num_reg_rc = 0; //unnecessary
1579	inst->_write_rd = 1;
1580	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1581	inst->_write_re = 0;
1582	inst->_num_reg_re = 0; //unnecessary
1583	inst->_exception_use = EXCEPTION_USE_NONE;
1584	inst->_exception = EXCEPTION_DECOD_NONE;
1585	// inst->_branch_condition = ;
1586	// inst->_branch_stack_write = ;
1587	// inst->_branch_direction = ;
1588	// inst->_address_next = ; // already define : PC+4
1589	inst->_no_execute = 0;
1590	inst->_event_type = EVENT_TYPE_NONE;
1591	}
1592
1593	void instruction_l_msb (decod_instruction_t * inst, decod_param_t * param)
1594	{
1595	log_printf(TRACE,Decod,"instruction_l_msb"," * instruction : l.msb");
1596
1597	#ifdef STATISTICS
1598	inst->_opcod = INSTRUCTION_L_MSB;
1599	#endif
1600	inst->_type = instruction_information(INSTRUCTION_L_MSB)._type ; //TYPE_SPECIAL;
1601	inst->_operation = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB;
1602	inst->_has_immediat = 0;
1603	inst->_immediat = 0; // unnecessary
1604	inst->_read_ra = 1;
1605	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1606	inst->_read_rb = 1;
1607	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1608	inst->_read_rc = 0;
1609	inst->_num_reg_rc = 0; //unnecessary
1610	inst->_write_rd = 0;
1611	inst->_num_reg_rd = 0; //unnecessary
1612	inst->_write_re = 0;
1613	inst->_num_reg_re = 0; //unnecessary
1614	inst->_exception_use = EXCEPTION_USE_NONE;
1615	inst->_exception = EXCEPTION_DECOD_NONE;
1616	// inst->_branch_condition = ;
1617	// inst->_branch_stack_write = ;
1618	// inst->_branch_direction = ;
1619	// inst->_address_next = ; // already define : PC+4 // don't change
1620	inst->_no_execute = 0;
1621	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1622	}
1623
1624	void instruction_l_msync (decod_instruction_t * inst, decod_param_t * param)
1625	{
1626	log_printf(TRACE,Decod,"instruction_l_msync"," * instruction : l.msync");
1627
1628	if (range<uint32_t>(inst->_instruction,22, 0) != 0)
1629	{
1630	instruction_illegal (inst, param);
1631	}
1632	else
1633	{
1634	#ifdef STATISTICS
1635	inst->_opcod = INSTRUCTION_L_MSYNC;
1636	#endif
1637	inst->_type = instruction_information(INSTRUCTION_L_MSYNC)._type ; //TYPE_SPECIAL;
1638	inst->_operation = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC;
1639	inst->_has_immediat = 0;
1640	inst->_immediat = 0; // unnecessary
1641	inst->_read_ra = 0;
1642	inst->_num_reg_ra = 0; //unnecessary
1643	inst->_read_rb = 0;
1644	inst->_num_reg_rb = 0; //unnecessary
1645	inst->_read_rc = 0;
1646	inst->_num_reg_rc = 0; //unnecessary
1647	inst->_write_rd = 0;
1648	inst->_num_reg_rd = 0; //unnecessary
1649	inst->_write_re = 0;
1650	inst->_num_reg_re = 0; //unnecessary
1651	inst->_exception_use = EXCEPTION_USE_NONE;
1652	inst->_exception = EXCEPTION_DECOD_NONE;
1653	// inst->_branch_condition = ;
1654	// inst->_branch_stack_write = ;
1655	// inst->_branch_direction = ;
1656	// inst->_address_next = ; // already define : PC+4 // don't change
1657	inst->_no_execute = 0;
1658	inst->_event_type = EVENT_TYPE_MSYNC;
1659	}
1660	}
1661
1662	void instruction_l_mtspr (decod_instruction_t * inst, decod_param_t * param)
1663	{
1664	log_printf(TRACE,Decod,"instruction_l_mtspr"," * instruction : l.mtspr");
1665
1666	#ifdef STATISTICS
1667	inst->_opcod = INSTRUCTION_L_MTSPR;
1668	#endif
1669	inst->_type = instruction_information(INSTRUCTION_L_MTSPR)._type ; //TYPE_SPECIAL;
1670	inst->_operation = instruction_information(INSTRUCTION_L_MTSPR)._operation; //OPERATION_SPECIAL_L_MTSPR;
1671	inst->_has_immediat = 1;
1672	inst->_immediat = EXTENDZ(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
1673	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
1674	inst->_read_ra = 1;
1675	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1676	inst->_read_rb = 1;
1677	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1678	inst->_read_rc = 0;
1679	inst->_num_reg_rc = 0; //unnecessary
1680	inst->_write_rd = 0;
1681	inst->_num_reg_rd = 0; //unnecessary
1682	inst->_write_re = 0;
1683	inst->_num_reg_re = 0; //unnecessary
1684	inst->_exception_use = EXCEPTION_USE_NONE;
1685	inst->_exception = EXCEPTION_DECOD_NONE;
1686	// inst->_branch_condition = ;
1687	// inst->_branch_stack_write = ;
1688	// inst->_branch_direction = ;
1689	// inst->_address_next = ; // already define : PC+4 // don't change
1690	inst->_no_execute = 0;
1691	inst->_event_type = EVENT_TYPE_SPR_ACCESS;
1692	}
1693
1694	void instruction_l_mul (decod_instruction_t * inst, decod_param_t * param)
1695	{
1696	log_printf(TRACE,Decod,"instruction_l_mul"," * instruction : l.mul");
1697
1698	#ifdef STATISTICS
1699	inst->_opcod = INSTRUCTION_L_MUL;
1700	#endif
1701	inst->_type = instruction_information(INSTRUCTION_L_MUL)._type ; //TYPE_MUL;
1702	inst->_operation = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL;
1703	inst->_has_immediat = 0;
1704	inst->_immediat = 0; // unnecessary
1705	inst->_read_ra = 1;
1706	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1707	inst->_read_rb = 1;
1708	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1709	inst->_read_rc = 0;
1710	inst->_num_reg_rc = 0; //unnecessary
1711	inst->_write_rd = 1;
1712	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1713	inst->_write_re = 1;
1714	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
1715	inst->_exception_use = EXCEPTION_USE_RANGE;
1716	inst->_exception = EXCEPTION_DECOD_NONE;
1717	// inst->_branch_condition = ;
1718	// inst->_branch_stack_write = ;
1719	// inst->_branch_direction = ;
1720	// inst->_address_next = ; // already define : PC+4
1721	inst->_no_execute = 0;
1722	inst->_event_type = EVENT_TYPE_NONE;
1723	}
1724
1725	void instruction_l_muli (decod_instruction_t * inst, decod_param_t * param)
1726	{
1727	log_printf(TRACE,Decod,"instruction_l_muli"," * instruction : l.muli");
1728
1729	#ifdef STATISTICS
1730	inst->_opcod = INSTRUCTION_L_MULI;
1731	#endif
1732	inst->_type = instruction_information(INSTRUCTION_L_MULI)._type ; //TYPE_MUL;
1733	inst->_operation = instruction_information(INSTRUCTION_L_MULI)._operation; //OPERATION_MUL_L_MUL;
1734	inst->_has_immediat = 1;
1735	inst->_immediat = EXTENDS(inst->_instruction,16);
1736	inst->_read_ra = 1;
1737	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1738	inst->_read_rb = 0;
1739	inst->_num_reg_rb = 0; //unnecessary
1740	inst->_read_rc = 0;
1741	inst->_num_reg_rc = 0; //unnecessary
1742	inst->_write_rd = 1;
1743	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1744	inst->_write_re = 1;
1745	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
1746	inst->_exception_use = EXCEPTION_USE_RANGE;
1747	inst->_exception = EXCEPTION_DECOD_NONE;
1748	// inst->_branch_condition = ;
1749	// inst->_branch_stack_write = ;
1750	// inst->_branch_direction = ;
1751	// inst->_address_next = ; // already define : PC+4
1752	inst->_no_execute = 0;
1753	inst->_event_type = EVENT_TYPE_NONE;
1754	}
1755
1756	void instruction_l_mulu (decod_instruction_t * inst, decod_param_t * param)
1757	{
1758	log_printf(TRACE,Decod,"instruction_l_mulu"," * instruction : l.mulu");
1759
1760	#ifdef STATISTICS
1761	inst->_opcod = INSTRUCTION_L_MULU;
1762	#endif
1763	inst->_type = instruction_information(INSTRUCTION_L_MULU)._type ; //TYPE_MUL;
1764	inst->_operation = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU;
1765	inst->_has_immediat = 0;
1766	inst->_immediat = 0; // unnecessary
1767	inst->_read_ra = 1;
1768	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1769	inst->_read_rb = 1;
1770	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1771	inst->_read_rc = 0;
1772	inst->_num_reg_rc = 0; //unnecessary
1773	inst->_write_rd = 1;
1774	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1775	inst->_write_re = 1;
1776	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
1777	inst->_exception_use = EXCEPTION_USE_RANGE;
1778	inst->_exception = EXCEPTION_DECOD_NONE;
1779	// inst->_branch_condition = ;
1780	// inst->_branch_stack_write = ;
1781	// inst->_branch_direction = ;
1782	// inst->_address_next = ; // already define : PC+4
1783	inst->_no_execute = 0;
1784	inst->_event_type = EVENT_TYPE_NONE;
1785	}
1786
1787	void instruction_l_nop (decod_instruction_t * inst, decod_param_t * param)
1788	{
1789	log_printf(TRACE,Decod,"instruction_l_nop"," * instruction : l.nop");
1790
1791	#ifdef STATISTICS
1792	inst->_opcod = INSTRUCTION_L_NOP;
1793	#endif
1794	inst->_type = instruction_information(INSTRUCTION_L_NOP)._type ; //TYPE_SPECIAL;
1795	inst->_operation = instruction_information(INSTRUCTION_L_NOP)._operation; //OPERATION_SPECIAL_L_NOP;
1796	// inst->_has_immediat = 1;
1797	// inst->_immediat = EXTENDZ(inst->_instruction,16);
1798	inst->_has_immediat = 0;
1799	inst->_immediat = 0; // unnecessary
1800	inst->_read_ra = 0;
1801	inst->_num_reg_ra = 0; //unnecessary
1802	inst->_read_rb = 0;
1803	inst->_num_reg_rb = 0; //unnecessary
1804	inst->_read_rc = 0;
1805	inst->_num_reg_rc = 0; //unnecessary
1806	inst->_write_rd = 0;
1807	inst->_num_reg_rd = 0; //unnecessary
1808	inst->_write_re = 0;
1809	inst->_num_reg_re = 0; //unnecessary
1810	inst->_exception_use = EXCEPTION_USE_NONE;
1811	inst->_exception = EXCEPTION_DECOD_NONE;
1812	// inst->_branch_condition = ;
1813	// inst->_branch_stack_write = ;
1814	// inst->_branch_direction = ;
1815	// inst->_address_next = ; // already define : PC+4
1816	inst->_no_execute = 1;
1817	inst->_event_type = EVENT_TYPE_NONE;
1818	}
1819
1820	void instruction_l_or (decod_instruction_t * inst, decod_param_t * param)
1821	{
1822	log_printf(TRACE,Decod,"instruction_l_or"," * instruction : l.or");
1823
1824	#ifdef STATISTICS
1825	inst->_opcod = INSTRUCTION_L_OR;
1826	#endif
1827	inst->_type = instruction_information(INSTRUCTION_L_OR)._type ; //TYPE_ALU;
1828	inst->_operation = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR;
1829	inst->_has_immediat = 0;
1830	inst->_immediat = 0; // unnecessary
1831	inst->_read_ra = 1;
1832	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1833	inst->_read_rb = 1;
1834	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1835	inst->_read_rc = 0;
1836	inst->_num_reg_rc = 0; //unnecessary
1837	inst->_write_rd = 1;
1838	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1839	inst->_write_re = 0;
1840	inst->_num_reg_re = 0; //unnecessary
1841	inst->_exception_use = EXCEPTION_USE_NONE;
1842	inst->_exception = EXCEPTION_DECOD_NONE;
1843	// inst->_branch_condition = ;
1844	// inst->_branch_stack_write = ;
1845	// inst->_branch_direction = ;
1846	// inst->_address_next = ; // already define : PC+4
1847	inst->_no_execute = 0;
1848	inst->_event_type = EVENT_TYPE_NONE;
1849	}
1850
1851	void instruction_l_ori (decod_instruction_t * inst, decod_param_t * param)
1852	{
1853	log_printf(TRACE,Decod,"instruction_l_ori"," * instruction : l.ori");
1854
1855	#ifdef STATISTICS
1856	inst->_opcod = INSTRUCTION_L_ORI;
1857	#endif
1858	inst->_type = instruction_information(INSTRUCTION_L_ORI)._type ; //TYPE_ALU;
1859	inst->_operation = instruction_information(INSTRUCTION_L_ORI)._operation; //OPERATION_ALU_L_OR;
1860	inst->_has_immediat = 1;
1861	inst->_immediat = EXTENDZ(inst->_instruction,16);
1862	inst->_read_ra = 1;
1863	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1864	inst->_read_rb = 0;
1865	inst->_num_reg_rb = 0; //unnecessary
1866	inst->_read_rc = 0;
1867	inst->_num_reg_rc = 0; //unnecessary
1868	inst->_write_rd = 1;
1869	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1870	inst->_write_re = 0;
1871	inst->_num_reg_re = 0; //unnecessary
1872	inst->_exception_use = EXCEPTION_USE_NONE;
1873	inst->_exception = EXCEPTION_DECOD_NONE;
1874	// inst->_branch_condition = ;
1875	// inst->_branch_stack_write = ;
1876	// inst->_branch_direction = ;
1877	// inst->_address_next = ; // already define : PC+4
1878	inst->_no_execute = 0;
1879	inst->_event_type = EVENT_TYPE_NONE;
1880	}
1881
1882	void instruction_l_psync (decod_instruction_t * inst, decod_param_t * param)
1883	{
1884	log_printf(TRACE,Decod,"instruction_l_psync"," * instruction : l.psync");
1885
1886	if (range<uint32_t>(inst->_instruction,22, 0) != 0)
1887	{
1888	instruction_illegal (inst, param);
1889	}
1890	else
1891	{
1892	#ifdef STATISTICS
1893	inst->_opcod = INSTRUCTION_L_PSYNC;
1894	#endif
1895	inst->_type = instruction_information(INSTRUCTION_L_PSYNC)._type ; //TYPE_SPECIAL;
1896	inst->_operation = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC;
1897	inst->_has_immediat = 0;
1898	inst->_immediat = 0; // unnecessary
1899	inst->_read_ra = 0;
1900	inst->_num_reg_ra = 0; //unnecessary
1901	inst->_read_rb = 0;
1902	inst->_num_reg_rb = 0; //unnecessary
1903	inst->_read_rc = 0;
1904	inst->_num_reg_rc = 0; //unnecessary
1905	inst->_write_rd = 0;
1906	inst->_num_reg_rd = 0; //unnecessary
1907	inst->_write_re = 0;
1908	inst->_num_reg_re = 0; //unnecessary
1909	inst->_exception_use = EXCEPTION_USE_NONE;
1910	inst->_exception = EXCEPTION_DECOD_NONE;
1911	// inst->_branch_condition = ;
1912	// inst->_branch_stack_write = ;
1913	// inst->_branch_direction = ;
1914	// inst->_address_next = ; // already define : PC+4 // don't change
1915	inst->_no_execute = 0;
1916	inst->_event_type = EVENT_TYPE_PSYNC;
1917	}
1918	}
1919
1920	void instruction_l_rfe (decod_instruction_t * inst, decod_param_t * param)
1921	{
1922	log_printf(TRACE,Decod,"instruction_l_rfe"," * instruction : l.rfe");
1923
1924	#ifdef STATISTICS
1925	inst->_opcod = INSTRUCTION_L_RFE;
1926	#endif
1927	inst->_type = instruction_information(INSTRUCTION_L_RFE)._type ; //TYPE_SPECIAL;
1928	inst->_operation = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE;
1929	inst->_has_immediat = 0;
1930	inst->_immediat = 0; // unnecessary
1931	inst->_read_ra = 0;
1932	inst->_num_reg_ra = 0; //unnecessary
1933	inst->_read_rb = 0;
1934	inst->_num_reg_rb = 0; //unnecessary
1935	inst->_read_rc = 0;
1936	inst->_num_reg_rc = 0; //unnecessary
1937	inst->_write_rd = 0;
1938	inst->_num_reg_rd = 0; //unnecessary
1939	inst->_write_re = 0;
1940	inst->_num_reg_re = 0; //unnecessary
1941	inst->_exception_use = EXCEPTION_USE_NONE;
1942	inst->_exception = EXCEPTION_DECOD_NONE;
1943	// inst->_branch_condition = ;
1944	// inst->_branch_stack_write = ;
1945	// inst->_branch_direction = ;
1946	// inst->_address_next = ; // already define : PC+4 // don't change
1947	inst->_no_execute = 1;
1948	inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage
1949	}
1950
1951	void instruction_l_ror (decod_instruction_t * inst, decod_param_t * param)
1952	{
1953	log_printf(TRACE,Decod,"instruction_l_ror"," * instruction : l.ror");
1954
1955	#ifdef STATISTICS
1956	inst->_opcod = INSTRUCTION_L_ROR;
1957	#endif
1958	inst->_type = instruction_information(INSTRUCTION_L_ROR)._type ; //TYPE_SHIFT;
1959	inst->_operation = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR;
1960	inst->_has_immediat = 0;
1961	inst->_immediat = 0; // unnecessary
1962	inst->_read_ra = 1;
1963	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1964	inst->_read_rb = 1;
1965	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
1966	inst->_read_rc = 0;
1967	inst->_num_reg_rc = 0; //unnecessary
1968	inst->_write_rd = 1;
1969	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
1970	inst->_write_re = 0;
1971	inst->_num_reg_re = 0; //unnecessary
1972	inst->_exception_use = EXCEPTION_USE_NONE;
1973	inst->_exception = EXCEPTION_DECOD_NONE;
1974	// inst->_branch_condition = ;
1975	// inst->_branch_stack_write = ;
1976	// inst->_branch_direction = ;
1977	// inst->_address_next = ; // already define : PC+4
1978	inst->_no_execute = 0;
1979	inst->_event_type = EVENT_TYPE_NONE;
1980	}
1981
1982	void instruction_l_rori (decod_instruction_t * inst, decod_param_t * param)
1983	{
1984	log_printf(TRACE,Decod,"instruction_l_rori"," * instruction : l.rori");
1985
1986	#ifdef STATISTICS
1987	inst->_opcod = INSTRUCTION_L_RORI;
1988	#endif
1989	inst->_type = instruction_information(INSTRUCTION_L_RORI)._type ; //TYPE_SHIFT;
1990	inst->_operation = instruction_information(INSTRUCTION_L_RORI)._operation; //OPERATION_SHIFT_L_ROR;
1991	inst->_has_immediat = 1;
1992	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
1993	inst->_read_ra = 1;
1994	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
1995	inst->_read_rb = 0;
1996	inst->_num_reg_rb = 0; //unnecessary
1997	inst->_read_rc = 0;
1998	inst->_num_reg_rc = 0; //unnecessary
1999	inst->_write_rd = 1;
2000	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2001	inst->_write_re = 0;
2002	inst->_num_reg_re = 0; //unnecessary
2003	inst->_exception_use = EXCEPTION_USE_NONE;
2004	inst->_exception = EXCEPTION_DECOD_NONE;
2005	// inst->_branch_condition = ;
2006	// inst->_branch_stack_write = ;
2007	// inst->_branch_direction = ;
2008	// inst->_address_next = ; // already define : PC+4
2009	inst->_no_execute = 0;
2010	inst->_event_type = EVENT_TYPE_NONE;
2011	}
2012
2013	void instruction_l_sb (decod_instruction_t * inst, decod_param_t * param)
2014	{
2015	log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb");
2016
2017	#ifdef STATISTICS
2018	inst->_opcod = INSTRUCTION_L_SB;
2019	#endif
2020	inst->_type = instruction_information(INSTRUCTION_L_SB)._type ; //TYPE_MEMORY;
2021	inst->_operation = instruction_information(INSTRUCTION_L_SB)._operation; //OPERATION_MEMORY_STORE_8;
2022	inst->_has_immediat = 1;
2023	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
2024	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
2025	inst->_read_ra = 1;
2026	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2027	inst->_read_rb = 1;
2028	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2029	inst->_read_rc = 0;
2030	inst->_num_reg_rc = 0; //unnecessary
2031	inst->_write_rd = 0;
2032	inst->_num_reg_rd = 0; //unnecessary
2033	inst->_write_re = 0;
2034	inst->_num_reg_re = 0; //unnecessary
2035	inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT;
2036	inst->_exception = EXCEPTION_DECOD_NONE;
2037	// inst->_branch_condition = ;
2038	// inst->_branch_stack_write = ;
2039	// inst->_branch_direction = ;
2040	// inst->_address_next = ; // already define : PC+4
2041	inst->_no_execute = 0;
2042	inst->_event_type = EVENT_TYPE_NONE;
2043	}
2044
2045	void instruction_l_sd (decod_instruction_t * inst, decod_param_t * param)
2046	{
2047	log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb");
2048
2049	#ifdef STATISTICS
2050	inst->_opcod = INSTRUCTION_L_SD;
2051	#endif
2052	inst->_type = instruction_information(INSTRUCTION_L_SD)._type ; //TYPE_MEMORY;
2053	inst->_operation = instruction_information(INSTRUCTION_L_SD)._operation; //OPERATION_MEMORY_STORE_64;
2054	inst->_has_immediat = 1;
2055	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
2056	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
2057	inst->_read_ra = 1;
2058	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2059	inst->_read_rb = 1;
2060	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2061	inst->_read_rc = 0;
2062	inst->_num_reg_rc = 0; //unnecessary
2063	inst->_write_rd = 0;
2064	inst->_num_reg_rd = 0; //unnecessary
2065	inst->_write_re = 0;
2066	inst->_num_reg_re = 0; //unnecessary
2067	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
2068	inst->_exception = EXCEPTION_DECOD_NONE;
2069	// inst->_branch_condition = ;
2070	// inst->_branch_stack_write = ;
2071	// inst->_branch_direction = ;
2072	// inst->_address_next = ; // already define : PC+4
2073	inst->_no_execute = 0;
2074	inst->_event_type = EVENT_TYPE_NONE;
2075	}
2076
2077	void instruction_l_sfeq (decod_instruction_t * inst, decod_param_t * param)
2078	{
2079	log_printf(TRACE,Decod,"instruction_l_sfeq"," * instruction : l.sfeq");
2080
2081	#ifdef STATISTICS
2082	inst->_opcod = INSTRUCTION_L_SFEQ;
2083	#endif
2084	inst->_type = instruction_information(INSTRUCTION_L_SFEQ)._type ; //TYPE_TEST;
2085	inst->_operation = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ;
2086	inst->_has_immediat = 0;
2087	inst->_immediat = 0; // unnecessary
2088	inst->_read_ra = 1;
2089	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2090	inst->_read_rb = 1;
2091	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2092	inst->_read_rc = 0;
2093	inst->_num_reg_rc = 0; //unnecessary
2094	inst->_write_rd = 0;
2095	inst->_num_reg_rd = 0; //unnecessary
2096	inst->_write_re = 1;
2097	inst->_num_reg_re = SPR_LOGIC_SR_F;
2098	inst->_exception_use = EXCEPTION_USE_NONE;
2099	inst->_exception = EXCEPTION_DECOD_NONE;
2100	// inst->_branch_condition = ;
2101	// inst->_branch_stack_write = ;
2102	// inst->_branch_direction = ;
2103	// inst->_address_next = ; // already define : PC+4
2104	inst->_no_execute = 0;
2105	inst->_event_type = EVENT_TYPE_NONE;
2106	}
2107
2108	void instruction_l_sfeqi (decod_instruction_t * inst, decod_param_t * param)
2109	{
2110	log_printf(TRACE,Decod,"instruction_l_sfeqi"," * instruction : l.sfeqi");
2111
2112	#ifdef STATISTICS
2113	inst->_opcod = INSTRUCTION_L_SFEQI;
2114	#endif
2115	inst->_type = instruction_information(INSTRUCTION_L_SFEQI)._type ; //TYPE_TEST;
2116	inst->_operation = instruction_information(INSTRUCTION_L_SFEQI)._operation; //OPERATION_TEST_L_SFEQ;
2117	inst->_has_immediat = 1;
2118	inst->_immediat = EXTENDS(inst->_instruction,16);
2119	inst->_read_ra = 1;
2120	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2121	inst->_read_rb = 0;
2122	inst->_num_reg_rb = 0; //unnecessary
2123	inst->_read_rc = 0;
2124	inst->_num_reg_rc = 0; //unnecessary
2125	inst->_write_rd = 0;
2126	inst->_num_reg_rd = 0; //unnecessary
2127	inst->_write_re = 1;
2128	inst->_num_reg_re = SPR_LOGIC_SR_F;
2129	inst->_exception_use = EXCEPTION_USE_NONE;
2130	inst->_exception = EXCEPTION_DECOD_NONE;
2131	// inst->_branch_condition = ;
2132	// inst->_branch_stack_write = ;
2133	// inst->_branch_direction = ;
2134	// inst->_address_next = ; // already define : PC+4
2135	inst->_no_execute = 0;
2136	inst->_event_type = EVENT_TYPE_NONE;
2137	}
2138
2139	void instruction_l_sfges (decod_instruction_t * inst, decod_param_t * param)
2140	{
2141	log_printf(TRACE,Decod,"instruction_l_sfges"," * instruction : l.sfges");
2142
2143	#ifdef STATISTICS
2144	inst->_opcod = INSTRUCTION_L_SFGES;
2145	#endif
2146	inst->_type = instruction_information(INSTRUCTION_L_SFGES)._type ; //TYPE_TEST;
2147	inst->_operation = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES;
2148	inst->_has_immediat = 0;
2149	inst->_immediat = 0; // unnecessary
2150	inst->_read_ra = 1;
2151	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2152	inst->_read_rb = 1;
2153	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2154	inst->_read_rc = 0;
2155	inst->_num_reg_rc = 0; //unnecessary
2156	inst->_write_rd = 0;
2157	inst->_num_reg_rd = 0; //unnecessary
2158	inst->_write_re = 1;
2159	inst->_num_reg_re = SPR_LOGIC_SR_F;
2160	inst->_exception_use = EXCEPTION_USE_NONE;
2161	inst->_exception = EXCEPTION_DECOD_NONE;
2162	// inst->_branch_condition = ;
2163	// inst->_branch_stack_write = ;
2164	// inst->_branch_direction = ;
2165	// inst->_address_next = ; // already define : PC+4
2166	inst->_no_execute = 0;
2167	inst->_event_type = EVENT_TYPE_NONE;
2168	}
2169
2170	void instruction_l_sfgesi (decod_instruction_t * inst, decod_param_t * param)
2171	{
2172	log_printf(TRACE,Decod,"instruction_l_sfgesi"," * instruction : l.sfgesi");
2173
2174	#ifdef STATISTICS
2175	inst->_opcod = INSTRUCTION_L_SFGESI;
2176	#endif
2177	inst->_type = instruction_information(INSTRUCTION_L_SFGESI)._type ; //TYPE_TEST;
2178	inst->_operation = instruction_information(INSTRUCTION_L_SFGESI)._operation; //OPERATION_TEST_L_SFGES;
2179	inst->_has_immediat = 1;
2180	inst->_immediat = EXTENDS(inst->_instruction,16);
2181	inst->_read_ra = 1;
2182	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2183	inst->_read_rb = 0;
2184	inst->_num_reg_rb = 0; //unnecessary
2185	inst->_read_rc = 0;
2186	inst->_num_reg_rc = 0; //unnecessary
2187	inst->_write_rd = 0;
2188	inst->_num_reg_rd = 0; //unnecessary
2189	inst->_write_re = 1;
2190	inst->_num_reg_re = SPR_LOGIC_SR_F;
2191	inst->_exception_use = EXCEPTION_USE_NONE;
2192	inst->_exception = EXCEPTION_DECOD_NONE;
2193	// inst->_branch_condition = ;
2194	// inst->_branch_stack_write = ;
2195	// inst->_branch_direction = ;
2196	// inst->_address_next = ; // already define : PC+4
2197	inst->_no_execute = 0;
2198	inst->_event_type = EVENT_TYPE_NONE;
2199	}
2200
2201	void instruction_l_sfgeu (decod_instruction_t * inst, decod_param_t * param)
2202	{
2203	log_printf(TRACE,Decod,"instruction_l_sfgeu"," * instruction : l.sfgeu");
2204
2205	#ifdef STATISTICS
2206	inst->_opcod = INSTRUCTION_L_SFGEU;
2207	#endif
2208	inst->_type = instruction_information(INSTRUCTION_L_SFGEU)._type ; //TYPE_TEST;
2209	inst->_operation = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU;
2210	inst->_has_immediat = 0;
2211	inst->_immediat = 0; // unnecessary
2212	inst->_read_ra = 1;
2213	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2214	inst->_read_rb = 1;
2215	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2216	inst->_read_rc = 0;
2217	inst->_num_reg_rc = 0; //unnecessary
2218	inst->_write_rd = 0;
2219	inst->_num_reg_rd = 0; //unnecessary
2220	inst->_write_re = 1;
2221	inst->_num_reg_re = SPR_LOGIC_SR_F;
2222	inst->_exception_use = EXCEPTION_USE_NONE;
2223	inst->_exception = EXCEPTION_DECOD_NONE;
2224	// inst->_branch_condition = ;
2225	// inst->_branch_stack_write = ;
2226	// inst->_branch_direction = ;
2227	// inst->_address_next = ; // already define : PC+4
2228	inst->_no_execute = 0;
2229	inst->_event_type = EVENT_TYPE_NONE;
2230	}
2231
2232	void instruction_l_sfgeui (decod_instruction_t * inst, decod_param_t * param)
2233	{
2234	log_printf(TRACE,Decod,"instruction_l_sfgeui"," * instruction : l.sfgeui");
2235
2236	#ifdef STATISTICS
2237	inst->_opcod = INSTRUCTION_L_SFGEUI;
2238	#endif
2239	inst->_type = instruction_information(INSTRUCTION_L_SFGEUI)._type ; //TYPE_TEST;
2240	inst->_operation = instruction_information(INSTRUCTION_L_SFGEUI)._operation; //OPERATION_TEST_L_SFGEU;
2241	inst->_has_immediat = 1;
2242	inst->_immediat = EXTENDS(inst->_instruction,16);
2243	inst->_read_ra = 1;
2244	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2245	inst->_read_rb = 0;
2246	inst->_num_reg_rb = 0; //unnecessary
2247	inst->_read_rc = 0;
2248	inst->_num_reg_rc = 0; //unnecessary
2249	inst->_write_rd = 0;
2250	inst->_num_reg_rd = 0; //unnecessary
2251	inst->_write_re = 1;
2252	inst->_num_reg_re = SPR_LOGIC_SR_F;
2253	inst->_exception_use = EXCEPTION_USE_NONE;
2254	inst->_exception = EXCEPTION_DECOD_NONE;
2255	// inst->_branch_condition = ;
2256	// inst->_branch_stack_write = ;
2257	// inst->_branch_direction = ;
2258	// inst->_address_next = ; // already define : PC+4
2259	inst->_no_execute = 0;
2260	inst->_event_type = EVENT_TYPE_NONE;
2261	}
2262
2263	void instruction_l_sfgts (decod_instruction_t * inst, decod_param_t * param)
2264	{
2265	log_printf(TRACE,Decod,"instruction_l_sfgts"," * instruction : l.sfgts");
2266
2267	#ifdef STATISTICS
2268	inst->_opcod = INSTRUCTION_L_SFGTS;
2269	#endif
2270	inst->_type = instruction_information(INSTRUCTION_L_SFGTS)._type ; //TYPE_TEST;
2271	inst->_operation = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS;
2272	inst->_has_immediat = 0;
2273	inst->_immediat = 0; // unnecessary
2274	inst->_read_ra = 1;
2275	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2276	inst->_read_rb = 1;
2277	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2278	inst->_read_rc = 0;
2279	inst->_num_reg_rc = 0; //unnecessary
2280	inst->_write_rd = 0;
2281	inst->_num_reg_rd = 0; //unnecessary
2282	inst->_write_re = 1;
2283	inst->_num_reg_re = SPR_LOGIC_SR_F;
2284	inst->_exception_use = EXCEPTION_USE_NONE;
2285	inst->_exception = EXCEPTION_DECOD_NONE;
2286	// inst->_branch_condition = ;
2287	// inst->_branch_stack_write = ;
2288	// inst->_branch_direction = ;
2289	// inst->_address_next = ; // already define : PC+4
2290	inst->_no_execute = 0;
2291	inst->_event_type = EVENT_TYPE_NONE;
2292	}
2293
2294	void instruction_l_sfgtsi (decod_instruction_t * inst, decod_param_t * param)
2295	{
2296	log_printf(TRACE,Decod,"instruction_l_sfgtsi"," * instruction : l.sfgtsi");
2297
2298	#ifdef STATISTICS
2299	inst->_opcod = INSTRUCTION_L_SFGTSI;
2300	#endif
2301	inst->_type = instruction_information(INSTRUCTION_L_SFGTSI)._type ; //TYPE_TEST;
2302	inst->_operation = instruction_information(INSTRUCTION_L_SFGTSI)._operation; //OPERATION_TEST_L_SFGTS;
2303	inst->_has_immediat = 1;
2304	inst->_immediat = EXTENDS(inst->_instruction,16);
2305	inst->_read_ra = 1;
2306	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2307	inst->_read_rb = 0;
2308	inst->_num_reg_rb = 0; //unnecessary
2309	inst->_read_rc = 0;
2310	inst->_num_reg_rc = 0; //unnecessary
2311	inst->_write_rd = 0;
2312	inst->_num_reg_rd = 0; //unnecessary
2313	inst->_write_re = 1;
2314	inst->_num_reg_re = SPR_LOGIC_SR_F;
2315	inst->_exception_use = EXCEPTION_USE_NONE;
2316	inst->_exception = EXCEPTION_DECOD_NONE;
2317	// inst->_branch_condition = ;
2318	// inst->_branch_stack_write = ;
2319	// inst->_branch_direction = ;
2320	// inst->_address_next = ; // already define : PC+4
2321	inst->_no_execute = 0;
2322	inst->_event_type = EVENT_TYPE_NONE;
2323	}
2324
2325	void instruction_l_sfgtu (decod_instruction_t * inst, decod_param_t * param)
2326	{
2327	log_printf(TRACE,Decod,"instruction_l_sfgtu"," * instruction : l.sfgtu");
2328
2329	#ifdef STATISTICS
2330	inst->_opcod = INSTRUCTION_L_SFGTU;
2331	#endif
2332	inst->_type = instruction_information(INSTRUCTION_L_SFGTU)._type ; //TYPE_TEST;
2333	inst->_operation = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU;
2334	inst->_has_immediat = 0;
2335	inst->_immediat = 0; // unnecessary
2336	inst->_read_ra = 1;
2337	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2338	inst->_read_rb = 1;
2339	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2340	inst->_read_rc = 0;
2341	inst->_num_reg_rc = 0; //unnecessary
2342	inst->_write_rd = 0;
2343	inst->_num_reg_rd = 0; //unnecessary
2344	inst->_write_re = 1;
2345	inst->_num_reg_re = SPR_LOGIC_SR_F;
2346	inst->_exception_use = EXCEPTION_USE_NONE;
2347	inst->_exception = EXCEPTION_DECOD_NONE;
2348	// inst->_branch_condition = ;
2349	// inst->_branch_stack_write = ;
2350	// inst->_branch_direction = ;
2351	// inst->_address_next = ; // already define : PC+4
2352	inst->_no_execute = 0;
2353	inst->_event_type = EVENT_TYPE_NONE;
2354	}
2355
2356	void instruction_l_sfgtui (decod_instruction_t * inst, decod_param_t * param)
2357	{
2358	log_printf(TRACE,Decod,"instruction_l_sfgtui"," * instruction : l.sfgtui");
2359
2360	#ifdef STATISTICS
2361	inst->_opcod = INSTRUCTION_L_SFGTUI;
2362	#endif
2363	inst->_type = instruction_information(INSTRUCTION_L_SFGTUI)._type ; //TYPE_TEST;
2364	inst->_operation = instruction_information(INSTRUCTION_L_SFGTUI)._operation; //OPERATION_TEST_L_SFGTU;
2365	inst->_has_immediat = 1;
2366	inst->_immediat = EXTENDS(inst->_instruction,16);
2367	inst->_read_ra = 1;
2368	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2369	inst->_read_rb = 0;
2370	inst->_num_reg_rb = 0; //unnecessary
2371	inst->_read_rc = 0;
2372	inst->_num_reg_rc = 0; //unnecessary
2373	inst->_write_rd = 0;
2374	inst->_num_reg_rd = 0; //unnecessary
2375	inst->_write_re = 1;
2376	inst->_num_reg_re = SPR_LOGIC_SR_F;
2377	inst->_exception_use = EXCEPTION_USE_NONE;
2378	inst->_exception = EXCEPTION_DECOD_NONE;
2379	// inst->_branch_condition = ;
2380	// inst->_branch_stack_write = ;
2381	// inst->_branch_direction = ;
2382	// inst->_address_next = ; // already define : PC+4
2383	inst->_no_execute = 0;
2384	inst->_event_type = EVENT_TYPE_NONE;
2385	}
2386
2387	void instruction_l_sfles (decod_instruction_t * inst, decod_param_t * param)
2388	{
2389	log_printf(TRACE,Decod,"instruction_l_sfles"," * instruction : l.sfles");
2390
2391	#ifdef STATISTICS
2392	inst->_opcod = INSTRUCTION_L_SFLES;
2393	#endif
2394	inst->_type = instruction_information(INSTRUCTION_L_SFLES)._type ; //TYPE_TEST;
2395	inst->_operation = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES;
2396	inst->_has_immediat = 0;
2397	inst->_immediat = 0; // unnecessary
2398	inst->_read_ra = 1;
2399	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2400	inst->_read_rb = 1;
2401	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2402	inst->_read_rc = 0;
2403	inst->_num_reg_rc = 0; //unnecessary
2404	inst->_write_rd = 0;
2405	inst->_num_reg_rd = 0; //unnecessary
2406	inst->_write_re = 1;
2407	inst->_num_reg_re = SPR_LOGIC_SR_F;
2408	inst->_exception_use = EXCEPTION_USE_NONE;
2409	inst->_exception = EXCEPTION_DECOD_NONE;
2410	// inst->_branch_condition = ;
2411	// inst->_branch_stack_write = ;
2412	// inst->_branch_direction = ;
2413	// inst->_address_next = ; // already define : PC+4
2414	inst->_no_execute = 0;
2415	inst->_event_type = EVENT_TYPE_NONE;
2416	}
2417
2418	void instruction_l_sflesi (decod_instruction_t * inst, decod_param_t * param)
2419	{
2420	log_printf(TRACE,Decod,"instruction_l_sflesi"," * instruction : l.sflesi");
2421
2422	#ifdef STATISTICS
2423	inst->_opcod = INSTRUCTION_L_SFLESI;
2424	#endif
2425	inst->_type = instruction_information(INSTRUCTION_L_SFLESI)._type ; //TYPE_TEST;
2426	inst->_operation = instruction_information(INSTRUCTION_L_SFLESI)._operation; //OPERATION_TEST_L_SFLES;
2427	inst->_has_immediat = 1;
2428	inst->_immediat = EXTENDS(inst->_instruction,16);
2429	inst->_read_ra = 1;
2430	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2431	inst->_read_rb = 0;
2432	inst->_num_reg_rb = 0; //unnecessary
2433	inst->_read_rc = 0;
2434	inst->_num_reg_rc = 0; //unnecessary
2435	inst->_write_rd = 0;
2436	inst->_num_reg_rd = 0; //unnecessary
2437	inst->_write_re = 1;
2438	inst->_num_reg_re = SPR_LOGIC_SR_F;
2439	inst->_exception_use = EXCEPTION_USE_NONE;
2440	inst->_exception = EXCEPTION_DECOD_NONE;
2441	// inst->_branch_condition = ;
2442	// inst->_branch_stack_write = ;
2443	// inst->_branch_direction = ;
2444	// inst->_address_next = ; // already define : PC+4
2445	inst->_no_execute = 0;
2446	inst->_event_type = EVENT_TYPE_NONE;
2447	}
2448
2449	void instruction_l_sfleu (decod_instruction_t * inst, decod_param_t * param)
2450	{
2451	log_printf(TRACE,Decod,"instruction_l_sfleu"," * instruction : l.sfleu");
2452
2453	#ifdef STATISTICS
2454	inst->_opcod = INSTRUCTION_L_SFLEU;
2455	#endif
2456	inst->_type = instruction_information(INSTRUCTION_L_SFLEU)._type ; //TYPE_TEST;
2457	inst->_operation = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU;
2458	inst->_has_immediat = 0;
2459	inst->_immediat = 0; // unnecessary
2460	inst->_read_ra = 1;
2461	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2462	inst->_read_rb = 1;
2463	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2464	inst->_read_rc = 0;
2465	inst->_num_reg_rc = 0; //unnecessary
2466	inst->_write_rd = 0;
2467	inst->_num_reg_rd = 0; //unnecessary
2468	inst->_write_re = 1;
2469	inst->_num_reg_re = SPR_LOGIC_SR_F;
2470	inst->_exception_use = EXCEPTION_USE_NONE;
2471	inst->_exception = EXCEPTION_DECOD_NONE;
2472	// inst->_branch_condition = ;
2473	// inst->_branch_stack_write = ;
2474	// inst->_branch_direction = ;
2475	// inst->_address_next = ; // already define : PC+4
2476	inst->_no_execute = 0;
2477	inst->_event_type = EVENT_TYPE_NONE;
2478	}
2479
2480	void instruction_l_sfleui (decod_instruction_t * inst, decod_param_t * param)
2481	{
2482	log_printf(TRACE,Decod,"instruction_l_sfleui"," * instruction : l.sfleui");
2483
2484	#ifdef STATISTICS
2485	inst->_opcod = INSTRUCTION_L_SFLEUI;
2486	#endif
2487	inst->_type = instruction_information(INSTRUCTION_L_SFLEUI)._type ; //TYPE_TEST;
2488	inst->_operation = instruction_information(INSTRUCTION_L_SFLEUI)._operation; //OPERATION_TEST_L_SFLEU;
2489	inst->_has_immediat = 1;
2490	inst->_immediat = EXTENDS(inst->_instruction,16);
2491	inst->_read_ra = 1;
2492	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2493	inst->_read_rb = 0;
2494	inst->_num_reg_rb = 0; //unnecessary
2495	inst->_read_rc = 0;
2496	inst->_num_reg_rc = 0; //unnecessary
2497	inst->_write_rd = 0;
2498	inst->_num_reg_rd = 0; //unnecessary
2499	inst->_write_re = 1;
2500	inst->_num_reg_re = SPR_LOGIC_SR_F;
2501	inst->_exception_use = EXCEPTION_USE_NONE;
2502	inst->_exception = EXCEPTION_DECOD_NONE;
2503	// inst->_branch_condition = ;
2504	// inst->_branch_stack_write = ;
2505	// inst->_branch_direction = ;
2506	// inst->_address_next = ; // already define : PC+4
2507	inst->_no_execute = 0;
2508	inst->_event_type = EVENT_TYPE_NONE;
2509	}
2510
2511	void instruction_l_sflts (decod_instruction_t * inst, decod_param_t * param)
2512	{
2513	log_printf(TRACE,Decod,"instruction_l_sflts"," * instruction : l.sflts");
2514
2515	#ifdef STATISTICS
2516	inst->_opcod = INSTRUCTION_L_SFLTS;
2517	#endif
2518	inst->_type = instruction_information(INSTRUCTION_L_SFLTS)._type ; //TYPE_TEST;
2519	inst->_operation = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS;
2520	inst->_has_immediat = 0;
2521	inst->_immediat = 0; // unnecessary
2522	inst->_read_ra = 1;
2523	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2524	inst->_read_rb = 1;
2525	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2526	inst->_read_rc = 0;
2527	inst->_num_reg_rc = 0; //unnecessary
2528	inst->_write_rd = 0;
2529	inst->_num_reg_rd = 0; //unnecessary
2530	inst->_write_re = 1;
2531	inst->_num_reg_re = SPR_LOGIC_SR_F;
2532	inst->_exception_use = EXCEPTION_USE_NONE;
2533	inst->_exception = EXCEPTION_DECOD_NONE;
2534	// inst->_branch_condition = ;
2535	// inst->_branch_stack_write = ;
2536	// inst->_branch_direction = ;
2537	// inst->_address_next = ; // already define : PC+4
2538	inst->_no_execute = 0;
2539	inst->_event_type = EVENT_TYPE_NONE;
2540	}
2541
2542	void instruction_l_sfltsi (decod_instruction_t * inst, decod_param_t * param)
2543	{
2544	log_printf(TRACE,Decod,"instruction_l_sfltsi"," * instruction : l.sfltsi");
2545
2546	#ifdef STATISTICS
2547	inst->_opcod = INSTRUCTION_L_SFLTSI;
2548	#endif
2549	inst->_type = instruction_information(INSTRUCTION_L_SFLTSI)._type ; //TYPE_TEST;
2550	inst->_operation = instruction_information(INSTRUCTION_L_SFLTSI)._operation; //OPERATION_TEST_L_SFLTS;
2551	inst->_has_immediat = 1;
2552	inst->_immediat = EXTENDS(inst->_instruction,16);
2553	inst->_read_ra = 1;
2554	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2555	inst->_read_rb = 0;
2556	inst->_num_reg_rb = 0; //unnecessary
2557	inst->_read_rc = 0;
2558	inst->_num_reg_rc = 0; //unnecessary
2559	inst->_write_rd = 0;
2560	inst->_num_reg_rd = 0; //unnecessary
2561	inst->_write_re = 1;
2562	inst->_num_reg_re = SPR_LOGIC_SR_F;
2563	inst->_exception_use = EXCEPTION_USE_NONE;
2564	inst->_exception = EXCEPTION_DECOD_NONE;
2565	// inst->_branch_condition = ;
2566	// inst->_branch_stack_write = ;
2567	// inst->_branch_direction = ;
2568	// inst->_address_next = ; // already define : PC+4
2569	inst->_no_execute = 0;
2570	inst->_event_type = EVENT_TYPE_NONE;
2571	}
2572
2573	void instruction_l_sfltu (decod_instruction_t * inst, decod_param_t * param)
2574	{
2575	log_printf(TRACE,Decod,"instruction_l_sfltu"," * instruction : l.sfltu");
2576
2577	#ifdef STATISTICS
2578	inst->_opcod = INSTRUCTION_L_SFLTU;
2579	#endif
2580	inst->_type = instruction_information(INSTRUCTION_L_SFLTU)._type ; //TYPE_TEST;
2581	inst->_operation = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU;
2582	inst->_has_immediat = 0;
2583	inst->_immediat = 0; // unnecessary
2584	inst->_read_ra = 1;
2585	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2586	inst->_read_rb = 1;
2587	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2588	inst->_read_rc = 0;
2589	inst->_num_reg_rc = 0; //unnecessary
2590	inst->_write_rd = 0;
2591	inst->_num_reg_rd = 0; //unnecessary
2592	inst->_write_re = 1;
2593	inst->_num_reg_re = SPR_LOGIC_SR_F;
2594	inst->_exception_use = EXCEPTION_USE_NONE;
2595	inst->_exception = EXCEPTION_DECOD_NONE;
2596	// inst->_branch_condition = ;
2597	// inst->_branch_stack_write = ;
2598	// inst->_branch_direction = ;
2599	// inst->_address_next = ; // already define : PC+4
2600	inst->_no_execute = 0;
2601	inst->_event_type = EVENT_TYPE_NONE;
2602	}
2603
2604	void instruction_l_sfltui (decod_instruction_t * inst, decod_param_t * param)
2605	{
2606	log_printf(TRACE,Decod,"instruction_l_sfltui"," * instruction : l.sfltui");
2607
2608	#ifdef STATISTICS
2609	inst->_opcod = INSTRUCTION_L_SFLTUI;
2610	#endif
2611	inst->_type = instruction_information(INSTRUCTION_L_SFLTUI)._type ; //TYPE_TEST;
2612	inst->_operation = instruction_information(INSTRUCTION_L_SFLTUI)._operation; //OPERATION_TEST_L_SFLTU;
2613	inst->_has_immediat = 1;
2614	inst->_immediat = EXTENDS(inst->_instruction,16);
2615	inst->_read_ra = 1;
2616	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2617	inst->_read_rb = 0;
2618	inst->_num_reg_rb = 0; //unnecessary
2619	inst->_read_rc = 0;
2620	inst->_num_reg_rc = 0; //unnecessary
2621	inst->_write_rd = 0;
2622	inst->_num_reg_rd = 0; //unnecessary
2623	inst->_write_re = 1;
2624	inst->_num_reg_re = SPR_LOGIC_SR_F;
2625	inst->_exception_use = EXCEPTION_USE_NONE;
2626	inst->_exception = EXCEPTION_DECOD_NONE;
2627	// inst->_branch_condition = ;
2628	// inst->_branch_stack_write = ;
2629	// inst->_branch_direction = ;
2630	// inst->_address_next = ; // already define : PC+4
2631	inst->_no_execute = 0;
2632	inst->_event_type = EVENT_TYPE_NONE;
2633	}
2634
2635	void instruction_l_sfne (decod_instruction_t * inst, decod_param_t * param)
2636	{
2637	log_printf(TRACE,Decod,"instruction_l_sfne"," * instruction : l.sfne");
2638
2639	#ifdef STATISTICS
2640	inst->_opcod = INSTRUCTION_L_SFNE;
2641	#endif
2642	inst->_type = instruction_information(INSTRUCTION_L_SFNE)._type ; //TYPE_TEST;
2643	inst->_operation = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE;
2644	inst->_has_immediat = 0;
2645	inst->_immediat = 0; // unnecessary
2646	inst->_read_ra = 1;
2647	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2648	inst->_read_rb = 1;
2649	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2650	inst->_read_rc = 0;
2651	inst->_num_reg_rc = 0; //unnecessary
2652	inst->_write_rd = 0;
2653	inst->_num_reg_rd = 0; //unnecessary
2654	inst->_write_re = 1;
2655	inst->_num_reg_re = SPR_LOGIC_SR_F;
2656	inst->_exception_use = EXCEPTION_USE_NONE;
2657	inst->_exception = EXCEPTION_DECOD_NONE;
2658	// inst->_branch_condition = ;
2659	// inst->_branch_stack_write = ;
2660	// inst->_branch_direction = ;
2661	// inst->_address_next = ; // already define : PC+4
2662	inst->_no_execute = 0;
2663	inst->_event_type = EVENT_TYPE_NONE;
2664	}
2665
2666	void instruction_l_sfnei (decod_instruction_t * inst, decod_param_t * param)
2667	{
2668	log_printf(TRACE,Decod,"instruction_l_sfnei"," * instruction : l.sfnei");
2669
2670	#ifdef STATISTICS
2671	inst->_opcod = INSTRUCTION_L_SFNEI;
2672	#endif
2673	inst->_type = instruction_information(INSTRUCTION_L_SFNEI)._type ; //TYPE_TEST;
2674	inst->_operation = instruction_information(INSTRUCTION_L_SFNEI)._operation; //OPERATION_TEST_L_SFNE;
2675	inst->_has_immediat = 1;
2676	inst->_immediat = EXTENDS(inst->_instruction,16);
2677	inst->_read_ra = 1;
2678	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2679	inst->_read_rb = 0;
2680	inst->_num_reg_rb = 0; //unnecessary
2681	inst->_read_rc = 0;
2682	inst->_num_reg_rc = 0; //unnecessary
2683	inst->_write_rd = 0;
2684	inst->_num_reg_rd = 0; //unnecessary
2685	inst->_write_re = 1;
2686	inst->_num_reg_re = SPR_LOGIC_SR_F;
2687	inst->_exception_use = EXCEPTION_USE_NONE;
2688	inst->_exception = EXCEPTION_DECOD_NONE;
2689	// inst->_branch_condition = ;
2690	// inst->_branch_stack_write = ;
2691	// inst->_branch_direction = ;
2692	// inst->_address_next = ; // already define : PC+4
2693	inst->_no_execute = 0;
2694	inst->_event_type = EVENT_TYPE_NONE;
2695	}
2696
2697	void instruction_l_sh (decod_instruction_t * inst, decod_param_t * param)
2698	{
2699	log_printf(TRACE,Decod,"instruction_l_sh"," * instruction : l.sh");
2700
2701	#ifdef STATISTICS
2702	inst->_opcod = INSTRUCTION_L_SH;
2703	#endif
2704	inst->_type = instruction_information(INSTRUCTION_L_SH)._type ; //TYPE_MEMORY;
2705	inst->_operation = instruction_information(INSTRUCTION_L_SH)._operation; //OPERATION_MEMORY_STORE_16;
2706	inst->_has_immediat = 1;
2707	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
2708	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
2709	inst->_read_ra = 1;
2710	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2711	inst->_read_rb = 1;
2712	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2713	inst->_read_rc = 0;
2714	inst->_num_reg_rc = 0; //unnecessary
2715	inst->_write_rd = 0;
2716	inst->_num_reg_rd = 0; //unnecessary
2717	inst->_write_re = 0;
2718	inst->_num_reg_re = 0; //unnecessary
2719	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
2720	inst->_exception = EXCEPTION_DECOD_NONE;
2721	// inst->_branch_condition = ;
2722	// inst->_branch_stack_write = ;
2723	// inst->_branch_direction = ;
2724	// inst->_address_next = ; // already define : PC+4
2725	inst->_no_execute = 0;
2726	inst->_event_type = EVENT_TYPE_NONE;
2727	}
2728
2729	void instruction_l_sll (decod_instruction_t * inst, decod_param_t * param)
2730	{
2731	log_printf(TRACE,Decod,"instruction_l_sll"," * instruction : l.sll");
2732
2733	#ifdef STATISTICS
2734	inst->_opcod = INSTRUCTION_L_SLL;
2735	#endif
2736	inst->_type = instruction_information(INSTRUCTION_L_SLL)._type ; //TYPE_SHIFT;
2737	inst->_operation = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL;
2738	inst->_has_immediat = 0;
2739	inst->_immediat = 0; // unnecessary
2740	inst->_read_ra = 1;
2741	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2742	inst->_read_rb = 1;
2743	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2744	inst->_read_rc = 0;
2745	inst->_num_reg_rc = 0; //unnecessary
2746	inst->_write_rd = 1;
2747	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2748	inst->_write_re = 0;
2749	inst->_num_reg_re = 0; //unnecessary
2750	inst->_exception_use = EXCEPTION_USE_NONE;
2751	inst->_exception = EXCEPTION_DECOD_NONE;
2752	// inst->_branch_condition = ;
2753	// inst->_branch_stack_write = ;
2754	// inst->_branch_direction = ;
2755	// inst->_address_next = ; // already define : PC+4
2756	inst->_no_execute = 0;
2757	inst->_event_type = EVENT_TYPE_NONE;
2758	}
2759
2760	void instruction_l_slli (decod_instruction_t * inst, decod_param_t * param)
2761	{
2762	log_printf(TRACE,Decod,"instruction_l_slli"," * instruction : l.slli");
2763
2764	#ifdef STATISTICS
2765	inst->_opcod = INSTRUCTION_L_SLLI;
2766	#endif
2767	inst->_type = instruction_information(INSTRUCTION_L_SLLI)._type ; //TYPE_SHIFT;
2768	inst->_operation = instruction_information(INSTRUCTION_L_SLLI)._operation; //OPERATION_SHIFT_L_SLL;
2769	inst->_has_immediat = 1;
2770	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
2771	inst->_read_ra = 1;
2772	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2773	inst->_read_rb = 0;
2774	inst->_num_reg_rb = 0; //unnecessary
2775	inst->_read_rc = 0;
2776	inst->_num_reg_rc = 0; //unnecessary
2777	inst->_write_rd = 1;
2778	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2779	inst->_write_re = 0;
2780	inst->_num_reg_re = 0; //unnecessary
2781	inst->_exception_use = EXCEPTION_USE_NONE;
2782	inst->_exception = EXCEPTION_DECOD_NONE;
2783	// inst->_branch_condition = ;
2784	// inst->_branch_stack_write = ;
2785	// inst->_branch_direction = ;
2786	// inst->_address_next = ; // already define : PC+4
2787	inst->_no_execute = 0;
2788	inst->_event_type = EVENT_TYPE_NONE;
2789	}
2790
2791	void instruction_l_sra (decod_instruction_t * inst, decod_param_t * param)
2792	{
2793	log_printf(TRACE,Decod,"instruction_l_sra"," * instruction : l.sra");
2794
2795	#ifdef STATISTICS
2796	inst->_opcod = INSTRUCTION_L_SRA;
2797	#endif
2798	inst->_type = instruction_information(INSTRUCTION_L_SRA)._type ; //TYPE_SHIFT;
2799	inst->_operation = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA;
2800	inst->_has_immediat = 0;
2801	inst->_immediat = 0; // unnecessary
2802	inst->_read_ra = 1;
2803	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2804	inst->_read_rb = 1;
2805	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2806	inst->_read_rc = 0;
2807	inst->_num_reg_rc = 0; //unnecessary
2808	inst->_write_rd = 1;
2809	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2810	inst->_write_re = 0;
2811	inst->_num_reg_re = 0; //unnecessary
2812	inst->_exception_use = EXCEPTION_USE_NONE;
2813	inst->_exception = EXCEPTION_DECOD_NONE;
2814	// inst->_branch_condition = ;
2815	// inst->_branch_stack_write = ;
2816	// inst->_branch_direction = ;
2817	// inst->_address_next = ; // already define : PC+4
2818	inst->_no_execute = 0;
2819	inst->_event_type = EVENT_TYPE_NONE;
2820	}
2821
2822	void instruction_l_srai (decod_instruction_t * inst, decod_param_t * param)
2823	{
2824	log_printf(TRACE,Decod,"instruction_l_srai"," * instruction : l.srai");
2825
2826	#ifdef STATISTICS
2827	inst->_opcod = INSTRUCTION_L_SRAI;
2828	#endif
2829	inst->_type = instruction_information(INSTRUCTION_L_SRAI)._type ; //TYPE_SHIFT;
2830	inst->_operation = instruction_information(INSTRUCTION_L_SRAI)._operation; //OPERATION_SHIFT_L_SRA;
2831	inst->_has_immediat = 1;
2832	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
2833	inst->_read_ra = 1;
2834	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2835	inst->_read_rb = 0;
2836	inst->_num_reg_rb = 0; //unnecessary
2837	inst->_read_rc = 0;
2838	inst->_num_reg_rc = 0; //unnecessary
2839	inst->_write_rd = 1;
2840	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2841	inst->_write_re = 0;
2842	inst->_num_reg_re = 0; //unnecessary
2843	inst->_exception_use = EXCEPTION_USE_NONE;
2844	inst->_exception = EXCEPTION_DECOD_NONE;
2845	// inst->_branch_condition = ;
2846	// inst->_branch_stack_write = ;
2847	// inst->_branch_direction = ;
2848	// inst->_address_next = ; // already define : PC+4
2849	inst->_no_execute = 0;
2850	inst->_event_type = EVENT_TYPE_NONE;
2851	}
2852
2853	void instruction_l_srl (decod_instruction_t * inst, decod_param_t * param)
2854	{
2855	log_printf(TRACE,Decod,"instruction_l_srl"," * instruction : l.srl");
2856
2857	#ifdef STATISTICS
2858	inst->_opcod = INSTRUCTION_L_SRL;
2859	#endif
2860	inst->_type = instruction_information(INSTRUCTION_L_SRL)._type ; //TYPE_SHIFT;
2861	inst->_operation = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL;
2862	inst->_has_immediat = 0;
2863	inst->_immediat = 0; // unnecessary
2864	inst->_read_ra = 1;
2865	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2866	inst->_read_rb = 1;
2867	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2868	inst->_read_rc = 0;
2869	inst->_num_reg_rc = 0; //unnecessary
2870	inst->_write_rd = 1;
2871	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2872	inst->_write_re = 0;
2873	inst->_num_reg_re = 0; //unnecessary
2874	inst->_exception_use = EXCEPTION_USE_NONE;
2875	inst->_exception = EXCEPTION_DECOD_NONE;
2876	// inst->_branch_condition = ;
2877	// inst->_branch_stack_write = ;
2878	// inst->_branch_direction = ;
2879	// inst->_address_next = ; // already define : PC+4
2880	inst->_no_execute = 0;
2881	inst->_event_type = EVENT_TYPE_NONE;
2882	}
2883
2884	void instruction_l_srli (decod_instruction_t * inst, decod_param_t * param)
2885	{
2886	log_printf(TRACE,Decod,"instruction_l_srli"," * instruction : l.srli");
2887
2888	#ifdef STATISTICS
2889	inst->_opcod = INSTRUCTION_L_SRLI;
2890	#endif
2891	inst->_type = instruction_information(INSTRUCTION_L_SRLI)._type ; //TYPE_SHIFT;
2892	inst->_operation = instruction_information(INSTRUCTION_L_SRLI)._operation; //OPERATION_SHIFT_L_SRL;
2893	inst->_has_immediat = 1;
2894	inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0);
2895	inst->_read_ra = 1;
2896	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2897	inst->_read_rb = 0;
2898	inst->_num_reg_rb = 0; //unnecessary
2899	inst->_read_rc = 0;
2900	inst->_num_reg_rc = 0; //unnecessary
2901	inst->_write_rd = 1;
2902	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2903	inst->_write_re = 0;
2904	inst->_num_reg_re = 0; //unnecessary
2905	inst->_exception_use = EXCEPTION_USE_NONE;
2906	inst->_exception = EXCEPTION_DECOD_NONE;
2907	// inst->_branch_condition = ;
2908	// inst->_branch_stack_write = ;
2909	// inst->_branch_direction = ;
2910	// inst->_address_next = ; // already define : PC+4
2911	inst->_no_execute = 0;
2912	inst->_event_type = EVENT_TYPE_NONE;
2913	}
2914
2915	void instruction_l_sub (decod_instruction_t * inst, decod_param_t * param)
2916	{
2917	log_printf(TRACE,Decod,"instruction_l_sub"," * instruction : l.sub");
2918
2919	#ifdef STATISTICS
2920	inst->_opcod = INSTRUCTION_L_SUB;
2921	#endif
2922	inst->_type = instruction_information(INSTRUCTION_L_SUB)._type ; //TYPE_ALU;
2923	inst->_operation = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB;
2924	inst->_has_immediat = 0;
2925	inst->_immediat = 0; // unnecessary
2926	inst->_read_ra = 1;
2927	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2928	inst->_read_rb = 1;
2929	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2930	inst->_read_rc = 0;
2931	inst->_num_reg_rc = 0; //unnecessary
2932	inst->_write_rd = 1;
2933	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
2934	inst->_write_re = 1;
2935	inst->_num_reg_re = SPR_LOGIC_SR_CY_OV;
2936	inst->_exception_use = EXCEPTION_USE_RANGE;
2937	inst->_exception = EXCEPTION_DECOD_NONE;
2938	// inst->_branch_condition = ;
2939	// inst->_branch_stack_write = ;
2940	// inst->_branch_direction = ;
2941	// inst->_address_next = ; // already define : PC+4
2942	inst->_no_execute = 0;
2943	inst->_event_type = EVENT_TYPE_NONE;
2944	}
2945
2946	void instruction_l_sw (decod_instruction_t * inst, decod_param_t * param)
2947	{
2948	log_printf(TRACE,Decod,"instruction_l_sw"," * instruction : l.sw");
2949
2950	#ifdef STATISTICS
2951	inst->_opcod = INSTRUCTION_L_SW;
2952	#endif
2953	inst->_type = instruction_information(INSTRUCTION_L_SW)._type ; //TYPE_MEMORY;
2954	inst->_operation = instruction_information(INSTRUCTION_L_SW)._operation; //OPERATION_MEMORY_STORE_32;
2955	inst->_has_immediat = 1;
2956	inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)\|
2957	(range<Tgeneral_data_t >(inst->_instruction,10, 0))),16);
2958	inst->_read_ra = 1;
2959	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
2960	inst->_read_rb = 1;
2961	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
2962	inst->_read_rc = 0;
2963	inst->_num_reg_rc = 0; //unnecessary
2964	inst->_write_rd = 0;
2965	inst->_num_reg_rd = 0; //unnecessary
2966	inst->_write_re = 0;
2967	inst->_num_reg_re = 0; //unnecessary
2968	inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT;
2969	inst->_exception = EXCEPTION_DECOD_NONE;
2970	// inst->_branch_condition = ;
2971	// inst->_branch_stack_write = ;
2972	// inst->_branch_direction = ;
2973	// inst->_address_next = ; // already define : PC+4
2974	inst->_no_execute = 0;
2975	inst->_event_type = EVENT_TYPE_NONE;
2976	}
2977
2978	void instruction_l_sys (decod_instruction_t * inst, decod_param_t * param)
2979	{
2980	log_printf(TRACE,Decod,"instruction_l_sys"," * instruction : l.sys");
2981
2982	if (range<uint32_t>(inst->_instruction,22,16) != 0)
2983	{
2984	instruction_illegal (inst, param);
2985	}
2986	else
2987	{
2988	#ifdef STATISTICS
2989	inst->_opcod = INSTRUCTION_L_SYS;
2990	#endif
2991	inst->_type = instruction_information(INSTRUCTION_L_SYS)._type ; //TYPE_SPECIAL;
2992	inst->_operation = instruction_information(INSTRUCTION_L_SYS)._operation; //OPERATION_SPECIAL_L_SYS;
2993	// inst->_has_immediat = 1;
2994	// inst->_immediat = EXTENDZ(inst->_instruction,16);
2995	inst->_has_immediat = 0;
2996	inst->_immediat = 0; // unnecessary
2997	inst->_read_ra = 0;
2998	inst->_num_reg_ra = 0; //unnecessary
2999	inst->_read_rb = 0;
3000	inst->_num_reg_rb = 0; //unnecessary
3001	inst->_read_rc = 0;
3002	inst->_num_reg_rc = 0; //unnecessary
3003	inst->_write_rd = 0;
3004	inst->_num_reg_rd = 0; //unnecessary
3005	inst->_write_re = 0;
3006	inst->_num_reg_re = 0; //unnecessary
3007	inst->_exception_use = EXCEPTION_USE_SYSCALL;
3008	inst->_exception = EXCEPTION_SYSCALL;
3009	// inst->_branch_condition = ;
3010	// inst->_branch_stack_write = ;
3011	// inst->_branch_direction = ;
3012
3013	// if (inst->_is_delay_slot)
3014	// inst->_address_next = inst->_address_previous;
3015	// else
3016	// inst->_address_next = inst->_address;
3017
3018
3019	// inst->_address_next = ; // already define : PC+4 // don't change
3020	inst->_no_execute = 1;
3021	inst->_event_type = EVENT_TYPE_EXCEPTION;
3022	}
3023	}
3024
3025	void instruction_l_trap (decod_instruction_t * inst, decod_param_t * param)
3026	{
3027	log_printf(TRACE,Decod,"instruction_l_trap"," * instruction : l.trap");
3028
3029	if (range<uint32_t>(inst->_instruction,22,16) != 0)
3030	{
3031	instruction_illegal (inst, param);
3032	}
3033	else
3034	{
3035	#ifdef STATISTICS
3036	inst->_opcod = INSTRUCTION_L_TRAP;
3037	#endif
3038	inst->_type = instruction_information(INSTRUCTION_L_TRAP)._type ; //TYPE_SPECIAL;
3039	inst->_operation = instruction_information(INSTRUCTION_L_TRAP)._operation; //OPERATION_SPECIAL_L_TRAP;
3040	inst->_has_immediat = 1;
3041	inst->_immediat = EXTENDZ(inst->_instruction,16);
3042	inst->_read_ra = 0;
3043	inst->_num_reg_ra = 0; //unnecessary
3044	inst->_read_rb = 0;
3045	inst->_num_reg_rb = 0; //unnecessary
3046	inst->_read_rc = 0; // read all SR
3047	inst->_num_reg_rc = 0; //unnecessary
3048	inst->_write_rd = 0;
3049	inst->_num_reg_rd = 0; //unnecessary
3050	inst->_write_re = 0;
3051	inst->_num_reg_re = 0; //unnecessary
3052	inst->_exception_use = EXCEPTION_USE_TRAP;
3053	inst->_exception = EXCEPTION_DECOD_NONE;
3054	// inst->_branch_condition = ;
3055	// inst->_branch_stack_write = ;
3056	// inst->_branch_direction = ;
3057	// inst->_address_next = ; // already define : PC+4
3058	inst->_no_execute = 1;
3059	inst->_event_type = EVENT_TYPE_NONE;
3060	}
3061	}
3062
3063	void instruction_l_xor (decod_instruction_t * inst, decod_param_t * param)
3064	{
3065	log_printf(TRACE,Decod,"instruction_l_xor"," * instruction : l.xor");
3066
3067	#ifdef STATISTICS
3068	inst->_opcod = INSTRUCTION_L_XOR;
3069	#endif
3070	inst->_type = instruction_information(INSTRUCTION_L_XOR)._type ; //TYPE_ALU;
3071	inst->_operation = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR;
3072	inst->_has_immediat = 0;
3073	inst->_immediat = 0; // unnecessary
3074	inst->_read_ra = 1;
3075	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
3076	inst->_read_rb = 1;
3077	inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11);
3078	inst->_read_rc = 0;
3079	inst->_num_reg_rc = 0; //unnecessary
3080	inst->_write_rd = 1;
3081	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
3082	inst->_write_re = 0;
3083	inst->_num_reg_re = 0; //unnecessary
3084	inst->_exception_use = EXCEPTION_USE_NONE;
3085	inst->_exception = EXCEPTION_DECOD_NONE;
3086	// inst->_branch_condition = ;
3087	// inst->_branch_stack_write = ;
3088	// inst->_branch_direction = ;
3089	// inst->_address_next = ; // already define : PC+4
3090	inst->_no_execute = 0;
3091	inst->_event_type = EVENT_TYPE_NONE;
3092	}
3093
3094	void instruction_l_xori (decod_instruction_t * inst, decod_param_t * param)
3095	{
3096	log_printf(TRACE,Decod,"instruction_l_xori"," * instruction : l.xori");
3097
3098	#ifdef STATISTICS
3099	inst->_opcod = INSTRUCTION_L_XORI;
3100	#endif
3101	inst->_type = instruction_information(INSTRUCTION_L_XORI)._type ; //TYPE_ALU;
3102	inst->_operation = instruction_information(INSTRUCTION_L_XORI)._operation; //OPERATION_ALU_L_XOR;
3103	inst->_has_immediat = 1;
3104	inst->_immediat = EXTENDS(inst->_instruction,16);
3105	inst->_read_ra = 1;
3106	inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16);
3107	inst->_read_rb = 0;
3108	inst->_num_reg_rb = 0; //unnecessary
3109	inst->_read_rc = 0;
3110	inst->_num_reg_rc = 0; //unnecessary
3111	inst->_write_rd = 1;
3112	inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21);
3113	inst->_write_re = 0;
3114	inst->_num_reg_re = 0; //unnecessary
3115	inst->_exception_use = EXCEPTION_USE_NONE;
3116	inst->_exception = EXCEPTION_DECOD_NONE;
3117	// inst->_branch_condition = ;
3118	// inst->_branch_stack_write = ;
3119	// inst->_branch_direction = ;
3120	// inst->_address_next = ; // already define : PC+4
3121	inst->_no_execute = 0;
3122	inst->_event_type = EVENT_TYPE_NONE;
3123	}
3124
3125	// // ORFPX
3126	// void instruction_lf_add_d (decod_instruction_t * inst, decod_param_t * param)
3127	// void instruction_lf_add_s (decod_instruction_t * inst, decod_param_t * param)
3128	// void instruction_lf_cust1_d (decod_instruction_t * inst, decod_param_t * param)
3129	// void instruction_lf_cust1_s (decod_instruction_t * inst, decod_param_t * param)
3130	// void instruction_lf_div_d (decod_instruction_t * inst, decod_param_t * param)
3131	// void instruction_lf_div_s (decod_instruction_t * inst, decod_param_t * param)
3132	// void instruction_lf_ftoi_d (decod_instruction_t * inst, decod_param_t * param)
3133	// void instruction_lf_ftoi_s (decod_instruction_t * inst, decod_param_t * param)
3134	// void instruction_lf_itof_d (decod_instruction_t * inst, decod_param_t * param)
3135	// void instruction_lf_itof_s (decod_instruction_t * inst, decod_param_t * param)
3136	// void instruction_lf_madd_d (decod_instruction_t * inst, decod_param_t * param)
3137	// void instruction_lf_madd_s (decod_instruction_t * inst, decod_param_t * param)
3138	// void instruction_lf_mul_d (decod_instruction_t * inst, decod_param_t * param)
3139	// void instruction_lf_mul_s (decod_instruction_t * inst, decod_param_t * param)
3140	// void instruction_lf_rem_d (decod_instruction_t * inst, decod_param_t * param)
3141	// void instruction_lf_rem_s (decod_instruction_t * inst, decod_param_t * param)
3142	// void instruction_lf_sfeq_d (decod_instruction_t * inst, decod_param_t * param)
3143	// void instruction_lf_sfeq_s (decod_instruction_t * inst, decod_param_t * param)
3144	// void instruction_lf_sfge_d (decod_instruction_t * inst, decod_param_t * param)
3145	// void instruction_lf_sfge_s (decod_instruction_t * inst, decod_param_t * param)
3146	// void instruction_lf_sfgt_d (decod_instruction_t * inst, decod_param_t * param)
3147	// void instruction_lf_sfgt_s (decod_instruction_t * inst, decod_param_t * param)
3148	// void instruction_lf_sfle_d (decod_instruction_t * inst, decod_param_t * param)
3149	// void instruction_lf_sfle_s (decod_instruction_t * inst, decod_param_t * param)
3150	// void instruction_lf_sflt_d (decod_instruction_t * inst, decod_param_t * param)
3151	// void instruction_lf_sflt_s (decod_instruction_t * inst, decod_param_t * param)
3152	// void instruction_lf_sfne_d (decod_instruction_t * inst, decod_param_t * param)
3153	// void instruction_lf_sfne_s (decod_instruction_t * inst, decod_param_t * param)
3154	// void instruction_lf_sub_d (decod_instruction_t * inst, decod_param_t * param)
3155	// void instruction_lf_sub_s (decod_instruction_t * inst, decod_param_t * param)
3156
3157	// // ORVDX
3158	// void instruction_lv_add_b (decod_instruction_t * inst, decod_param_t * param)
3159	// void instruction_lv_add_h (decod_instruction_t * inst, decod_param_t * param)
3160	// void instruction_lv_adds_b (decod_instruction_t * inst, decod_param_t * param)
3161	// void instruction_lv_adds_h (decod_instruction_t * inst, decod_param_t * param)
3162	// void instruction_lv_addu_b (decod_instruction_t * inst, decod_param_t * param)
3163	// void instruction_lv_addu_h (decod_instruction_t * inst, decod_param_t * param)
3164	// void instruction_lv_addus_b (decod_instruction_t * inst, decod_param_t * param)
3165	// void instruction_lv_addus_h (decod_instruction_t * inst, decod_param_t * param)
3166	// void instruction_lv_all_eq_b (decod_instruction_t * inst, decod_param_t * param)
3167	// void instruction_lv_all_eq_h (decod_instruction_t * inst, decod_param_t * param)
3168	// void instruction_lv_all_ge_b (decod_instruction_t * inst, decod_param_t * param)
3169	// void instruction_lv_all_ge_h (decod_instruction_t * inst, decod_param_t * param)
3170	// void instruction_lv_all_gt_b (decod_instruction_t * inst, decod_param_t * param)
3171	// void instruction_lv_all_gt_h (decod_instruction_t * inst, decod_param_t * param)
3172	// void instruction_lv_all_le_b (decod_instruction_t * inst, decod_param_t * param)
3173	// void instruction_lv_all_le_h (decod_instruction_t * inst, decod_param_t * param)
3174	// void instruction_lv_all_lt_b (decod_instruction_t * inst, decod_param_t * param)
3175	// void instruction_lv_all_lt_h (decod_instruction_t * inst, decod_param_t * param)
3176	// void instruction_lv_all_ne_b (decod_instruction_t * inst, decod_param_t * param)
3177	// void instruction_lv_all_ne_h (decod_instruction_t * inst, decod_param_t * param)
3178	// void instruction_lv_and (decod_instruction_t * inst, decod_param_t * param)
3179	// void instruction_lv_any_eq_b (decod_instruction_t * inst, decod_param_t * param)
3180	// void instruction_lv_any_eq_h (decod_instruction_t * inst, decod_param_t * param)
3181	// void instruction_lv_any_ge_b (decod_instruction_t * inst, decod_param_t * param)
3182	// void instruction_lv_any_ge_h (decod_instruction_t * inst, decod_param_t * param)
3183	// void instruction_lv_any_gt_b (decod_instruction_t * inst, decod_param_t * param)
3184	// void instruction_lv_any_gt_h (decod_instruction_t * inst, decod_param_t * param)
3185	// void instruction_lv_any_le_b (decod_instruction_t * inst, decod_param_t * param)
3186	// void instruction_lv_any_le_h (decod_instruction_t * inst, decod_param_t * param)
3187	// void instruction_lv_any_lt_b (decod_instruction_t * inst, decod_param_t * param)
3188	// void instruction_lv_any_lt_h (decod_instruction_t * inst, decod_param_t * param)
3189	// void instruction_lv_any_ne_b (decod_instruction_t * inst, decod_param_t * param)
3190	// void instruction_lv_any_ne_h (decod_instruction_t * inst, decod_param_t * param)
3191	// void instruction_lv_avg_b (decod_instruction_t * inst, decod_param_t * param)
3192	// void instruction_lv_avg_h (decod_instruction_t * inst, decod_param_t * param)
3193	// void instruction_lv_cmp_eq_b (decod_instruction_t * inst, decod_param_t * param)
3194	// void instruction_lv_cmp_eq_h (decod_instruction_t * inst, decod_param_t * param)
3195	// void instruction_lv_cmp_ge_b (decod_instruction_t * inst, decod_param_t * param)
3196	// void instruction_lv_cmp_ge_h (decod_instruction_t * inst, decod_param_t * param)
3197	// void instruction_lv_cmp_gt_b (decod_instruction_t * inst, decod_param_t * param)
3198	// void instruction_lv_cmp_gt_h (decod_instruction_t * inst, decod_param_t * param)
3199	// void instruction_lv_cmp_le_b (decod_instruction_t * inst, decod_param_t * param)
3200	// void instruction_lv_cmp_le_h (decod_instruction_t * inst, decod_param_t * param)
3201	// void instruction_lv_cmp_lt_b (decod_instruction_t * inst, decod_param_t * param)
3202	// void instruction_lv_cmp_lt_h (decod_instruction_t * inst, decod_param_t * param)
3203	// void instruction_lv_cmp_ne_b (decod_instruction_t * inst, decod_param_t * param)
3204	// void instruction_lv_cmp_ne_h (decod_instruction_t * inst, decod_param_t * param)
3205	// void instruction_lv_cust1 (decod_instruction_t * inst, decod_param_t * param)
3206	// void instruction_lv_cust2 (decod_instruction_t * inst, decod_param_t * param)
3207	// void instruction_lv_cust3 (decod_instruction_t * inst, decod_param_t * param)
3208	// void instruction_lv_cust4 (decod_instruction_t * inst, decod_param_t * param)
3209	// void instruction_lv_madds_h (decod_instruction_t * inst, decod_param_t * param)
3210	// void instruction_lv_max_b (decod_instruction_t * inst, decod_param_t * param)
3211	// void instruction_lv_max_h (decod_instruction_t * inst, decod_param_t * param)
3212	// void instruction_lv_merge_b (decod_instruction_t * inst, decod_param_t * param)
3213	// void instruction_lv_merge_h (decod_instruction_t * inst, decod_param_t * param)
3214	// void instruction_lv_min_b (decod_instruction_t * inst, decod_param_t * param)
3215	// void instruction_lv_min_h (decod_instruction_t * inst, decod_param_t * param)
3216	// void instruction_lv_msubs_h (decod_instruction_t * inst, decod_param_t * param)
3217	// void instruction_lv_muls_h (decod_instruction_t * inst, decod_param_t * param)
3218	// void instruction_lv_nand (decod_instruction_t * inst, decod_param_t * param)
3219	// void instruction_lv_nor (decod_instruction_t * inst, decod_param_t * param)
3220	// void instruction_lv_or (decod_instruction_t * inst, decod_param_t * param)
3221	// void instruction_lv_pack_b (decod_instruction_t * inst, decod_param_t * param)
3222	// void instruction_lv_pack_h (decod_instruction_t * inst, decod_param_t * param)
3223	// void instruction_lv_packs_b (decod_instruction_t * inst, decod_param_t * param)
3224	// void instruction_lv_packs_h (decod_instruction_t * inst, decod_param_t * param)
3225	// void instruction_lv_packus_b (decod_instruction_t * inst, decod_param_t * param)
3226	// void instruction_lv_packus_h (decod_instruction_t * inst, decod_param_t * param)
3227	// void instruction_lv_perm_n (decod_instruction_t * inst, decod_param_t * param)
3228	// void instruction_lv_rl_b (decod_instruction_t * inst, decod_param_t * param)
3229	// void instruction_lv_rl_h (decod_instruction_t * inst, decod_param_t * param)
3230	// void instruction_lv_sll (decod_instruction_t * inst, decod_param_t * param)
3231	// void instruction_lv_sll_b (decod_instruction_t * inst, decod_param_t * param)
3232	// void instruction_lv_sll_h (decod_instruction_t * inst, decod_param_t * param)
3233	// void instruction_lv_sra_b (decod_instruction_t * inst, decod_param_t * param)
3234	// void instruction_lv_sra_h (decod_instruction_t * inst, decod_param_t * param)
3235	// void instruction_lv_srl (decod_instruction_t * inst, decod_param_t * param)
3236	// void instruction_lv_srl_b (decod_instruction_t * inst, decod_param_t * param)
3237	// void instruction_lv_srl_h (decod_instruction_t * inst, decod_param_t * param)
3238	// void instruction_lv_sub_b (decod_instruction_t * inst, decod_param_t * param)
3239	// void instruction_lv_sub_h (decod_instruction_t * inst, decod_param_t * param)
3240	// void instruction_lv_subs_b (decod_instruction_t * inst, decod_param_t * param)
3241	// void instruction_lv_subs_h (decod_instruction_t * inst, decod_param_t * param)
3242	// void instruction_lv_subu_b (decod_instruction_t * inst, decod_param_t * param)
3243	// void instruction_lv_subu_h (decod_instruction_t * inst, decod_param_t * param)
3244	// void instruction_lv_subus_b (decod_instruction_t * inst, decod_param_t * param)
3245	// void instruction_lv_subus_h (decod_instruction_t * inst, decod_param_t * param)
3246	// void instruction_lv_unpack_b (decod_instruction_t * inst, decod_param_t * param)
3247	// void instruction_lv_unpack_h (decod_instruction_t * inst, decod_param_t * param)
3248	// void instruction_lv_xor (decod_instruction_t * inst, decod_param_t * param)
3249
3250	}; // end namespace decod
3251	}; // end namespace decod_unit
3252	}; // end namespace front_end
3253	}; // end namespace multi_front_end
3254	}; // end namespace core
3255	}; // end namespace behavioural
3256	}; // end namespace morpheo

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp

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