/* * $Id: test.cpp 101 2009-01-15 17:19:08Z rosiere $ * * [ Description ] * * Test */ #define NB_ITERATION 1 #define CYCLE_MAX (2048*NB_ITERATION) #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/test.h" #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h" #include #include "Common/include/Test.h" #include "Behavioural/include/Allocation.h" void test (string name, morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * _param) { msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); #ifdef STATISTICS morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); #endif Tusage_t _usage = USE_ALL; // _usage = usage_unset(_usage,USE_SYSTEMC ); // _usage = usage_unset(_usage,USE_VHDL ); // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); // _usage = usage_unset(_usage,USE_POSITION ); // _usage = usage_unset(_usage,USE_STATISTICS ); // _usage = usage_unset(_usage,USE_INFORMATION ); Decod * _Decod = new Decod (name.c_str(), #ifdef STATISTICS _parameters_statistics, #endif _param, _usage); #ifdef SYSTEMC /********************************************************************* * Déclarations des signaux *********************************************************************/ string rename; sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); sc_signal * in_NRESET = new sc_signal ("NRESET"); ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID ," in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS ," in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context); // ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS_NEXT ," in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_IFETCH_INST_IFETCH_PTR ," in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE ," in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION ," in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context); ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod); // ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod); // ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod); ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t ); ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t ); ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t ); /******************************************************** * Instanciation ********************************************************/ msg(_("<%s> : Instanciation of _Decod.\n"),name.c_str()); (*(_Decod->in_CLOCK)) (*(in_CLOCK)); (*(_Decod->in_NRESET)) (*(in_NRESET)); INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1]); INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1]); INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]); if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS ,_param->_nb_context); // INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION ,_param->_nb_context); for (uint32_t i=0; i<_param->_nb_context; i++) { if (_param->_have_port_inst_ifetch_ptr) INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]); // if (_param->_have_port_branch_update_prediction_id) if (_param->_have_port_depth) INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); } INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK ,_param->_nb_inst_decod); if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod); if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_DEPTH ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RA ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RB ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RC ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RD ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK ,_param->_nb_inst_decod); if (_param->_have_port_context_id) INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod); // if (_param->_have_port_branch_update_prediction_id) if (_param->_have_port_depth) INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod); // INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod); // INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH_VAL ,_param->_nb_context); for (uint32_t i=0; i<_param->_nb_context; i++) if (_param->_have_port_depth) INSTANCE_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]); INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL ); INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK ); if (_param->_have_port_context_id) INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID ); if (_param->_have_port_depth) INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_DEPTH ); INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE ); INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT ); INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS ); INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); Time * _time = new Time(); /******************************************************** * Simulation - Begin ********************************************************/ // Initialisation const uint32_t seed = 0; //const uint32_t seed = static_cast(time(NULL)); const int32_t percent_transaction_ifetch = 75; const int32_t percent_transaction_decod = 75; const int32_t percent_transaction_predict = 75; const int32_t percent_transaction_event = 75; srand(seed); SC_START(0); LABEL("Initialisation"); LABEL("Reset"); in_NRESET->write(0); SC_START(5); in_NRESET->write(1); LABEL("Loop of Test"); for (uint32_t i=0; i<_param->_nb_context; i++) in_CONTEXT_DEPTH_VAL [i]->write(1); for (uint32_t iteration=0; iteration_nb_context]; uint32_t nb_request = 0; uint32_t delay_slot_previous [_param->_nb_context]; uint32_t delay_slot_current [_param->_nb_context]; uint32_t delay_slot_next [_param->_nb_context]; for (uint32_t i=0; i<_param->_nb_context; i++) { nb_request += request[i].size(); delay_slot_current [i] = false; delay_slot_next [i] = false; } while (nb_request > 0) { for (uint32_t i=0; i<_param->_nb_context; i++) { delay_slot_previous [i] = false; in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)_nb_inst_fetch[i]; j++) in_IFETCH_VAL [i][j]->write(0); if ((rand()%100)::iterator it = request[i].begin(); if (it!=request [i].end()) { uint32_t lsb = it->_address%_param->_nb_inst_fetch[i]; in_IFETCH_ADDRESS [i]->write(it->_address-lsb); in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE); if (_param->_have_port_inst_ifetch_ptr) in_IFETCH_INST_IFETCH_PTR [i]->write(0); in_IFETCH_EXCEPTION [i]->write(EXCEPTION_IFETCH_NONE); // Alignement for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++) { in_IFETCH_VAL [i][j]->write(1); in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction); // in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next); if (it->_type == TYPE_BRANCH) in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state); in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id); if ((it->_is_delay_slot) or ((++it)==request [i].end())) break; } } } } { bool previous_ack = true; for (uint32_t i=0; i<_param->_nb_inst_decod; i++) { bool ack = previous_ack and ((rand()%100)write(ack); previous_ack = ack; in_PREDICT_ACK [i]->write((rand()%100)write(0); } } in_CONTEXT_EVENT_ACK->write((rand()%100)_nb_context; i++) for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read()) { LABEL("IFETCH [%d][%d] : transaction",i,j); nb_inst_ifetch ++; } uint32_t nb_inst_decod = 0; uint32_t find_event = false; for (uint32_t i=0; i<_param->_nb_inst_decod; i++) if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read()) { Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0; LABEL("DECOD [%d] : transaction",i ); LABEL(" * context : %d",context); LABEL(" * instruction : 0x%x",request [context].front()._instruction); if (_param->_have_port_depth) TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), request [context].front()._depth ); TEST(Ttype_t , out_DECOD_TYPE [i]->read(), request [context].front()._type ); TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), request [context].front()._operation ); TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), request [context].front()._is_delay_slot); TEST(Tcontrol_t , delay_slot_current [context] , request [context].front()._is_delay_slot); TEST(Tgeneral_data_t , out_DECOD_ADDRESS [i]->read(), request [context].front()._address ); TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), request [context].front()._has_immediat ); if (request [context].front()._has_immediat) TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), request [context].front()._immediat ); TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), request [context].front()._read_ra ); if (request [context].front()._read_ra) TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), request [context].front()._num_reg_ra ); TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), request [context].front()._read_rb ); if (request [context].front()._read_rb) TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), request [context].front()._num_reg_rb ); TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), request [context].front()._read_rc ); if (request [context].front()._read_rc) TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), request [context].front()._num_reg_rc ); TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), request [context].front()._write_rd ); if (request [context].front()._write_rd) TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), request [context].front()._num_reg_rd ); TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), request [context].front()._write_re ); if (request [context].front()._write_re) TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), request [context].front()._num_reg_re ); TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), request [context].front()._exception_use); if (request [context].front()._type == TYPE_BRANCH) { delay_slot_next [context] = true; TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), true); TEST(Tcontrol_t, in_PREDICT_ACK[i]->read(), true); LABEL("PREDICT [%d] : transaction",i ); if (_param->_have_port_context_id) TEST(Tcontext_t , out_PREDICT_CONTEXT_ID [i]->read(), context); TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0); TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [i]->read(), request [context].front()._branch_state ); // if (_param->_have_port_branch_update_prediction_id) if (_param->_have_port_depth) TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id); TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [i]->read(), request [context].front()._branch_condition ); // TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [i]->read(), request [context].front()._branch_stack_write ); TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [i]->read(), request [context].front()._branch_direction ); TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i]->read(), request [context].front()._address ); TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i]->read(), request [context].front()._branch_address_dest ); } else { TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), false); } TEST(bool, find_event, false); // can continue decod after event if (request [context].front()._context_event_type != EVENT_TYPE_NONE) { find_event = true; LABEL("CONTEXT_EVENT : transaction"); if (_param->_have_port_context_id) TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), context); if (_param->_have_port_depth ) TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), request [context].front()._depth ); TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), request [context].front()._context_event_type); TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot); TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), request [context].front()._address ); TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), request [context].front()._address_next ); } TEST(bool, delay_slot_previous [context], false); // can't continue delay_slot_previous [context] = delay_slot_current [context]; delay_slot_current [context] = delay_slot_next [context]; delay_slot_next [context] = false; request [context].pop_front(); nb_inst_decod ++; nb_request --; } TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event); TEST(uint32_t, nb_inst_decod, nb_inst_ifetch); SC_START(1); } } /******************************************************** * Simulation - End ********************************************************/ TEST_OK ("End of Simulation"); delete _time; msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); delete in_CLOCK; delete in_NRESET; delete [] in_IFETCH_VAL ; delete [] out_IFETCH_ACK ; delete [] in_IFETCH_INSTRUCTION ; delete [] in_IFETCH_CONTEXT_ID ; delete [] in_IFETCH_ADDRESS ; // delete [] in_IFETCH_ADDRESS_NEXT ; delete [] in_IFETCH_INST_IFETCH_PTR ; delete [] in_IFETCH_BRANCH_STATE ; delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ; delete [] in_IFETCH_EXCEPTION ; delete [] out_DECOD_VAL ; delete [] in_DECOD_ACK ; delete [] out_DECOD_CONTEXT_ID ; delete [] out_DECOD_DEPTH ; delete [] out_DECOD_TYPE ; delete [] out_DECOD_OPERATION ; delete [] out_DECOD_NO_EXECUTE ; delete [] out_DECOD_IS_DELAY_SLOT ; delete [] out_DECOD_ADDRESS ; delete [] out_DECOD_HAS_IMMEDIAT ; delete [] out_DECOD_IMMEDIAT ; delete [] out_DECOD_READ_RA ; delete [] out_DECOD_NUM_REG_RA ; delete [] out_DECOD_READ_RB ; delete [] out_DECOD_NUM_REG_RB ; delete [] out_DECOD_READ_RC ; delete [] out_DECOD_NUM_REG_RC ; delete [] out_DECOD_WRITE_RD ; delete [] out_DECOD_NUM_REG_RD ; delete [] out_DECOD_WRITE_RE ; delete [] out_DECOD_NUM_REG_RE ; delete [] out_DECOD_EXCEPTION_USE ; delete [] out_DECOD_EXCEPTION ; delete [] out_PREDICT_VAL ; delete [] in_PREDICT_ACK ; delete [] out_PREDICT_CONTEXT_ID ; delete [] out_PREDICT_MATCH_INST_IFETCH_PTR ; delete [] out_PREDICT_BRANCH_STATE ; delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID; delete [] out_PREDICT_BRANCH_CONDITION ; //delete [] out_PREDICT_BRANCH_STACK_WRITE ; delete [] out_PREDICT_BRANCH_DIRECTION ; delete [] out_PREDICT_ADDRESS_SRC ; delete [] out_PREDICT_ADDRESS_DEST ; //delete [] in_PREDICT_CAN_CONTINUE ; delete [] in_CONTEXT_DECOD_ENABLE ; delete [] in_CONTEXT_DEPTH_VAL ; delete [] in_CONTEXT_DEPTH ; delete out_CONTEXT_EVENT_VAL ; delete in_CONTEXT_EVENT_ACK ; delete out_CONTEXT_EVENT_CONTEXT_ID ; delete out_CONTEXT_EVENT_DEPTH ; delete out_CONTEXT_EVENT_TYPE ; delete out_CONTEXT_EVENT_IS_DELAY_SLOT ; delete out_CONTEXT_EVENT_ADDRESS ; delete out_CONTEXT_EVENT_ADDRESS_EPCR ; #endif delete _Decod; #ifdef STATISTICS delete _parameters_statistics; #endif }