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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp @ 108

Last change on this file since 108 was 108, checked in by rosiere, 15 years ago
1) decod_queue : add reg_LAST_SLOT. 2) Commit : insert on event -> to pop decod_queue. Head test : add information (speculative or not) 3) Context State / UPT : Branch miss and Load miss in same cycle. 4) Free List : Bank is on LSB not MSB. 5) Platforms : move data
Property svn:keywords set to `Id`
File size: 28.3 KB

Line
1	/*
2	* $Id: test.cpp 108 2009-02-12 11:55:06Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (2048*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/test.h"
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h"
14	#include <list>
15	#include "Common/include/Test.h"
16	#include "Behavioural/include/Allocation.h"
17
18	void test (string name,
19	morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * _param)
20	{
21	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
22
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
25	#endif
26
27	Tusage_t _usage = USE_ALL;
28
29	// _usage = usage_unset(_usage,USE_SYSTEMC );
30	// _usage = usage_unset(_usage,USE_VHDL );
31	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
32	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
33	// _usage = usage_unset(_usage,USE_POSITION );
34	// _usage = usage_unset(_usage,USE_STATISTICS );
35	// _usage = usage_unset(_usage,USE_INFORMATION );
36
37	Decod * _Decod = new Decod
38	(name.c_str(),
39	#ifdef STATISTICS
40	_parameters_statistics,
41	#endif
42	_param,
43	_usage);
44
45	#ifdef SYSTEMC
46	/*********************************************************************
47	* Déclarations des signaux
48	*********************************************************************/
49	string rename;
50
51	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
52	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
53
54	ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
55	ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
56	ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
57	ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID ," in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
58	ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS ," in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context);
59	// ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS_NEXT ," in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context);
60	ALLOC1_SC_SIGNAL( in_IFETCH_INST_IFETCH_PTR ," in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context);
61	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE ," in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context);
62	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context);
63	ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION ," in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context);
64
65	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
66	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
67	ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
68	ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
69	ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod);
70	ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod);
71	ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod);
72	ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod);
73	#ifdef DEBUG
74	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod);
75	#endif
76	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod);
77	ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod);
78	ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod);
79	ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod);
80	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod);
81	ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod);
82	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod);
83	ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod);
84	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod);
85	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod);
86	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod);
87	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
98	// ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod);
99	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod);
101	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod);
102	// ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);
103	ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context);
104	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
105	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context);
106	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t );
107	ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t );
108	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t );
109	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t );
110	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t );
111	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
112	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t );
113	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t );
114
115	/********************************************************
116	* Instanciation
117	********************************************************/
118
119	msg(_("<%s> : Instanciation of _Decod.\n"),name.c_str());
120
121	((_Decod->in_CLOCK)) ((in_CLOCK));
122	((_Decod->in_NRESET)) ((in_NRESET));
123
124	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
125	INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
126	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
127	if (_param->_have_port_context_id)
128	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID ,_param->_nb_context);
129	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS ,_param->_nb_context);
130	// INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT ,_param->_nb_context);
131	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE ,_param->_nb_context);
132	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION ,_param->_nb_context);
133
134	for (uint32_t i=0; i<_param->_nb_context; i++)
135	{
136	if (_param->_have_port_inst_ifetch_ptr)
137	INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]);
138	// if (_param->_have_port_branch_update_prediction_id)
139	if (_param->_have_port_depth)
140	INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]);
141	}
142
143	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL ,_param->_nb_inst_decod);
144	INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK ,_param->_nb_inst_decod);
145	if (_param->_have_port_context_id)
146	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
147	if (_param->_have_port_depth)
148	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_DEPTH ,_param->_nb_inst_decod);
149	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE ,_param->_nb_inst_decod);
150	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION ,_param->_nb_inst_decod);
151	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod);
152	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod);
153	#ifdef DEBUG
154	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod);
155	#endif
156	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod);
157	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod);
158	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod);
159	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RA ,_param->_nb_inst_decod);
160	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod);
161	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RB ,_param->_nb_inst_decod);
162	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod);
163	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RC ,_param->_nb_inst_decod);
164	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod);
165	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RD ,_param->_nb_inst_decod);
166	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod);
167	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RE ,_param->_nb_inst_decod);
168	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod);
169	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod);
170	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION ,_param->_nb_inst_decod);
171	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL ,_param->_nb_inst_decod);
172	INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK ,_param->_nb_inst_decod);
173	if (_param->_have_port_context_id)
174	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod);
175	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod);
176	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod);
177	// if (_param->_have_port_branch_update_prediction_id)
178	if (_param->_have_port_depth)
179	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod);
181	// INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod);
183	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod);
184	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod);
185	// INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);
186	INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context);
187	INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH_VAL ,_param->_nb_context);
188	for (uint32_t i=0; i<_param->_nb_context; i++)
189	if (_param->_have_port_depth)
190	INSTANCE_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]);
191	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL );
192	INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK );
193	if (_param->_have_port_context_id)
194	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID );
195	if (_param->_have_port_depth)
196	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_DEPTH );
197	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE );
198	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT );
199	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS );
200	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR );
201
202	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
203
204	Time * _time = new Time();
205
206	/********************************************************
207	* Simulation - Begin
208	********************************************************/
209
210	// Initialisation
211
212	const uint32_t seed = 0;
213	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
214
215	const int32_t percent_transaction_ifetch = 75;
216	const int32_t percent_transaction_decod = 75;
217	const int32_t percent_transaction_predict = 75;
218	const int32_t percent_transaction_event = 75;
219
220	srand(seed);
221
222	SC_START(0);
223	LABEL("Initialisation");
224
225	LABEL("Reset");
226	in_NRESET->write(0);
227	SC_START(5);
228	in_NRESET->write(1);
229
230	LABEL("Loop of Test");
231
232	for (uint32_t i=0; i<_param->_nb_context; i++)
233	in_CONTEXT_DEPTH_VAL [i]->write(1);
234
235	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
236	{
237	LABEL("Iteration %d",iteration);
238
239	Decod_request request [_param->_nb_context];
240
241	uint32_t nb_request = 0;
242
243	uint32_t delay_slot_previous [_param->_nb_context];
244	uint32_t delay_slot_current [_param->_nb_context];
245	uint32_t delay_slot_next [_param->_nb_context];
246
247	for (uint32_t i=0; i<_param->_nb_context; i++)
248	{
249	nb_request += request[i].size();
250	delay_slot_current [i] = false;
251	delay_slot_next [i] = false;
252	}
253
254	while (nb_request > 0)
255	{
256	for (uint32_t i=0; i<_param->_nb_context; i++)
257	{
258	delay_slot_previous [i] = false;
259
260	in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)<percent_transaction_decod);
261
262	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
263	in_IFETCH_VAL [i][j]->write(0);
264
265	if ((rand()%100)<percent_transaction_ifetch)
266	{
267	list<entry_t>::iterator it = request[i].begin();
268
269	if (it!=request [i].end())
270	{
271	uint32_t lsb = it->_address%_param->_nb_inst_fetch[i];
272
273	in_IFETCH_ADDRESS [i]->write(it->_address-lsb);
274	in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE);
275	if (_param->_have_port_inst_ifetch_ptr)
276	in_IFETCH_INST_IFETCH_PTR [i]->write(0);
277	in_IFETCH_EXCEPTION [i]->write(EXCEPTION_IFETCH_NONE);
278
279	// Alignement
280	for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++)
281	{
282	in_IFETCH_VAL [i][j]->write(1);
283	in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction);
284	// in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next);
285	if (it->_type == TYPE_BRANCH)
286	in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state);
287	in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id);
288
289	if ((it->_is_delay_slot) or
290	((++it)==request [i].end()))
291	break;
292	}
293	}
294	}
295	}
296
297	{
298	bool previous_ack = true;
299
300	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
301	{
302	bool ack = previous_ack and ((rand()%100)<percent_transaction_decod);
303	in_DECOD_ACK [i]->write(ack);
304
305	previous_ack = ack;
306
307	in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict);
308	// in_PREDICT_CAN_CONTINUE [i]->write(0);
309	}
310	}
311
312	in_CONTEXT_EVENT_ACK->write((rand()%100)<percent_transaction_event);
313
314	SC_START(0);
315
316
317	uint32_t nb_inst_ifetch = 0;
318	for (uint32_t i=0; i<_param->_nb_context; i++)
319	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
320	if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read())
321	{
322	LABEL("IFETCH [%d][%d] : transaction",i,j);
323	nb_inst_ifetch ++;
324	}
325
326	uint32_t nb_inst_decod = 0;
327	uint32_t find_event = false;
328
329	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
330	if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read())
331	{
332	Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0;
333
334	LABEL("DECOD [%d] : transaction",i );
335	LABEL(" * context : %d",context);
336	LABEL(" * instruction : 0x%x",request [context].front()._instruction);
337
338	if (_param->_have_port_depth)
339	TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), request [context].front()._depth );
340	TEST(Ttype_t , out_DECOD_TYPE [i]->read(), request [context].front()._type );
341	TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), request [context].front()._operation );
342	TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), request [context].front()._is_delay_slot);
343	TEST(Tcontrol_t , delay_slot_current [context] , request [context].front()._is_delay_slot);
344	// TEST(Tgeneral_data_t , out_DECOD_ADDRESS_NEXT [i]->read(), request [context].front()._address_next );
345	TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), request [context].front()._has_immediat );
346	if (request [context].front()._has_immediat)
347	TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), request [context].front()._immediat );
348	TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), request [context].front()._read_ra );
349	if (request [context].front()._read_ra)
350	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), request [context].front()._num_reg_ra );
351	TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), request [context].front()._read_rb );
352	if (request [context].front()._read_rb)
353	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), request [context].front()._num_reg_rb );
354	TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), request [context].front()._read_rc );
355	if (request [context].front()._read_rc)
356	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), request [context].front()._num_reg_rc );
357	TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), request [context].front()._write_rd );
358	if (request [context].front()._write_rd)
359	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), request [context].front()._num_reg_rd );
360	TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), request [context].front()._write_re );
361	if (request [context].front()._write_re)
362	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), request [context].front()._num_reg_re );
363	TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), request [context].front()._exception_use);
364
365	if (request [context].front()._type == TYPE_BRANCH)
366	{
367	delay_slot_next [context] = true;
368
369	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), true);
370	TEST(Tcontrol_t, in_PREDICT_ACK[i]->read(), true);
371
372	LABEL("PREDICT [%d] : transaction",i );
373
374	if (_param->_have_port_context_id)
375	TEST(Tcontext_t , out_PREDICT_CONTEXT_ID [i]->read(), context);
376	TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0);
377	TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [i]->read(), request [context].front()._branch_state );
378	// if (_param->_have_port_branch_update_prediction_id)
379	if (_param->_have_port_depth)
380	TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id);
381	TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [i]->read(), request [context].front()._branch_condition );
382	// TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [i]->read(), request [context].front()._branch_stack_write );
383	TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [i]->read(), request [context].front()._branch_direction );
384	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i]->read(), request [context].front()._address );
385	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i]->read(), request [context].front()._branch_address_dest );
386	}
387	else
388	{
389	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), false);
390	}
391
392	TEST(bool, find_event, false); // can continue decod after event
393	if (request [context].front()._context_event_type != EVENT_TYPE_NONE)
394	{
395	find_event = true;
396
397	LABEL("CONTEXT_EVENT : transaction");
398
399	if (_param->_have_port_context_id)
400	TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), context);
401	if (_param->_have_port_depth )
402	TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), request [context].front()._depth );
403	TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), request [context].front()._context_event_type);
404	TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot);
405	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), request [context].front()._address );
406	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), request [context].front()._address_next );
407
408	}
409
410	TEST(bool, delay_slot_previous [context], false); // can't continue
411	delay_slot_previous [context] = delay_slot_current [context];
412	delay_slot_current [context] = delay_slot_next [context];
413	delay_slot_next [context] = false;
414
415	request [context].pop_front();
416	nb_inst_decod ++;
417	nb_request --;
418	}
419
420	TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event);
421	TEST(uint32_t, nb_inst_decod, nb_inst_ifetch);
422
423	SC_START(1);
424	}
425	}
426
427	/********************************************************
428	* Simulation - End
429	********************************************************/
430
431	TEST_OK ("End of Simulation");
432	delete _time;
433
434	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
435
436	delete in_CLOCK;
437	delete in_NRESET;
438
439	delete [] in_IFETCH_VAL ;
440	delete [] out_IFETCH_ACK ;
441	delete [] in_IFETCH_INSTRUCTION ;
442	delete [] in_IFETCH_CONTEXT_ID ;
443	delete [] in_IFETCH_ADDRESS ;
444	// delete [] in_IFETCH_ADDRESS_NEXT ;
445	delete [] in_IFETCH_INST_IFETCH_PTR ;
446	delete [] in_IFETCH_BRANCH_STATE ;
447	delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;
448	delete [] in_IFETCH_EXCEPTION ;
449
450	delete [] out_DECOD_VAL ;
451	delete [] in_DECOD_ACK ;
452	delete [] out_DECOD_CONTEXT_ID ;
453	delete [] out_DECOD_DEPTH ;
454	delete [] out_DECOD_TYPE ;
455	delete [] out_DECOD_OPERATION ;
456	delete [] out_DECOD_NO_EXECUTE ;
457	delete [] out_DECOD_IS_DELAY_SLOT ;
458	#ifdef DEBUG
459	delete [] out_DECOD_ADDRESS ;
460	#endif
461	delete [] out_DECOD_ADDRESS_NEXT ;
462	delete [] out_DECOD_HAS_IMMEDIAT ;
463	delete [] out_DECOD_IMMEDIAT ;
464	delete [] out_DECOD_READ_RA ;
465	delete [] out_DECOD_NUM_REG_RA ;
466	delete [] out_DECOD_READ_RB ;
467	delete [] out_DECOD_NUM_REG_RB ;
468	delete [] out_DECOD_READ_RC ;
469	delete [] out_DECOD_NUM_REG_RC ;
470	delete [] out_DECOD_WRITE_RD ;
471	delete [] out_DECOD_NUM_REG_RD ;
472	delete [] out_DECOD_WRITE_RE ;
473	delete [] out_DECOD_NUM_REG_RE ;
474	delete [] out_DECOD_EXCEPTION_USE ;
475	delete [] out_DECOD_EXCEPTION ;
476
477	delete [] out_PREDICT_VAL ;
478	delete [] in_PREDICT_ACK ;
479	delete [] out_PREDICT_CONTEXT_ID ;
480	delete [] out_PREDICT_MATCH_INST_IFETCH_PTR ;
481	delete [] out_PREDICT_BRANCH_STATE ;
482	delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
483	delete [] out_PREDICT_BRANCH_CONDITION ;
484	//delete [] out_PREDICT_BRANCH_STACK_WRITE ;
485	delete [] out_PREDICT_BRANCH_DIRECTION ;
486	delete [] out_PREDICT_ADDRESS_SRC ;
487	delete [] out_PREDICT_ADDRESS_DEST ;
488	//delete [] in_PREDICT_CAN_CONTINUE ;
489
490	delete [] in_CONTEXT_DECOD_ENABLE ;
491	delete [] in_CONTEXT_DEPTH_VAL ;
492	delete [] in_CONTEXT_DEPTH ;
493
494	delete out_CONTEXT_EVENT_VAL ;
495	delete in_CONTEXT_EVENT_ACK ;
496	delete out_CONTEXT_EVENT_CONTEXT_ID ;
497	delete out_CONTEXT_EVENT_DEPTH ;
498	delete out_CONTEXT_EVENT_TYPE ;
499	delete out_CONTEXT_EVENT_IS_DELAY_SLOT ;
500	delete out_CONTEXT_EVENT_ADDRESS ;
501	delete out_CONTEXT_EVENT_ADDRESS_EPCR ;
502	#endif
503
504	delete _Decod;
505	#ifdef STATISTICS
506	delete _parameters_statistics;
507	#endif
508	}

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