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test.cpp @ 113

Last change on this file since 113 was 113, checked in by rosiere, 15 years ago
1) Add modelsim simulation systemC 2) Modelsim cosimulation systemC / VHDL is not finish !!!! (cf execute_queue and write_unit) 3) Add multi architecture 5) Add template for comparator, multiplier and divider 6) Change Message Warning) Various test macro have change, many selftest can't compile
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File size: 33.5 KB

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1	/*
2	* $Id: test.cpp 113 2009-04-14 18:39:12Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (2048*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/test.h"
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h"
14	#include <list>
15	#include "Common/include/Test.h"
16	#include "Behavioural/include/Allocation.h"
17
18	void test (string name,
19	morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * _param)
20	{
21	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
22
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
25	#endif
26
27	Tusage_t _usage = USE_ALL;
28
29	// _usage = usage_unset(_usage,USE_SYSTEMC );
30	// _usage = usage_unset(_usage,USE_VHDL );
31	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
32	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
33	// _usage = usage_unset(_usage,USE_POSITION );
34	// _usage = usage_unset(_usage,USE_STATISTICS );
35	// _usage = usage_unset(_usage,USE_INFORMATION );
36
37	Decod * _Decod = new Decod
38	(name.c_str(),
39	#ifdef STATISTICS
40	_parameters_statistics,
41	#endif
42	_param,
43	_usage);
44
45	#ifdef SYSTEMC
46	/*********************************************************************
47	* Déclarations des signaux
48	*********************************************************************/
49	string rename;
50
51	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
52	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
53
54	sc_signal<Tcontrol_t > *** in_IFETCH_VAL ;//[nb_context][nb_inst_fetch]
55	sc_signal<Tcontrol_t > *** out_IFETCH_ACK ;//[nb_context][nb_inst_fetch]
56	sc_signal<Tinstruction_t > *** in_IFETCH_INSTRUCTION ;//[nb_context][nb_inst_fetch]
57	sc_signal<Tcontext_t > ** in_IFETCH_CONTEXT_ID ;//[nb_context]
58	sc_signal<Tgeneral_address_t > ** in_IFETCH_ADDRESS ;//[nb_context]
59	//sc_signal<Tgeneral_address_t > ** in_IFETCH_ADDRESS_NEXT ;//[nb_context]
60	sc_signal<Tinst_ifetch_ptr_t > ** in_IFETCH_INST_IFETCH_PTR ;//[nb_context]
61	sc_signal<Tbranch_state_t > ** in_IFETCH_BRANCH_STATE ;//[nb_context]
62	sc_signal<Tprediction_ptr_t > ** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;//[nb_context]
63	sc_signal<Texception_t > ** in_IFETCH_EXCEPTION ;//[nb_context]
64	sc_signal<Tcontrol_t > ** out_DECOD_VAL ;//[nb_inst_decod]
65	sc_signal<Tcontrol_t > ** in_DECOD_ACK ;//[nb_inst_decod]
66	sc_signal<Tcontext_t > ** out_DECOD_CONTEXT_ID ;//[nb_inst_decod]
67	sc_signal<Tdepth_t > ** out_DECOD_DEPTH ;//[nb_inst_decod]
68	sc_signal<Ttype_t > ** out_DECOD_TYPE ;//[nb_inst_decod]
69	sc_signal<Toperation_t > ** out_DECOD_OPERATION ;//[nb_inst_decod]
70	sc_signal<Tcontrol_t > ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod]
71	sc_signal<Tcontrol_t > ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod]
72	sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS ;//[nb_inst_decod]
73	sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS_NEXT ;//[nb_inst_decod]
74	sc_signal<Tcontrol_t > ** out_DECOD_HAS_IMMEDIAT ;//[nb_inst_decod]
75	sc_signal<Tgeneral_data_t > ** out_DECOD_IMMEDIAT ;//[nb_inst_decod]
76	sc_signal<Tcontrol_t > ** out_DECOD_READ_RA ;//[nb_inst_decod]
77	sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RA ;//[nb_inst_decod]
78	sc_signal<Tcontrol_t > ** out_DECOD_READ_RB ;//[nb_inst_decod]
79	sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RB ;//[nb_inst_decod]
80	sc_signal<Tcontrol_t > ** out_DECOD_READ_RC ;//[nb_inst_decod]
81	sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RC ;//[nb_inst_decod]
82	sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RD ;//[nb_inst_decod]
83	sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RD ;//[nb_inst_decod]
84	sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RE ;//[nb_inst_decod]
85	sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RE ;//[nb_inst_decod]
86	sc_signal<Texception_t > ** out_DECOD_EXCEPTION_USE ;//[nb_inst_decod]
87	sc_signal<Texception_t > ** out_DECOD_EXCEPTION ;//[nb_inst_decod]
88	sc_signal<Tcontrol_t > ** out_PREDICT_VAL ;//[nb_inst_decod]
89	sc_signal<Tcontrol_t > ** in_PREDICT_ACK ;//[nb_inst_decod]
90	sc_signal<Tcontext_t > ** out_PREDICT_CONTEXT_ID ;//[nb_inst_decod]
91	sc_signal<Tcontrol_t > ** out_PREDICT_MATCH_INST_IFETCH_PTR ;//[nb_inst_decod]
92	sc_signal<Tbranch_state_t > ** out_PREDICT_BRANCH_STATE ;//[nb_inst_decod]
93	sc_signal<Tprediction_ptr_t > ** out_PREDICT_BRANCH_UPDATE_PREDICTION_ID;//[nb_inst_decod]
94	sc_signal<Tbranch_condition_t> ** out_PREDICT_BRANCH_CONDITION ;//[nb_inst_decod]
95	//sc_signal<Tcontrol_t > ** out_PREDICT_BRANCH_STACK_WRITE ;//[nb_inst_decod]
96	sc_signal<Tcontrol_t > ** out_PREDICT_BRANCH_DIRECTION ;//[nb_inst_decod]
97	sc_signal<Tgeneral_data_t > ** out_PREDICT_ADDRESS_SRC ;//[nb_inst_decod]
98	sc_signal<Tgeneral_data_t > ** out_PREDICT_ADDRESS_DEST ;//[nb_inst_decod]
99	sc_signal<Tcontrol_t > ** in_PREDICT_CAN_CONTINUE ;//[nb_inst_decod]
100	sc_signal<Tcontrol_t > ** in_CONTEXT_DECOD_ENABLE ;//[nb_context]
101	sc_signal<Tcontrol_t > ** in_CONTEXT_DEPTH_VAL ;//[nb_context]
102	sc_signal<Tdepth_t > ** in_CONTEXT_DEPTH ;//[nb_context]
103	sc_signal<Tcontrol_t > * out_CONTEXT_EVENT_VAL ;
104	sc_signal<Tcontrol_t > * in_CONTEXT_EVENT_ACK ;
105	sc_signal<Tcontext_t > * out_CONTEXT_EVENT_CONTEXT_ID ;
106	sc_signal<Tdepth_t > * out_CONTEXT_EVENT_DEPTH ;
107	sc_signal<Tevent_type_t > * out_CONTEXT_EVENT_TYPE ;
108	sc_signal<Tcontrol_t > * out_CONTEXT_EVENT_IS_DELAY_SLOT ;
109	sc_signal<Tgeneral_data_t > * out_CONTEXT_EVENT_ADDRESS ;
110	sc_signal<Tgeneral_data_t > * out_CONTEXT_EVENT_ADDRESS_EPCR ;
111
112	ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
113	ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
114	ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
115	ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID ," in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
116	ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS ," in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context);
117	// ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS_NEXT ," in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context);
118	ALLOC1_SC_SIGNAL( in_IFETCH_INST_IFETCH_PTR ," in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE ," in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context);
121	ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION ," in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context);
122
123	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
124	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
125	ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
126	ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
127	ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod);
128	ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod);
129	ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod);
130	ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod);
131	#ifdef DEBUG
132	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod);
133	#endif
134	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod);
135	ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod);
136	ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod);
137	ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod);
138	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod);
139	ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod);
140	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod);
141	ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod);
142	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod);
143	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod);
144	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod);
145	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod);
146	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod);
147	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod);
148	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod);
149	ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
150	ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
151	ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
152	ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod);
153	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod);
154	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod);
155	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
156	// ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod);
157	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod);
158	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod);
159	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod);
160	ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);
161	ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context);
162	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
163	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context);
164	ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t );
165	ALLOC0_SC_SIGNAL( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t );
166	ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t );
167	ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t );
168	ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t );
169	ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
170	ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t );
171	ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t );
172
173	/********************************************************
174	* Instanciation
175	********************************************************/
176
177	msg(_("<%s> : Instanciation of _Decod.\n"),name.c_str());
178
179	((_Decod->in_CLOCK)) ((in_CLOCK));
180	((_Decod->in_NRESET)) ((in_NRESET));
181
182	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
183	INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
184	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
185	if (_param->_have_port_context_id)
186	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID ,_param->_nb_context);
187	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS ,_param->_nb_context);
188	// INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT ,_param->_nb_context);
189	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE ,_param->_nb_context);
190	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION ,_param->_nb_context);
191
192	for (uint32_t i=0; i<_param->_nb_context; i++)
193	{
194	if (_param->_have_port_inst_ifetch_ptr)
195	INSTANCE0_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]);
196	// if (_param->_have_port_branch_update_prediction_id)
197	if (_param->_have_port_depth)
198	INSTANCE0_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]);
199	}
200
201	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL ,_param->_nb_inst_decod);
202	INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK ,_param->_nb_inst_decod);
203	if (_param->_have_port_context_id)
204	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
205	if (_param->_have_port_depth)
206	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_DEPTH ,_param->_nb_inst_decod);
207	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE ,_param->_nb_inst_decod);
208	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION ,_param->_nb_inst_decod);
209	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod);
210	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod);
211	#ifdef DEBUG
212	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod);
213	#endif
214	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod);
215	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod);
216	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod);
217	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RA ,_param->_nb_inst_decod);
218	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod);
219	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RB ,_param->_nb_inst_decod);
220	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod);
221	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RC ,_param->_nb_inst_decod);
222	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod);
223	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RD ,_param->_nb_inst_decod);
224	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod);
225	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RE ,_param->_nb_inst_decod);
226	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod);
227	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod);
228	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION ,_param->_nb_inst_decod);
229	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL ,_param->_nb_inst_decod);
230	INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK ,_param->_nb_inst_decod);
231	if (_param->_have_port_context_id)
232	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod);
233	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod);
234	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod);
235	// if (_param->_have_port_branch_update_prediction_id)
236	if (_param->_have_port_depth)
237	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod);
238	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod);
239	// INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod);
240	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod);
241	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod);
242	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod);
243	INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);
244	INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context);
245	INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH_VAL ,_param->_nb_context);
246	for (uint32_t i=0; i<_param->_nb_context; i++)
247	if (_param->_have_port_depth)
248	INSTANCE0_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]);
249	INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_VAL );
250	INSTANCE0_SC_SIGNAL(_Decod, in_CONTEXT_EVENT_ACK );
251	if (_param->_have_port_context_id)
252	INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_CONTEXT_ID );
253	if (_param->_have_port_depth)
254	INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_DEPTH );
255	INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_TYPE );
256	INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT );
257	INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_ADDRESS );
258	INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR );
259
260	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
261
262	Time * _time = new Time();
263
264	/********************************************************
265	* Simulation - Begin
266	********************************************************/
267
268	// Initialisation
269
270	const uint32_t seed = 0;
271	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
272
273	const int32_t percent_transaction_ifetch = 75;
274	const int32_t percent_transaction_decod = 75;
275	const int32_t percent_transaction_predict = 75;
276	const int32_t percent_transaction_event = 75;
277
278	srand(seed);
279
280	SC_START(0);
281	LABEL("Initialisation");
282
283	LABEL("Reset");
284	in_NRESET->write(0);
285	SC_START(5);
286	in_NRESET->write(1);
287
288	LABEL("Loop of Test");
289
290	for (uint32_t i=0; i<_param->_nb_context; i++)
291	in_CONTEXT_DEPTH_VAL [i]->write(1);
292
293	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
294	{
295	LABEL("Iteration %d",iteration);
296
297	Decod_request request [_param->_nb_context];
298
299	uint32_t nb_request = 0;
300
301	uint32_t delay_slot_previous [_param->_nb_context];
302	uint32_t delay_slot_current [_param->_nb_context];
303	uint32_t delay_slot_next [_param->_nb_context];
304
305	for (uint32_t i=0; i<_param->_nb_context; i++)
306	{
307	nb_request += request[i].size();
308	delay_slot_current [i] = false;
309	delay_slot_next [i] = false;
310	}
311
312	while (nb_request > 0)
313	{
314	for (uint32_t i=0; i<_param->_nb_context; i++)
315	{
316	delay_slot_previous [i] = false;
317
318	in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)<percent_transaction_decod);
319
320	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
321	in_IFETCH_VAL [i][j]->write(0);
322
323	if ((rand()%100)<percent_transaction_ifetch)
324	{
325	list<entry_t>::iterator it = request[i].begin();
326
327	if (it!=request [i].end())
328	{
329	uint32_t lsb = it->_address%_param->_nb_inst_fetch[i];
330
331	in_IFETCH_ADDRESS [i]->write(it->_address-lsb);
332	in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE);
333	if (_param->_have_port_inst_ifetch_ptr)
334	in_IFETCH_INST_IFETCH_PTR [i]->write(0);
335	in_IFETCH_EXCEPTION [i]->write(EXCEPTION_IFETCH_NONE);
336
337	// Alignement
338	for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++)
339	{
340	in_IFETCH_VAL [i][j]->write(1);
341	in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction);
342	// in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next);
343	if (it->_type == TYPE_BRANCH)
344	in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state);
345	in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id);
346
347	if ((it->_is_delay_slot) or
348	((++it)==request [i].end()))
349	break;
350	}
351	}
352	}
353	}
354
355	{
356	bool previous_ack = true;
357
358	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
359	{
360	bool ack = previous_ack and ((rand()%100)<percent_transaction_decod);
361	in_DECOD_ACK [i]->write(ack);
362
363	previous_ack = ack;
364
365	in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict);
366	in_PREDICT_CAN_CONTINUE [i]->write(0);
367	}
368	}
369
370	in_CONTEXT_EVENT_ACK->write((rand()%100)<percent_transaction_event);
371
372	SC_START(0);
373
374
375	uint32_t nb_inst_ifetch = 0;
376	for (uint32_t i=0; i<_param->_nb_context; i++)
377	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
378	if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read())
379	{
380	LABEL("IFETCH [%d][%d] : transaction",i,j);
381	nb_inst_ifetch ++;
382	}
383
384	uint32_t nb_inst_decod = 0;
385	uint32_t find_event = false;
386
387	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
388	if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read())
389	{
390	Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0;
391
392	LABEL("DECOD [%d] : transaction",i );
393	LABEL(" * context : %d",context);
394	LABEL(" * instruction : 0x%x",request [context].front()._instruction);
395
396	if (_param->_have_port_depth)
397	TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), request [context].front()._depth );
398	TEST(Ttype_t , out_DECOD_TYPE [i]->read(), request [context].front()._type );
399	TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), request [context].front()._operation );
400	TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), request [context].front()._is_delay_slot);
401	TEST(Tcontrol_t , delay_slot_current [context] , request [context].front()._is_delay_slot);
402	// TEST(Tgeneral_data_t , out_DECOD_ADDRESS_NEXT [i]->read(), request [context].front()._address_next );
403	TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), request [context].front()._has_immediat );
404	if (request [context].front()._has_immediat)
405	TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), request [context].front()._immediat );
406	TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), request [context].front()._read_ra );
407	if (request [context].front()._read_ra)
408	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), request [context].front()._num_reg_ra );
409	TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), request [context].front()._read_rb );
410	if (request [context].front()._read_rb)
411	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), request [context].front()._num_reg_rb );
412	TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), request [context].front()._read_rc );
413	if (request [context].front()._read_rc)
414	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), request [context].front()._num_reg_rc );
415	TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), request [context].front()._write_rd );
416	if (request [context].front()._write_rd)
417	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), request [context].front()._num_reg_rd );
418	TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), request [context].front()._write_re );
419	if (request [context].front()._write_re)
420	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), request [context].front()._num_reg_re );
421	TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), request [context].front()._exception_use);
422
423	if (request [context].front()._type == TYPE_BRANCH)
424	{
425	delay_slot_next [context] = true;
426
427	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), true);
428	TEST(Tcontrol_t, in_PREDICT_ACK[i]->read(), true);
429
430	LABEL("PREDICT [%d] : transaction",i );
431
432	if (_param->_have_port_context_id)
433	TEST(Tcontext_t , out_PREDICT_CONTEXT_ID [i]->read(), context);
434	TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0);
435	TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [i]->read(), request [context].front()._branch_state );
436	// if (_param->_have_port_branch_update_prediction_id)
437	if (_param->_have_port_depth)
438	TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id);
439	TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [i]->read(), request [context].front()._branch_condition );
440	// TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [i]->read(), request [context].front()._branch_stack_write );
441	TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [i]->read(), request [context].front()._branch_direction );
442	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i]->read(), request [context].front()._address );
443	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i]->read(), request [context].front()._branch_address_dest );
444	}
445	else
446	{
447	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), false);
448	}
449
450	TEST(bool, find_event, false); // can continue decod after event
451	if (request [context].front()._context_event_type != EVENT_TYPE_NONE)
452	{
453	find_event = true;
454
455	LABEL("CONTEXT_EVENT : transaction");
456
457	if (_param->_have_port_context_id)
458	TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), context);
459	if (_param->_have_port_depth )
460	TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), request [context].front()._depth );
461	TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), request [context].front()._context_event_type);
462	TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot);
463	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), request [context].front()._address );
464	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), request [context].front()._address_next );
465
466	}
467
468	TEST(bool, delay_slot_previous [context], false); // can't continue
469	delay_slot_previous [context] = delay_slot_current [context];
470	delay_slot_current [context] = delay_slot_next [context];
471	delay_slot_next [context] = false;
472
473	request [context].pop_front();
474	nb_inst_decod ++;
475	nb_request --;
476	}
477
478	TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event);
479	TEST(uint32_t, nb_inst_decod, nb_inst_ifetch);
480
481	SC_START(1);
482	}
483	}
484
485	/********************************************************
486	* Simulation - End
487	********************************************************/
488
489	TEST_OK ("End of Simulation");
490	delete _time;
491
492	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
493
494	delete in_CLOCK;
495	delete in_NRESET;
496
497	delete [] in_IFETCH_VAL ;
498	delete [] out_IFETCH_ACK ;
499	delete [] in_IFETCH_INSTRUCTION ;
500	delete [] in_IFETCH_CONTEXT_ID ;
501	delete [] in_IFETCH_ADDRESS ;
502	// delete [] in_IFETCH_ADDRESS_NEXT ;
503	delete [] in_IFETCH_INST_IFETCH_PTR ;
504	delete [] in_IFETCH_BRANCH_STATE ;
505	delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;
506	delete [] in_IFETCH_EXCEPTION ;
507
508	delete [] out_DECOD_VAL ;
509	delete [] in_DECOD_ACK ;
510	delete [] out_DECOD_CONTEXT_ID ;
511	delete [] out_DECOD_DEPTH ;
512	delete [] out_DECOD_TYPE ;
513	delete [] out_DECOD_OPERATION ;
514	delete [] out_DECOD_NO_EXECUTE ;
515	delete [] out_DECOD_IS_DELAY_SLOT ;
516	#ifdef DEBUG
517	delete [] out_DECOD_ADDRESS ;
518	#endif
519	delete [] out_DECOD_ADDRESS_NEXT ;
520	delete [] out_DECOD_HAS_IMMEDIAT ;
521	delete [] out_DECOD_IMMEDIAT ;
522	delete [] out_DECOD_READ_RA ;
523	delete [] out_DECOD_NUM_REG_RA ;
524	delete [] out_DECOD_READ_RB ;
525	delete [] out_DECOD_NUM_REG_RB ;
526	delete [] out_DECOD_READ_RC ;
527	delete [] out_DECOD_NUM_REG_RC ;
528	delete [] out_DECOD_WRITE_RD ;
529	delete [] out_DECOD_NUM_REG_RD ;
530	delete [] out_DECOD_WRITE_RE ;
531	delete [] out_DECOD_NUM_REG_RE ;
532	delete [] out_DECOD_EXCEPTION_USE ;
533	delete [] out_DECOD_EXCEPTION ;
534
535	delete [] out_PREDICT_VAL ;
536	delete [] in_PREDICT_ACK ;
537	delete [] out_PREDICT_CONTEXT_ID ;
538	delete [] out_PREDICT_MATCH_INST_IFETCH_PTR ;
539	delete [] out_PREDICT_BRANCH_STATE ;
540	delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
541	delete [] out_PREDICT_BRANCH_CONDITION ;
542	//delete [] out_PREDICT_BRANCH_STACK_WRITE ;
543	delete [] out_PREDICT_BRANCH_DIRECTION ;
544	delete [] out_PREDICT_ADDRESS_SRC ;
545	delete [] out_PREDICT_ADDRESS_DEST ;
546	delete [] in_PREDICT_CAN_CONTINUE ;
547
548	delete [] in_CONTEXT_DECOD_ENABLE ;
549	delete [] in_CONTEXT_DEPTH_VAL ;
550	delete [] in_CONTEXT_DEPTH ;
551
552	delete out_CONTEXT_EVENT_VAL ;
553	delete in_CONTEXT_EVENT_ACK ;
554	delete out_CONTEXT_EVENT_CONTEXT_ID ;
555	delete out_CONTEXT_EVENT_DEPTH ;
556	delete out_CONTEXT_EVENT_TYPE ;
557	delete out_CONTEXT_EVENT_IS_DELAY_SLOT ;
558	delete out_CONTEXT_EVENT_ADDRESS ;
559	delete out_CONTEXT_EVENT_ADDRESS_EPCR ;
560	#endif
561
562	delete _Decod;
563	#ifdef STATISTICS
564	delete _parameters_statistics;
565	#endif
566	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp @ 113

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