1 | /* |
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2 | * $Id: test.cpp 113 2009-04-14 18:39:12Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #define NB_ITERATION 1 |
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10 | #define CYCLE_MAX (2048*NB_ITERATION) |
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11 | |
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12 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/test.h" |
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13 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h" |
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14 | #include <list> |
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15 | #include "Common/include/Test.h" |
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16 | #include "Behavioural/include/Allocation.h" |
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17 | |
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18 | void test (string name, |
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19 | morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * _param) |
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20 | { |
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21 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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22 | |
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23 | #ifdef STATISTICS |
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24 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0); |
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25 | #endif |
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26 | |
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27 | Tusage_t _usage = USE_ALL; |
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28 | |
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29 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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30 | // _usage = usage_unset(_usage,USE_VHDL ); |
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31 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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32 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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33 | // _usage = usage_unset(_usage,USE_POSITION ); |
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34 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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35 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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36 | |
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37 | Decod * _Decod = new Decod |
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38 | (name.c_str(), |
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39 | #ifdef STATISTICS |
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40 | _parameters_statistics, |
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41 | #endif |
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42 | _param, |
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43 | _usage); |
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44 | |
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45 | #ifdef SYSTEMC |
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46 | /********************************************************************* |
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47 | * Déclarations des signaux |
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48 | *********************************************************************/ |
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49 | string rename; |
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50 | |
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51 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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52 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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53 | |
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54 | sc_signal<Tcontrol_t > *** in_IFETCH_VAL ;//[nb_context][nb_inst_fetch] |
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55 | sc_signal<Tcontrol_t > *** out_IFETCH_ACK ;//[nb_context][nb_inst_fetch] |
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56 | sc_signal<Tinstruction_t > *** in_IFETCH_INSTRUCTION ;//[nb_context][nb_inst_fetch] |
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57 | sc_signal<Tcontext_t > ** in_IFETCH_CONTEXT_ID ;//[nb_context] |
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58 | sc_signal<Tgeneral_address_t > ** in_IFETCH_ADDRESS ;//[nb_context] |
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59 | //sc_signal<Tgeneral_address_t > ** in_IFETCH_ADDRESS_NEXT ;//[nb_context] |
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60 | sc_signal<Tinst_ifetch_ptr_t > ** in_IFETCH_INST_IFETCH_PTR ;//[nb_context] |
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61 | sc_signal<Tbranch_state_t > ** in_IFETCH_BRANCH_STATE ;//[nb_context] |
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62 | sc_signal<Tprediction_ptr_t > ** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;//[nb_context] |
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63 | sc_signal<Texception_t > ** in_IFETCH_EXCEPTION ;//[nb_context] |
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64 | sc_signal<Tcontrol_t > ** out_DECOD_VAL ;//[nb_inst_decod] |
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65 | sc_signal<Tcontrol_t > ** in_DECOD_ACK ;//[nb_inst_decod] |
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66 | sc_signal<Tcontext_t > ** out_DECOD_CONTEXT_ID ;//[nb_inst_decod] |
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67 | sc_signal<Tdepth_t > ** out_DECOD_DEPTH ;//[nb_inst_decod] |
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68 | sc_signal<Ttype_t > ** out_DECOD_TYPE ;//[nb_inst_decod] |
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69 | sc_signal<Toperation_t > ** out_DECOD_OPERATION ;//[nb_inst_decod] |
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70 | sc_signal<Tcontrol_t > ** out_DECOD_NO_EXECUTE ;//[nb_inst_decod] |
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71 | sc_signal<Tcontrol_t > ** out_DECOD_IS_DELAY_SLOT ;//[nb_inst_decod] |
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72 | sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS ;//[nb_inst_decod] |
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73 | sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS_NEXT ;//[nb_inst_decod] |
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74 | sc_signal<Tcontrol_t > ** out_DECOD_HAS_IMMEDIAT ;//[nb_inst_decod] |
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75 | sc_signal<Tgeneral_data_t > ** out_DECOD_IMMEDIAT ;//[nb_inst_decod] |
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76 | sc_signal<Tcontrol_t > ** out_DECOD_READ_RA ;//[nb_inst_decod] |
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77 | sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RA ;//[nb_inst_decod] |
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78 | sc_signal<Tcontrol_t > ** out_DECOD_READ_RB ;//[nb_inst_decod] |
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79 | sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RB ;//[nb_inst_decod] |
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80 | sc_signal<Tcontrol_t > ** out_DECOD_READ_RC ;//[nb_inst_decod] |
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81 | sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RC ;//[nb_inst_decod] |
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82 | sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RD ;//[nb_inst_decod] |
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83 | sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RD ;//[nb_inst_decod] |
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84 | sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RE ;//[nb_inst_decod] |
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85 | sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RE ;//[nb_inst_decod] |
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86 | sc_signal<Texception_t > ** out_DECOD_EXCEPTION_USE ;//[nb_inst_decod] |
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87 | sc_signal<Texception_t > ** out_DECOD_EXCEPTION ;//[nb_inst_decod] |
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88 | sc_signal<Tcontrol_t > ** out_PREDICT_VAL ;//[nb_inst_decod] |
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89 | sc_signal<Tcontrol_t > ** in_PREDICT_ACK ;//[nb_inst_decod] |
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90 | sc_signal<Tcontext_t > ** out_PREDICT_CONTEXT_ID ;//[nb_inst_decod] |
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91 | sc_signal<Tcontrol_t > ** out_PREDICT_MATCH_INST_IFETCH_PTR ;//[nb_inst_decod] |
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92 | sc_signal<Tbranch_state_t > ** out_PREDICT_BRANCH_STATE ;//[nb_inst_decod] |
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93 | sc_signal<Tprediction_ptr_t > ** out_PREDICT_BRANCH_UPDATE_PREDICTION_ID;//[nb_inst_decod] |
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94 | sc_signal<Tbranch_condition_t> ** out_PREDICT_BRANCH_CONDITION ;//[nb_inst_decod] |
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95 | //sc_signal<Tcontrol_t > ** out_PREDICT_BRANCH_STACK_WRITE ;//[nb_inst_decod] |
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96 | sc_signal<Tcontrol_t > ** out_PREDICT_BRANCH_DIRECTION ;//[nb_inst_decod] |
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97 | sc_signal<Tgeneral_data_t > ** out_PREDICT_ADDRESS_SRC ;//[nb_inst_decod] |
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98 | sc_signal<Tgeneral_data_t > ** out_PREDICT_ADDRESS_DEST ;//[nb_inst_decod] |
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99 | sc_signal<Tcontrol_t > ** in_PREDICT_CAN_CONTINUE ;//[nb_inst_decod] |
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100 | sc_signal<Tcontrol_t > ** in_CONTEXT_DECOD_ENABLE ;//[nb_context] |
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101 | sc_signal<Tcontrol_t > ** in_CONTEXT_DEPTH_VAL ;//[nb_context] |
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102 | sc_signal<Tdepth_t > ** in_CONTEXT_DEPTH ;//[nb_context] |
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103 | sc_signal<Tcontrol_t > * out_CONTEXT_EVENT_VAL ; |
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104 | sc_signal<Tcontrol_t > * in_CONTEXT_EVENT_ACK ; |
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105 | sc_signal<Tcontext_t > * out_CONTEXT_EVENT_CONTEXT_ID ; |
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106 | sc_signal<Tdepth_t > * out_CONTEXT_EVENT_DEPTH ; |
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107 | sc_signal<Tevent_type_t > * out_CONTEXT_EVENT_TYPE ; |
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108 | sc_signal<Tcontrol_t > * out_CONTEXT_EVENT_IS_DELAY_SLOT ; |
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109 | sc_signal<Tgeneral_data_t > * out_CONTEXT_EVENT_ADDRESS ; |
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110 | sc_signal<Tgeneral_data_t > * out_CONTEXT_EVENT_ADDRESS_EPCR ; |
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111 | |
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112 | ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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113 | ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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114 | ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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115 | ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID ," in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context); |
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116 | ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS ," in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context); |
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117 | // ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS_NEXT ," in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context); |
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118 | ALLOC1_SC_SIGNAL( in_IFETCH_INST_IFETCH_PTR ," in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context); |
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119 | ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE ," in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context); |
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120 | ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context); |
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121 | ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION ," in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context); |
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122 | |
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123 | ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod); |
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124 | ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod); |
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125 | ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod); |
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126 | ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod); |
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127 | ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod); |
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128 | ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod); |
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129 | ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod); |
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130 | ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod); |
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131 | #ifdef DEBUG |
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132 | ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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133 | #endif |
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134 | ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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135 | ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod); |
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136 | ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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137 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod); |
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138 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod); |
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139 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod); |
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140 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod); |
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141 | ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod); |
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142 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod); |
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143 | ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod); |
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144 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod); |
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145 | ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod); |
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146 | ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod); |
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147 | ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod); |
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148 | ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod); |
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149 | ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod); |
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150 | ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod); |
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151 | ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod); |
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152 | ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod); |
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153 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod); |
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154 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod); |
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155 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod); |
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156 | // ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod); |
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157 | ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod); |
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158 | ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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159 | ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod); |
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160 | ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod); |
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161 | ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context); |
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162 | ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context); |
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163 | ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context); |
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164 | ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t ); |
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165 | ALLOC0_SC_SIGNAL( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t ); |
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166 | ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t ); |
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167 | ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t ); |
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168 | ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t ); |
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169 | ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t ); |
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170 | ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t ); |
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171 | ALLOC0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t ); |
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172 | |
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173 | /******************************************************** |
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174 | * Instanciation |
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175 | ********************************************************/ |
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176 | |
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177 | msg(_("<%s> : Instanciation of _Decod.\n"),name.c_str()); |
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178 | |
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179 | (*(_Decod->in_CLOCK)) (*(in_CLOCK)); |
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180 | (*(_Decod->in_NRESET)) (*(in_NRESET)); |
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181 | |
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182 | INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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183 | INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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184 | INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]); |
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185 | if (_param->_have_port_context_id) |
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186 | INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID ,_param->_nb_context); |
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187 | INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS ,_param->_nb_context); |
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188 | // INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT ,_param->_nb_context); |
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189 | INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE ,_param->_nb_context); |
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190 | INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION ,_param->_nb_context); |
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191 | |
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192 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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193 | { |
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194 | if (_param->_have_port_inst_ifetch_ptr) |
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195 | INSTANCE0_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]); |
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196 | // if (_param->_have_port_branch_update_prediction_id) |
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197 | if (_param->_have_port_depth) |
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198 | INSTANCE0_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]); |
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199 | } |
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200 | |
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201 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL ,_param->_nb_inst_decod); |
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202 | INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK ,_param->_nb_inst_decod); |
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203 | if (_param->_have_port_context_id) |
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204 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod); |
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205 | if (_param->_have_port_depth) |
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206 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_DEPTH ,_param->_nb_inst_decod); |
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207 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE ,_param->_nb_inst_decod); |
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208 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION ,_param->_nb_inst_decod); |
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209 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod); |
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210 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod); |
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211 | #ifdef DEBUG |
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212 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod); |
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213 | #endif |
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214 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod); |
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215 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod); |
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216 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod); |
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217 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RA ,_param->_nb_inst_decod); |
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218 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod); |
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219 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RB ,_param->_nb_inst_decod); |
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220 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod); |
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221 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RC ,_param->_nb_inst_decod); |
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222 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod); |
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223 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RD ,_param->_nb_inst_decod); |
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224 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod); |
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225 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RE ,_param->_nb_inst_decod); |
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226 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod); |
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227 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod); |
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228 | INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION ,_param->_nb_inst_decod); |
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229 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL ,_param->_nb_inst_decod); |
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230 | INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK ,_param->_nb_inst_decod); |
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231 | if (_param->_have_port_context_id) |
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232 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod); |
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233 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod); |
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234 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod); |
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235 | // if (_param->_have_port_branch_update_prediction_id) |
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236 | if (_param->_have_port_depth) |
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237 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod); |
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238 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod); |
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239 | // INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod); |
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240 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod); |
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241 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod); |
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242 | INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod); |
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243 | INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod); |
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244 | INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context); |
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245 | INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH_VAL ,_param->_nb_context); |
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246 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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247 | if (_param->_have_port_depth) |
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248 | INSTANCE0_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]); |
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249 | INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_VAL ); |
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250 | INSTANCE0_SC_SIGNAL(_Decod, in_CONTEXT_EVENT_ACK ); |
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251 | if (_param->_have_port_context_id) |
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252 | INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_CONTEXT_ID ); |
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253 | if (_param->_have_port_depth) |
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254 | INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_DEPTH ); |
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255 | INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_TYPE ); |
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256 | INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT ); |
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257 | INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_ADDRESS ); |
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258 | INSTANCE0_SC_SIGNAL(_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR ); |
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259 | |
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260 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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261 | |
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262 | Time * _time = new Time(); |
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263 | |
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264 | /******************************************************** |
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265 | * Simulation - Begin |
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266 | ********************************************************/ |
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267 | |
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268 | // Initialisation |
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269 | |
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270 | const uint32_t seed = 0; |
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271 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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272 | |
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273 | const int32_t percent_transaction_ifetch = 75; |
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274 | const int32_t percent_transaction_decod = 75; |
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275 | const int32_t percent_transaction_predict = 75; |
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276 | const int32_t percent_transaction_event = 75; |
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277 | |
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278 | srand(seed); |
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279 | |
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280 | SC_START(0); |
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281 | LABEL("Initialisation"); |
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282 | |
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283 | LABEL("Reset"); |
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284 | in_NRESET->write(0); |
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285 | SC_START(5); |
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286 | in_NRESET->write(1); |
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287 | |
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288 | LABEL("Loop of Test"); |
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289 | |
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290 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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291 | in_CONTEXT_DEPTH_VAL [i]->write(1); |
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292 | |
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293 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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294 | { |
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295 | LABEL("Iteration %d",iteration); |
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296 | |
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297 | Decod_request request [_param->_nb_context]; |
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298 | |
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299 | uint32_t nb_request = 0; |
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300 | |
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301 | uint32_t delay_slot_previous [_param->_nb_context]; |
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302 | uint32_t delay_slot_current [_param->_nb_context]; |
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303 | uint32_t delay_slot_next [_param->_nb_context]; |
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304 | |
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305 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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306 | { |
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307 | nb_request += request[i].size(); |
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308 | delay_slot_current [i] = false; |
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309 | delay_slot_next [i] = false; |
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310 | } |
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311 | |
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312 | while (nb_request > 0) |
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313 | { |
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314 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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315 | { |
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316 | delay_slot_previous [i] = false; |
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317 | |
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318 | in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)<percent_transaction_decod); |
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319 | |
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320 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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321 | in_IFETCH_VAL [i][j]->write(0); |
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322 | |
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323 | if ((rand()%100)<percent_transaction_ifetch) |
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324 | { |
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325 | list<entry_t>::iterator it = request[i].begin(); |
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326 | |
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327 | if (it!=request [i].end()) |
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328 | { |
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329 | uint32_t lsb = it->_address%_param->_nb_inst_fetch[i]; |
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330 | |
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331 | in_IFETCH_ADDRESS [i]->write(it->_address-lsb); |
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332 | in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE); |
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333 | if (_param->_have_port_inst_ifetch_ptr) |
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334 | in_IFETCH_INST_IFETCH_PTR [i]->write(0); |
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335 | in_IFETCH_EXCEPTION [i]->write(EXCEPTION_IFETCH_NONE); |
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336 | |
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337 | // Alignement |
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338 | for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++) |
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339 | { |
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340 | in_IFETCH_VAL [i][j]->write(1); |
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341 | in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction); |
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342 | // in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next); |
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343 | if (it->_type == TYPE_BRANCH) |
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344 | in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state); |
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345 | in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id); |
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346 | |
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347 | if ((it->_is_delay_slot) or |
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348 | ((++it)==request [i].end())) |
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349 | break; |
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350 | } |
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351 | } |
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352 | } |
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353 | } |
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354 | |
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355 | { |
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356 | bool previous_ack = true; |
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357 | |
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358 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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359 | { |
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360 | bool ack = previous_ack and ((rand()%100)<percent_transaction_decod); |
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361 | in_DECOD_ACK [i]->write(ack); |
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362 | |
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363 | previous_ack = ack; |
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364 | |
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365 | in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict); |
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366 | in_PREDICT_CAN_CONTINUE [i]->write(0); |
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367 | } |
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368 | } |
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369 | |
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370 | in_CONTEXT_EVENT_ACK->write((rand()%100)<percent_transaction_event); |
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371 | |
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372 | SC_START(0); |
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373 | |
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374 | |
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375 | uint32_t nb_inst_ifetch = 0; |
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376 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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377 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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378 | if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read()) |
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379 | { |
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380 | LABEL("IFETCH [%d][%d] : transaction",i,j); |
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381 | nb_inst_ifetch ++; |
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382 | } |
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383 | |
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384 | uint32_t nb_inst_decod = 0; |
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385 | uint32_t find_event = false; |
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386 | |
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387 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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388 | if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read()) |
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389 | { |
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390 | Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0; |
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391 | |
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392 | LABEL("DECOD [%d] : transaction",i ); |
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393 | LABEL(" * context : %d",context); |
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394 | LABEL(" * instruction : 0x%x",request [context].front()._instruction); |
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395 | |
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396 | if (_param->_have_port_depth) |
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397 | TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), request [context].front()._depth ); |
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398 | TEST(Ttype_t , out_DECOD_TYPE [i]->read(), request [context].front()._type ); |
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399 | TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), request [context].front()._operation ); |
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400 | TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), request [context].front()._is_delay_slot); |
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401 | TEST(Tcontrol_t , delay_slot_current [context] , request [context].front()._is_delay_slot); |
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402 | // TEST(Tgeneral_data_t , out_DECOD_ADDRESS_NEXT [i]->read(), request [context].front()._address_next ); |
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403 | TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), request [context].front()._has_immediat ); |
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404 | if (request [context].front()._has_immediat) |
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405 | TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), request [context].front()._immediat ); |
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406 | TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), request [context].front()._read_ra ); |
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407 | if (request [context].front()._read_ra) |
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408 | TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), request [context].front()._num_reg_ra ); |
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409 | TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), request [context].front()._read_rb ); |
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410 | if (request [context].front()._read_rb) |
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411 | TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), request [context].front()._num_reg_rb ); |
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412 | TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), request [context].front()._read_rc ); |
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413 | if (request [context].front()._read_rc) |
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414 | TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), request [context].front()._num_reg_rc ); |
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415 | TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), request [context].front()._write_rd ); |
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416 | if (request [context].front()._write_rd) |
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417 | TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), request [context].front()._num_reg_rd ); |
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418 | TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), request [context].front()._write_re ); |
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419 | if (request [context].front()._write_re) |
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420 | TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), request [context].front()._num_reg_re ); |
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421 | TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), request [context].front()._exception_use); |
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422 | |
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423 | if (request [context].front()._type == TYPE_BRANCH) |
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424 | { |
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425 | delay_slot_next [context] = true; |
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426 | |
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427 | TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), true); |
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428 | TEST(Tcontrol_t, in_PREDICT_ACK[i]->read(), true); |
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429 | |
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430 | LABEL("PREDICT [%d] : transaction",i ); |
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431 | |
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432 | if (_param->_have_port_context_id) |
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433 | TEST(Tcontext_t , out_PREDICT_CONTEXT_ID [i]->read(), context); |
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434 | TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0); |
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435 | TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [i]->read(), request [context].front()._branch_state ); |
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436 | // if (_param->_have_port_branch_update_prediction_id) |
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437 | if (_param->_have_port_depth) |
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438 | TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id); |
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439 | TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [i]->read(), request [context].front()._branch_condition ); |
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440 | // TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [i]->read(), request [context].front()._branch_stack_write ); |
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441 | TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [i]->read(), request [context].front()._branch_direction ); |
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442 | TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i]->read(), request [context].front()._address ); |
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443 | TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i]->read(), request [context].front()._branch_address_dest ); |
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444 | } |
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445 | else |
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446 | { |
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447 | TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), false); |
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448 | } |
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449 | |
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450 | TEST(bool, find_event, false); // can continue decod after event |
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451 | if (request [context].front()._context_event_type != EVENT_TYPE_NONE) |
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452 | { |
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453 | find_event = true; |
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454 | |
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455 | LABEL("CONTEXT_EVENT : transaction"); |
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456 | |
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457 | if (_param->_have_port_context_id) |
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458 | TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), context); |
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459 | if (_param->_have_port_depth ) |
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460 | TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), request [context].front()._depth ); |
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461 | TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), request [context].front()._context_event_type); |
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462 | TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot); |
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463 | TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), request [context].front()._address ); |
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464 | TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), request [context].front()._address_next ); |
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465 | |
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466 | } |
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467 | |
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468 | TEST(bool, delay_slot_previous [context], false); // can't continue |
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469 | delay_slot_previous [context] = delay_slot_current [context]; |
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470 | delay_slot_current [context] = delay_slot_next [context]; |
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471 | delay_slot_next [context] = false; |
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472 | |
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473 | request [context].pop_front(); |
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474 | nb_inst_decod ++; |
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475 | nb_request --; |
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476 | } |
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477 | |
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478 | TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event); |
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479 | TEST(uint32_t, nb_inst_decod, nb_inst_ifetch); |
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480 | |
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481 | SC_START(1); |
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482 | } |
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483 | } |
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484 | |
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485 | /******************************************************** |
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486 | * Simulation - End |
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487 | ********************************************************/ |
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488 | |
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489 | TEST_OK ("End of Simulation"); |
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490 | delete _time; |
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491 | |
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492 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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493 | |
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494 | delete in_CLOCK; |
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495 | delete in_NRESET; |
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496 | |
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497 | delete [] in_IFETCH_VAL ; |
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498 | delete [] out_IFETCH_ACK ; |
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499 | delete [] in_IFETCH_INSTRUCTION ; |
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500 | delete [] in_IFETCH_CONTEXT_ID ; |
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501 | delete [] in_IFETCH_ADDRESS ; |
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502 | // delete [] in_IFETCH_ADDRESS_NEXT ; |
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503 | delete [] in_IFETCH_INST_IFETCH_PTR ; |
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504 | delete [] in_IFETCH_BRANCH_STATE ; |
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505 | delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ; |
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506 | delete [] in_IFETCH_EXCEPTION ; |
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507 | |
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508 | delete [] out_DECOD_VAL ; |
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509 | delete [] in_DECOD_ACK ; |
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510 | delete [] out_DECOD_CONTEXT_ID ; |
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511 | delete [] out_DECOD_DEPTH ; |
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512 | delete [] out_DECOD_TYPE ; |
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513 | delete [] out_DECOD_OPERATION ; |
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514 | delete [] out_DECOD_NO_EXECUTE ; |
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515 | delete [] out_DECOD_IS_DELAY_SLOT ; |
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516 | #ifdef DEBUG |
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517 | delete [] out_DECOD_ADDRESS ; |
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518 | #endif |
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519 | delete [] out_DECOD_ADDRESS_NEXT ; |
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520 | delete [] out_DECOD_HAS_IMMEDIAT ; |
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521 | delete [] out_DECOD_IMMEDIAT ; |
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522 | delete [] out_DECOD_READ_RA ; |
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523 | delete [] out_DECOD_NUM_REG_RA ; |
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524 | delete [] out_DECOD_READ_RB ; |
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525 | delete [] out_DECOD_NUM_REG_RB ; |
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526 | delete [] out_DECOD_READ_RC ; |
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527 | delete [] out_DECOD_NUM_REG_RC ; |
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528 | delete [] out_DECOD_WRITE_RD ; |
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529 | delete [] out_DECOD_NUM_REG_RD ; |
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530 | delete [] out_DECOD_WRITE_RE ; |
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531 | delete [] out_DECOD_NUM_REG_RE ; |
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532 | delete [] out_DECOD_EXCEPTION_USE ; |
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533 | delete [] out_DECOD_EXCEPTION ; |
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534 | |
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535 | delete [] out_PREDICT_VAL ; |
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536 | delete [] in_PREDICT_ACK ; |
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537 | delete [] out_PREDICT_CONTEXT_ID ; |
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538 | delete [] out_PREDICT_MATCH_INST_IFETCH_PTR ; |
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539 | delete [] out_PREDICT_BRANCH_STATE ; |
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540 | delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID; |
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541 | delete [] out_PREDICT_BRANCH_CONDITION ; |
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542 | //delete [] out_PREDICT_BRANCH_STACK_WRITE ; |
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543 | delete [] out_PREDICT_BRANCH_DIRECTION ; |
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544 | delete [] out_PREDICT_ADDRESS_SRC ; |
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545 | delete [] out_PREDICT_ADDRESS_DEST ; |
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546 | delete [] in_PREDICT_CAN_CONTINUE ; |
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547 | |
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548 | delete [] in_CONTEXT_DECOD_ENABLE ; |
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549 | delete [] in_CONTEXT_DEPTH_VAL ; |
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550 | delete [] in_CONTEXT_DEPTH ; |
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551 | |
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552 | delete out_CONTEXT_EVENT_VAL ; |
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553 | delete in_CONTEXT_EVENT_ACK ; |
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554 | delete out_CONTEXT_EVENT_CONTEXT_ID ; |
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555 | delete out_CONTEXT_EVENT_DEPTH ; |
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556 | delete out_CONTEXT_EVENT_TYPE ; |
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557 | delete out_CONTEXT_EVENT_IS_DELAY_SLOT ; |
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558 | delete out_CONTEXT_EVENT_ADDRESS ; |
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559 | delete out_CONTEXT_EVENT_ADDRESS_EPCR ; |
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560 | #endif |
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561 | |
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562 | delete _Decod; |
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563 | #ifdef STATISTICS |
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564 | delete _parameters_statistics; |
---|
565 | #endif |
---|
566 | } |
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