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test.cpp @ 78

Last change on this file since 78 was 78, checked in by rosiere, 16 years ago

Add :

Execute_loop (must be test systemC)
Prediction
- Direction : predifined scheme
- Branch Target Buffer
iFetch_unit
- ifetch_queue
- pc management
Decod_unit
- coming soon : support for custom operation
Rename_unit
- RAT
- Free_list
- Dependence RAW check
- Load store unit pointer
New Environnement (hierarchy_memory will remove in a next version)

Modif :

Manage Custom Operation
All component in execute_loop to use the new statistics management

Not Finish :

Return Address Stack
Environnement

File size: 68.2 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/test.h"
10	#include <list>
11	#include "Common/include/Test.h"
12	#include "Behavioural/include/Allocation.h"
13
14	#define NB_ITERATION 1
15	#define CYCLE_MAX (2048*NB_ITERATION)
16
17	#define LABEL(str...) \
18	{ \
19	msg (_("{%d} "),static_cast<uint32_t>(sc_simulation_time())); \
20	msg (str); \
21	msg (_("\n")); \
22	} while(0)
23
24	#define SC_START(cycle_offset) \
25	do \
26	{ \
27	/cout << "SC_START (begin)" << endl;/ \
28	\
29	uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \
30	if (cycle_offset != 0) \
31	{ \
32	cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \
33	} \
34	\
35	if (cycle_current > CYCLE_MAX) \
36	{ \
37	TEST_KO("Maximal cycles Reached"); \
38	} \
39	\
40	sc_start(cycle_offset); \
41	\
42	/cout << "SC_START (end )" << endl;/ \
43	} while(0)
44
45	class entry_t
46	{
47	// public : Tcontrol_t _val ;
48	public : Tinstruction_t _instruction ;
49	// public : Tcontext_t _context_id ;
50	public : Tgeneral_address_t _address_previous ;
51	public : Tgeneral_address_t _address ;
52	public : Tgeneral_address_t _address_next ;
53	public : Tbranch_state_t _branch_state ;
54	public : Tprediction_ptr_t _branch_update_prediction_id;
55	public : Tbranch_condition_t _branch_condition ;
56	// public : Tcontrol_t _branch_stack_write ;
57	public : Tcontrol_t _branch_direction ;
58	public : Tgeneral_address_t _branch_address_dest ;
59	public : Tdepth_t _depth ;
60	public : Ttype_t _type ;
61	public : Toperation_t _operation ;
62	public : Tcontrol_t _is_delay_slot ;
63	public : Tcontrol_t _has_immediat ;
64	public : Tgeneral_data_t _immediat ;
65	public : Tcontrol_t _read_ra ;
66	public : Tgeneral_address_t _num_reg_ra ;
67	public : Tcontrol_t _read_rb ;
68	public : Tgeneral_address_t _num_reg_rb ;
69	public : Tcontrol_t _read_rc ;
70	public : Tspecial_address_t _num_reg_rc ;
71	public : Tcontrol_t _write_rd ;
72	public : Tgeneral_address_t _num_reg_rd ;
73	public : Tcontrol_t _write_re ;
74	public : Tspecial_address_t _num_reg_re ;
75	public : Texception_t _exception_use ;
76	public : Tevent_type_t _context_event_type ;
77
78	public : entry_t (
79	// Tcontrol_t val ,
80	Tinstruction_t instruction ,
81	// Tcontext_t context_id ,
82	Tgeneral_address_t address_previous ,
83	Tgeneral_address_t address ,
84	Tgeneral_address_t address_next ,
85	Tbranch_state_t branch_state ,
86	Tprediction_ptr_t branch_update_prediction_id,
87	Tbranch_condition_t branch_condition ,
88	// Tcontrol_t branch_stack_write ,
89	Tcontrol_t branch_direction ,
90	Tgeneral_address_t branch_address_dest ,
91	Tdepth_t depth ,
92	Ttype_t type ,
93	Toperation_t operation ,
94	Tcontrol_t is_delay_slot ,
95	Tcontrol_t has_immediat ,
96	Tgeneral_data_t immediat ,
97	Tcontrol_t read_ra ,
98	Tgeneral_address_t num_reg_ra ,
99	Tcontrol_t read_rb ,
100	Tgeneral_address_t num_reg_rb ,
101	Tcontrol_t read_rc ,
102	Tspecial_address_t num_reg_rc ,
103	Tcontrol_t write_rd ,
104	Tgeneral_address_t num_reg_rd ,
105	Tcontrol_t write_re ,
106	Tspecial_address_t num_reg_re ,
107	Texception_t exception_use ,
108	Tevent_type_t context_event_type )
109	{
110	// _val = val ;
111	_instruction = instruction ;
112	// _context_id = context_id ;
113	_address_previous = address_previous ;
114	_address = address ;
115	_address_next = address_next ;
116	_branch_state = branch_state ;
117	_branch_update_prediction_id = branch_update_prediction_id;
118	_branch_condition = branch_condition ;
119	// _branch_stack_write = branch_stack_write ;
120	_branch_direction = branch_direction ;
121	_branch_address_dest = branch_address_dest ;
122	_depth = depth ;
123	_type = type ;
124	_operation = operation ;
125	_is_delay_slot = is_delay_slot ;
126	_has_immediat = has_immediat ;
127	_immediat = immediat ;
128	_read_ra = read_ra ;
129	_num_reg_ra = num_reg_ra ;
130	_read_rb = read_rb ;
131	_num_reg_rb = num_reg_rb ;
132	_read_rc = read_rc ;
133	_num_reg_rc = num_reg_rc ;
134	_write_rd = write_rd ;
135	_num_reg_rd = num_reg_rd ;
136	_write_re = write_re ;
137	_num_reg_re = num_reg_re ;
138	_exception_use = exception_use ;
139	_context_event_type = context_event_type ;
140	}
141	};
142
143
144	void test (string name,
145	morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * _param)
146	{
147	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
148
149	#ifdef STATISTICS
150	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
151	#endif
152
153	Decod * _Decod = new Decod (name.c_str(),
154	#ifdef STATISTICS
155	_parameters_statistics,
156	#endif
157	_param);
158
159	#ifdef SYSTEMC
160	/*********************************************************************
161	* Déclarations des signaux
162	*********************************************************************/
163	string rename;
164
165	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
166	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
167
168	ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
169	ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
170	ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
171	ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID ," in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
172	ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS ," in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context);
173	// ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS_NEXT ," in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context);
174	ALLOC1_SC_SIGNAL( in_IFETCH_INST_IFETCH_PTR ," in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context);
175	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE ," in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context);
176	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context);
177	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
178	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
179	ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
180	ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
181	ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod);
182	ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod);
183	ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod);
184	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod);
185	ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod);
186	ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod);
187	ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod);
188	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod);
189	ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod);
190	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod);
191	ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod);
192	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod);
193	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod);
194	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod);
195	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod);
196	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod);
197	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod);
198	ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
199	ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
200	ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
201	ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod);
202	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod);
203	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod);
204	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
205	// ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod);
206	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod);
207	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod);
208	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod);
209	// ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);
210	ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context);
211	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context);
212	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t );
213	ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t );
214	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t );
215	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t );
216	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
217	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t );
218	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t );
219
220	/********************************************************
221	* Instanciation
222	********************************************************/
223
224	msg(_("<%s> : Instanciation of _Decod.\n"),name.c_str());
225
226	((_Decod->in_CLOCK)) ((in_CLOCK));
227	((_Decod->in_NRESET)) ((in_NRESET));
228
229	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
230	INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
231	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[alloc_signal_it1]);
232	if (_param->_have_port_context_id)
233	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID ,_param->_nb_context);
234	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS ,_param->_nb_context);
235	// INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT ,_param->_nb_context);
236	if (_param->_have_port_inst_ifetch_ptr)
237	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context);
238	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE ,_param->_nb_context);
239	if (_param->_have_port_branch_update_prediction_id)
240	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context);
241	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL ,_param->_nb_inst_decod);
242	INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK ,_param->_nb_inst_decod);
243	if (_param->_have_port_context_id)
244	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
245	if (_param->_have_port_depth)
246	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_DEPTH ,_param->_nb_inst_decod);
247	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE ,_param->_nb_inst_decod);
248	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION ,_param->_nb_inst_decod);
249	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod);
250	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod);
251	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod);
252	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod);
253	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RA ,_param->_nb_inst_decod);
254	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod);
255	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RB ,_param->_nb_inst_decod);
256	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod);
257	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RC ,_param->_nb_inst_decod);
258	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod);
259	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RD ,_param->_nb_inst_decod);
260	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod);
261	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RE ,_param->_nb_inst_decod);
262	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod);
263	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod);
264	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL ,_param->_nb_inst_decod);
265	INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK ,_param->_nb_inst_decod);
266	if (_param->_have_port_context_id)
267	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod);
268	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod);
269	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod);
270	if (_param->_have_port_branch_update_prediction_id)
271	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod);
272	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod);
273	// INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod);
274	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod);
275	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod);
276	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod);
277	// INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);
278	INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context);
279	if (_param->_have_port_depth)
280	INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH ,_param->_nb_context);
281	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL );
282	INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK );
283	if (_param->_have_port_context_id)
284	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID );
285	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE );
286	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT );
287	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS );
288	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR );
289
290	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
291
292	Time * _time = new Time();
293
294	/********************************************************
295	* Simulation - Begin
296	********************************************************/
297
298	// Initialisation
299
300	const uint32_t seed = 0;
301	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
302
303	const int32_t percent_transaction_ifetch = 75;
304	const int32_t percent_transaction_decod = 75;
305	const int32_t percent_transaction_predict = 75;
306	const int32_t percent_transaction_event = 75;
307
308	srand(seed);
309
310	SC_START(0);
311	LABEL("Initialisation");
312
313	LABEL("Reset");
314	in_NRESET->write(0);
315	SC_START(5);
316	in_NRESET->write(1);
317
318	LABEL("Loop of Test");
319
320	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
321	{
322	LABEL("Iteration %d",iteration);
323
324	list<entry_t> request [_param->_nb_context];
325
326	uint32_t w;
327	uint32_t x = 0xfc;
328	uint32_t y = 0x100;
329	uint32_t z = 0x104;
330
331	uint32_t delay_slot_previous [_param->_nb_context];
332	uint32_t delay_slot_current [_param->_nb_context];
333	uint32_t delay_slot_next [_param->_nb_context];
334
335	#define SEQ do {x=y; y=z; z+=4;} while(0);
336	#define JMP(j) do {x=y; y=z; z =j;} while(0);
337
338	// ===== l.add r15, r4 , r8
339	request [0].push_back (entry_t(
340	//instruction,address_previous,address,address_next
341	0xe1e44000,x,y,z,
342	//branch_state,branch_update_prediction_id,branch_condition,branch_stack_write,branch_direction, branch_address_dest
343	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0,0x0,
344	//depth,type,operation,is_delay_slot
345	0,TYPE_ALU,OPERATION_ALU_L_ADD,false,
346	//has_immediat,immediat,read_ra,reg_ra,read_rb,reg_rb,read_rc,reg_rc,write_rd,reg_rd,write_re,reg_re
347	0,0x00000000,1, 4,1, 8,0,0 ,1,15,1,SPR_LOGIC_SR_CY_OV,
348	//exception_use,context_event_type
349	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
350	SEQ;
351
352	// ===== l.addc r15, r4 , r31
353	request [0].push_back (entry_t(
354	0xe1e4f801,x,y,z,
355	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0,0x0,
356	0,TYPE_ALU,OPERATION_ALU_L_ADD,false,
357	0,0x00000000,1, 4,1,31,1,SPR_LOGIC_SR_CY_OV,1,15,1,SPR_LOGIC_SR_CY_OV,
358	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
359	SEQ;
360
361	// ===== l.addi r7 , r12, -1
362	request [0].push_back (entry_t(
363	0x9cecffff,x,y,z,
364	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
365	0,TYPE_ALU,OPERATION_ALU_L_ADD,false,
366	1,0xffffffff,1,12,0, 0,0,0 ,1,7 ,1,SPR_LOGIC_SR_CY_OV,
367	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
368	SEQ;
369
370	// ===== l.addi r8 , r17, 0
371	request [0].push_back (entry_t(
372	0x9d110000,x,y,z,
373	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
374	0,TYPE_ALU,OPERATION_ALU_L_ADD,false,
375	1,0x00000000,1,17,0, 0,0,0 ,1,8 ,1,SPR_LOGIC_SR_CY_OV,
376	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
377	SEQ;
378
379	// ===== l.addi r21, r7 , 1981
380	request [0].push_back (entry_t(
381	0x9ea707bd,x,y,z,
382	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
383	0,TYPE_ALU,OPERATION_ALU_L_ADD,false,
384	1,0x000007bd,1, 7,0, 0,0,0 ,1,21,1,SPR_LOGIC_SR_CY_OV,
385	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
386	SEQ;
387
388	// ===== l.addic r7 , r12, -1
389	request [0].push_back (entry_t(
390	0xa0ecffff,x,y,z,
391	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
392	0,TYPE_ALU,OPERATION_ALU_L_ADD,false,
393	1,0xffffffff,1,12,0, 0,1,SPR_LOGIC_SR_CY_OV,1,7 ,1,SPR_LOGIC_SR_CY_OV,
394	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
395	SEQ;
396
397	// ===== l.addic r8 , r17, 0
398	request [0].push_back (entry_t(
399	0xa1110000,x,y,z,
400	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
401	0,TYPE_ALU,OPERATION_ALU_L_ADD,false,
402	1,0x00000000,1,17,0, 0,1,SPR_LOGIC_SR_CY_OV,1,8 ,1,SPR_LOGIC_SR_CY_OV,
403	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
404	SEQ;
405
406	// ===== l.addic r21, r7 , 1981
407	request [0].push_back (entry_t(
408	0xa2a707bd,x,y,z,
409	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
410	0,TYPE_ALU,OPERATION_ALU_L_ADD,false,
411	1,0x000007bd,1, 7,0, 0,1,SPR_LOGIC_SR_CY_OV,1,21,1,SPR_LOGIC_SR_CY_OV,
412	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
413	SEQ;
414
415	// ===== l.and r24, r0 , r14
416	request [0].push_back (entry_t(
417	0xe3007003,x,y,z,
418	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
419	0,TYPE_ALU,OPERATION_ALU_L_AND,false,
420	0,0x0 ,1, 0,1,14,0,0 ,1,24,0,0 ,
421	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
422	SEQ;
423
424	// ===== l.andi r24, r4 , 1981
425	request [0].push_back (entry_t(
426	0xa70407bd,x,y,z,
427	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
428	0,TYPE_ALU,OPERATION_ALU_L_AND,false,
429	1,0x000007bd,1, 4,0,0 ,0,0 ,1,24,0,0 ,
430	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
431	SEQ;
432
433	// ===== l.bf 11
434	w = y+(11<<2);
435	request [0].push_back (entry_t(
436	0x1000000b,x,y,z,
437	BRANCH_STATE_NONE,0,BRANCH_CONDITION_FLAG_SET,0, w,
438	0,TYPE_BRANCH,OPERATION_BRANCH_L_TEST_F,false,
439	1,w,0, 0,0,0 ,1,SPR_LOGIC_SR_F ,0,0 ,0,0 ,
440	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
441	JMP(w);
442
443	// ===== l.cmov r30, r10, r20
444	request [0].push_back (entry_t(
445	0xe3caa00e,x,y,z,
446	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
447	0,TYPE_MOVE,OPERATION_MOVE_L_CMOV,true,
448	0,0x0,1,10,1,20,1,SPR_LOGIC_SR_F ,1,30,0,0 ,
449	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
450	SEQ;
451
452	// ===== l.div r30,r10,r20
453	request [0].push_back (entry_t(
454	0xe3caa309,x,y,z,
455	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
456	0,TYPE_MUL_DIV,OPERATION_MUL_DIV_L_DIV,false,
457	0,0x0,1,10,1,20,0,0 ,1,30,1,SPR_LOGIC_SR_CY_OV,
458	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
459	SEQ;
460
461	// ===== l.bf -9
462	w = y+(-9<<2);
463	request [0].push_back (entry_t(
464	0x13fffff7,x,y,z,
465	BRANCH_STATE_NONE,0,BRANCH_CONDITION_FLAG_SET,1, w,
466	0,TYPE_BRANCH,OPERATION_BRANCH_L_TEST_F,false,
467	1,w,0, 0,0,0 ,1,SPR_LOGIC_SR_F ,0,0 ,0,0 ,
468	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
469	JMP(w);
470
471	// ===== l.divu r30,r10,r20
472	request [0].push_back (entry_t(
473	0xe3caa30a,x,y,z,
474	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
475	0,TYPE_MUL_DIV,OPERATION_MUL_DIV_L_DIVU,true,
476	0,0x0,1,10,1,20,0,0 ,1,30,1,SPR_LOGIC_SR_CY_OV,
477	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
478	SEQ;
479
480	// ===== l.extbs r30,r10
481	request [0].push_back (entry_t(
482	0xe3ca004c,x,y,z,
483	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
484	0,TYPE_EXTEND,OPERATION_EXTEND_L_EXTEND_S,false,
485	1,8 ,1,10,0,0 ,0,0 ,1,30,0,0 ,
486	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
487	SEQ;
488
489	// ===== l.bnf 11
490	w = y+(11<<2);
491	request [0].push_back (entry_t(
492	0x0c00000b,x,y,z,
493	BRANCH_STATE_NONE,0,BRANCH_CONDITION_FLAG_UNSET,0, w,
494	0,TYPE_BRANCH,OPERATION_BRANCH_L_TEST_NF,false,
495	1,w,0, 0,0,0 ,1,SPR_LOGIC_SR_F ,0,0 ,0,0 ,
496	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
497	JMP(w);
498
499	// ===== l.extbz r30,r10
500	request [0].push_back (entry_t(
501	0xe3ca00cc,x,y,z,
502	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
503	0,TYPE_EXTEND,OPERATION_EXTEND_L_EXTEND_Z,true ,
504	1,8 ,1,10,0,0 ,0,0 ,1,30,0,0 ,
505	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
506	SEQ;
507
508	// ===== l.exths r30,r10
509	request [0].push_back (entry_t(
510	0xe3ca000c,x,y,z,
511	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
512	0,TYPE_EXTEND,OPERATION_EXTEND_L_EXTEND_S,false,
513	1,16 ,1,10,0,0 ,0,0 ,1,30,0,0 ,
514	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
515	SEQ;
516
517	// ===== l.bnf -9
518	w = y+(-9<<2);
519	request [0].push_back (entry_t(
520	0x0ffffff7,x,y,z,
521	BRANCH_STATE_NONE,0,BRANCH_CONDITION_FLAG_UNSET,1, w,
522	0,TYPE_BRANCH,OPERATION_BRANCH_L_TEST_NF,false,
523	1,w,0, 0,0,0 ,1,SPR_LOGIC_SR_F ,0,0 ,0,0 ,
524	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
525	JMP(w);
526
527	// ===== l.exthz r30,r10
528	request [0].push_back (entry_t(
529	0xe3ca008c,x,y,z,
530	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
531	0,TYPE_EXTEND,OPERATION_EXTEND_L_EXTEND_Z,true ,
532	1,16 ,1,10,0,0 ,0,0 ,1,30,0,0 ,
533	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
534	SEQ;
535
536	// ===== l.extws r30,r10
537	request [0].push_back (entry_t(
538	0xe3ca000d,x,y,z,
539	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
540	0,TYPE_EXTEND,OPERATION_EXTEND_L_EXTEND_S,false,
541	1,32 ,1,10,0,0 ,0,0 ,1,30,0,0 ,
542	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
543	SEQ;
544
545	// ===== l.extwz r30,r10
546	request [0].push_back (entry_t(
547	0xe3ca004d,x,y,z,
548	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
549	0,TYPE_EXTEND,OPERATION_EXTEND_L_EXTEND_Z,false,
550	1,32 ,1,10,0,0 ,0,0 ,1,30,0,0 ,
551	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
552	SEQ;
553
554	// ===== l.csync
555	request [0].push_back (entry_t(
556	0x23000000,x,y,z,
557	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
558	0,TYPE_SPECIAL,OPERATION_SPECIAL_L_CSYNC,false,
559	0,0 ,0,0 ,0,0 ,0,0 ,0,0 ,0,0 ,
560	EXCEPTION_USE_NONE,EVENT_TYPE_CSYNC));
561	SEQ;
562
563	// ===== l.ff1 r30,r10
564	request [0].push_back (entry_t(
565	0xe3ca000f,x,y,z,
566	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
567	0,TYPE_FIND,OPERATION_FIND_L_FF1,false,
568	0,0 ,1,10,0,0 ,0,0 ,1,30,0,0 ,
569	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
570	SEQ;
571
572	// ===== l.fl1 r30,r10
573	request [0].push_back (entry_t(
574	0xe3ca010f,x,y,z,
575	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
576	0,TYPE_FIND,OPERATION_FIND_L_FL1,false,
577	0,0 ,1,10,0,0 ,0,0 ,1,30,0,0 ,
578	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
579	SEQ;
580
581	// ===== l.j 1018
582	w = y+(1018<<2);
583	request [0].push_back (entry_t(
584	0x000003fa,x,y,z,
585	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,1, w,
586	0,TYPE_BRANCH,OPERATION_BRANCH_NONE,false,
587	0,0,0, 0,0,0 ,0,0 ,0,0 ,0,0 ,
588	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
589	JMP(w);
590
591	// ===== l.lbs r30,0x3fa(r10)
592	request [0].push_back (entry_t(
593	0x93ca03fa,x,y,z,
594	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
595	0,TYPE_MEMORY,OPERATION_MEMORY_LOAD_8_S,true,
596	1,0x3fa,1,10,0,0 ,0,0,1,30,0,0,
597	EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT,EVENT_TYPE_NONE));
598	SEQ;
599
600	// ===== l.lbz r30,0x3fa(r10)
601	request [0].push_back (entry_t(
602	0x8fca03fa,x,y,z,
603	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
604	0,TYPE_MEMORY,OPERATION_MEMORY_LOAD_8_Z,false,
605	1,0x3fa,1,10,0,0 ,0,0,1,30,0,0,
606	EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT,EVENT_TYPE_NONE));
607	SEQ;
608
609	// ===== l.j -1018
610	w = y+(-1018<<2);
611	request [0].push_back (entry_t(
612	0x03fffc06,x,y,z,
613	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,1, w,
614	0,TYPE_BRANCH,OPERATION_BRANCH_NONE,false,
615	0,0,0, 0,0,0 ,0,0 ,0,0 ,0,0 ,
616	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
617	JMP(w);
618
619	// ===== l.lhs r30,0x3fa(r10)
620	request [0].push_back (entry_t(
621	0x9bca03fa,x,y,z,
622	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
623	0,TYPE_MEMORY,OPERATION_MEMORY_LOAD_16_S,true,
624	1,0x3fa,1,10,0,0 ,0,0,1,30,0,0,
625	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
626	SEQ;
627
628	// ===== l.lhz r30,0x3fa(r10)
629	request [0].push_back (entry_t(
630	0x97ca03fa,x,y,z,
631	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
632	0,TYPE_MEMORY,OPERATION_MEMORY_LOAD_16_Z,false,
633	1,0x3fa,1,10,0,0 ,0,0,1,30,0,0,
634	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
635	SEQ;
636
637	// ===== l.jal 1018
638	w = y+(1018<<2);
639	request [0].push_back (entry_t(
640	0x040003fa,x,y,z,
641	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITH_WRITE_STACK,1, w,
642	0,TYPE_BRANCH,OPERATION_BRANCH_L_JALR,false,
643	1,z+4,0, 0,0,0 ,0,0 ,1,9 ,0,0 ,
644	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
645	JMP(w);
646
647	// ===== l.lws r30,0x3fa(r10)
648	request [0].push_back (entry_t(
649	0x8bca03fa,x,y,z,
650	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
651	0,TYPE_MEMORY,OPERATION_MEMORY_LOAD_32_S,true,
652	1,0x3fa,1,10,0,0 ,0,0,1,30,0,0,
653	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
654	SEQ;
655
656	// ===== l.lwz r30,0x3fa(r10)
657	request [0].push_back (entry_t(
658	0x87ca03fa,x,y,z,
659	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
660	0,TYPE_MEMORY,OPERATION_MEMORY_LOAD_32_Z,false,
661	1,0x3fa,1,10,0,0 ,0,0,1,30,0,0,
662	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
663	SEQ;
664
665	// ===== l.jal -1018
666	w = y+(-1018<<2);
667	request [0].push_back (entry_t(
668	0x07fffc06,x,y,z,
669	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITH_WRITE_STACK,1, w,
670	0,TYPE_BRANCH,OPERATION_BRANCH_L_JALR,false,
671	1,z+4,0, 0,0,0 ,0,0 ,1,9 ,0,0 ,
672	EXCEPTION_USE_NONE ,EVENT_TYPE_NONE));
673	JMP(w);
674
675	// ===== l.ld r30,1018(r10)
676	request [0].push_back (entry_t(
677	0x83ca03fa,x,y,z,
678	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
679	0,TYPE_MEMORY,OPERATION_MEMORY_LOAD_64_S,true,
680	1,1018,1,10,0,0 ,0,0,1,30,0,0,
681	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
682	SEQ;
683
684	// ===== l.ld r30,-1018(r10)
685	request [0].push_back (entry_t(
686	0x83cafc06,x,y,z,
687	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
688	0,TYPE_MEMORY,OPERATION_MEMORY_LOAD_64_S,false,
689	1,static_cast<Tgeneral_data_t>(-1018),1,10,0,0 ,0,0,1,30,0,0,
690	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
691	SEQ;
692
693	// ===== l.jalr r20
694	request [0].push_back (entry_t(
695	0x4800a000,x,y,z,
696	BRANCH_STATE_NONE,0,BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK,1, z, // branch_address_dest can be determined if BRANCH_STATE != NONE (also : previous prediction)
697	0,TYPE_BRANCH,OPERATION_BRANCH_L_JALR,false,
698	0,0 ,0,0 ,1,20,0,0,1,9 ,0,0,
699	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
700	SEQ;
701
702	// ===== l.mac r10,r20
703	request [0].push_back (entry_t(
704	0xc40aa001,x,y,z,
705	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
706	0,TYPE_SPECIAL,OPERATION_SPECIAL_L_MAC,true,
707	0,0,1,10,1,20,0,0,0,0,0,0,
708	EXCEPTION_USE_NONE,EVENT_TYPE_SPR_ACCESS));
709	SEQ;
710
711	// ===== l.maci r10,1018
712	request [0].push_back (entry_t(
713	0x4c0a03fa,x,y,z,
714	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
715	0,TYPE_SPECIAL,OPERATION_SPECIAL_L_MAC,false,
716	1,1018,1,10,0,0,0,0,0,0,0,0,
717	EXCEPTION_USE_NONE,EVENT_TYPE_SPR_ACCESS));
718	SEQ;
719
720	// ===== l.maci r10,-1018
721	request [0].push_back (entry_t(
722	0x4fea0406,x,y,z,
723	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
724	0,TYPE_SPECIAL,OPERATION_SPECIAL_L_MAC,false,
725	1,static_cast<Tgeneral_data_t>(-1018),1,10,0,0,0,0,0,0,0,0,
726	EXCEPTION_USE_NONE,EVENT_TYPE_SPR_ACCESS));
727	SEQ;
728
729	// ===== l.jr r10
730	request [0].push_back (entry_t(
731	0x44005000,x,y,z,
732	BRANCH_STATE_NONE,0,BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK,1, z,
733	0,TYPE_BRANCH,OPERATION_BRANCH_L_JALR,false,
734	0,0 ,0, 0,1,10,0,0,0,0 ,0,0,
735	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
736	SEQ;
737
738	// ===== l.macrc r30
739	request [0].push_back (entry_t(
740	0x1bc10000,x,y,z,
741	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
742	0,TYPE_SPECIAL,OPERATION_SPECIAL_L_MACRC,true,
743	0,0,0, 0,0, 0,0,0,1,30,0,0,
744	EXCEPTION_USE_NONE,EVENT_TYPE_SPR_ACCESS));
745	SEQ;
746
747	// ===== l.mfspr r30,r10,1018
748	request [0].push_back (entry_t(
749	0xb7ca03fa,x,y,z,
750	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
751	0,TYPE_SPECIAL,OPERATION_SPECIAL_L_MFSPR,false,
752	1,1018,1,10,0, 0,0,0,1,30,0,0,
753	EXCEPTION_USE_NONE,EVENT_TYPE_SPR_ACCESS));
754	SEQ;
755
756	// ===== l.mfspr r30,r10,-1018
757	request [0].push_back (entry_t(
758	0xb7cafc06,x,y,z,
759	BRANCH_STATE_NONE,0,BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK,0, 0x0,
760	0,TYPE_SPECIAL,OPERATION_SPECIAL_L_MFSPR,false,
761	1,0xfc06,1,10,0, 0,0,0,1,30,0,0,
762	EXCEPTION_USE_NONE,EVENT_TYPE_SPR_ACCESS));
763	SEQ;
764
765	// ===== l.jr r9
766	request [0].push_back (entry_t(
767	0x44004800,x,y,z,
768	BRANCH_STATE_NONE,0,BRANCH_CONDITION_READ_STACK,1, z,
769	0,TYPE_BRANCH,OPERATION_BRANCH_L_JALR,false,
770	0,0 ,0, 0,1,9,0,0,0,0 ,0,0,
771	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
772	SEQ;
773
774	// ===== l.movhi r30,0x3fa
775	request [0].push_back (entry_t(
776	0x1bc003fa,x,y,z,
777	0,0,0,0,0,0,
778	TYPE_MOVE,OPERATION_MOVE_L_MOVHI,true,
779	1,0x3fa,0,0, 0,0, 0,0, 1,30, 0,0,
780	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
781	SEQ;
782
783	// ===== l.movhi r30,0xfc06
784	request [0].push_back (entry_t(
785	0x1bc0fc06,x,y,z,
786	0,0,0,0,0,0,
787	TYPE_MOVE,OPERATION_MOVE_L_MOVHI,false,
788	1,0xfc06,0,0, 0,0, 0,0, 1,30, 0,0,
789	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
790	SEQ;
791
792	// ===== l.msb r10,r20
793	request [0].push_back (entry_t(
794	0xc40aa002,x,y,z,
795	0,0,0,0,0,0,
796	TYPE_SPECIAL,OPERATION_SPECIAL_L_MSB,false,
797	0,0, 1,10, 1,20, 0,0, 0,0, 0,0,
798	EXCEPTION_USE_NONE,EVENT_TYPE_SPR_ACCESS));
799	SEQ;
800
801	// ===== l.msync
802	request [0].push_back (entry_t(
803	0x22000000,x,y,z,
804	0,0,0,0,0,0,
805	TYPE_SPECIAL,OPERATION_SPECIAL_L_MSYNC,false,
806	0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
807	EXCEPTION_USE_NONE,EVENT_TYPE_MSYNC));
808	SEQ;
809
810	// ===== l.mtspr r10,r20,0x3fa
811	request [0].push_back (entry_t(
812	0xc00aa3fa,x,y,z,
813	0,0,0,0,0,0,
814	TYPE_SPECIAL,OPERATION_SPECIAL_L_MTSPR,false,
815	1,0x3fa, 1,10, 1,20, 0,0, 0,0, 0,0,
816	EXCEPTION_USE_NONE,EVENT_TYPE_SPR_ACCESS));
817	SEQ;
818
819	// ===== l.mtspr r10,r20,0xfc06
820	request [0].push_back (entry_t(
821	0xc3eaa406,x,y,z,
822	0,0,0,0,0,0,
823	TYPE_SPECIAL,OPERATION_SPECIAL_L_MTSPR,false,
824	1,0xfc06, 1,10, 1,20, 0,0, 0,0, 0,0,
825	EXCEPTION_USE_NONE,EVENT_TYPE_SPR_ACCESS));
826	SEQ;
827
828	// ===== l.mul r30,r10,r20
829	request [0].push_back (entry_t(
830	0xe3caa306,x,y,z,
831	0,0,0,0,0,0,
832	TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false,
833	0,0, 1,10, 1,20, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
834	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
835	SEQ;
836
837	// ===== l.muli r30,r10,0x3fa
838	request [0].push_back (entry_t(
839	0xb3ca03fa,x,y,z,
840	0,0,0,0,0,0,
841	TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false,
842	1,0x3fa, 1,10, 0,0, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
843	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
844	SEQ;
845
846	// ===== l.muli r30,r10,0xfffffc06
847	request [0].push_back (entry_t(
848	0xb3cafc06,x,y,z,
849	0,0,0,0,0,0,
850	TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MUL,false,
851	1,0xfffffc06, 1,10, 0,0, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
852	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
853	SEQ;
854
855	// ===== l.mulu r30,r10,r20
856	request [0].push_back (entry_t(
857	0xe3caa30b,x,y,z,
858	0,0,0,0,0,0,
859	TYPE_MUL_DIV,OPERATION_MUL_DIV_L_MULU,false,
860	0,0, 1,10, 1,20, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
861	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
862	SEQ;
863
864	// ===== l.nop 0x3fa
865	request [0].push_back (entry_t(
866	0x150003fa,x,y,z,
867	0,0,0,0,0,0,
868	TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP,false,
869	0,0x3fa, 0,0, 0,0, 0,0, 0,0, 0,0,
870	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
871	SEQ;
872
873	// ===== l.nop 0xfc06
874	request [0].push_back (entry_t(
875	0x1500fc06,x,y,z,
876	0,0,0,0,0,0,
877	TYPE_SPECIAL,OPERATION_SPECIAL_L_NOP,false,
878	0,0xfc06, 0,0, 0,0, 0,0, 0,0, 0,0,
879	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
880	SEQ;
881
882	// ===== l.or r30,r10,r20
883	request [0].push_back (entry_t(
884	0xe3caa004,x,y,z,
885	0,0,0,0,0,0,
886	TYPE_ALU,OPERATION_ALU_L_OR,false,
887	0,0, 1,10, 1,20, 0,0, 1,30, 0,0,
888	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
889	SEQ;
890
891	// ===== l.ori r30,r10,0x3fa
892	request [0].push_back (entry_t(
893	0xabca03fa,x,y,z,
894	0,0,0,0,0,0,
895	TYPE_ALU,OPERATION_ALU_L_OR,false,
896	1,0x3fa, 1,10, 0,0, 0,0, 1,30, 0,0,
897	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
898	SEQ;
899
900	// ===== l.ori r30,r10,0xfc06
901	request [0].push_back (entry_t(
902	0xabcafc06,x,y,z,
903	0,0,0,0,0,0,
904	TYPE_ALU,OPERATION_ALU_L_OR,false,
905	1,0xfc06, 1,10, 0,0, 0,0, 1,30, 0,0,
906	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
907	SEQ;
908
909	// ===== l.psync
910	request [0].push_back (entry_t(
911	0x22800000,x,y,z,
912	0,0,0,0,0,0,
913	TYPE_SPECIAL,OPERATION_SPECIAL_L_PSYNC,false,
914	0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
915	EXCEPTION_USE_NONE,EVENT_TYPE_PSYNC));
916	SEQ;
917
918	// ===== l.ror r30,r10,r20
919	request [0].push_back (entry_t(
920	0xe3caa0c8,x,y,z,
921	0,0,0,0,0,0,
922	TYPE_SHIFT,OPERATION_SHIFT_L_ROR,false,
923	0,0, 1,10, 1,20, 0,0, 1,30, 0,0,
924	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
925	SEQ;
926
927	// ===== l.rori r30,r10,0x3f
928	request [0].push_back (entry_t(
929	0xbbca00ff,x,y,z,
930	0,0,0,0,0,0,
931	TYPE_SHIFT,OPERATION_SHIFT_L_ROR,false,
932	1,0x3f, 1,10, 0,0, 0,0, 1,30, 0,0,
933	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
934	SEQ;
935
936	// ===== l.rori r30,r10,0x1
937	request [0].push_back (entry_t(
938	0xbbca00c1,x,y,z,
939	0,0,0,0,0,0,
940	TYPE_SHIFT,OPERATION_SHIFT_L_ROR,false,
941	1,0x1, 1,10, 0,0, 0,0, 1,30, 0,0,
942	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
943	SEQ;
944
945	// ===== l.sb 0x3fa(r10),r20
946	request [0].push_back (entry_t(
947	0xd80aa3fa,x,y,z,
948	0,0,0,0,0,0,
949	TYPE_MEMORY,OPERATION_MEMORY_STORE_8,false,
950	1,0x3fa, 1,10, 1,20, 0,0, 0,0, 0,0,
951	EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT,EVENT_TYPE_NONE));
952	SEQ;
953
954	// ===== l.sb 0xfffffc06(r10),r20
955	request [0].push_back (entry_t(
956	0xdbeaa406,x,y,z,
957	0,0,0,0,0,0,
958	TYPE_MEMORY,OPERATION_MEMORY_STORE_8,false,
959	1,0xfffffc06, 1,10, 1,20, 0,0, 0,0, 0,0,
960	EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT,EVENT_TYPE_NONE));
961	SEQ;
962
963	// ===== l.sd 0x3fa(r10),r20
964	request [0].push_back (entry_t(
965	0xd00aa3fa,x,y,z,
966	0,0,0,0,0,0,
967	TYPE_MEMORY,OPERATION_MEMORY_STORE_64,false,
968	1,0x3fa, 1,10, 1,20, 0,0, 0,0, 0,0,
969	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
970	SEQ;
971
972	// ===== l.sd 0xfffffc06(r10),r20
973	request [0].push_back (entry_t(
974	0xd3eaa406,x,y,z,
975	0,0,0,0,0,0,
976	TYPE_MEMORY,OPERATION_MEMORY_STORE_64,false,
977	1,0xfffffc06, 1,10, 1,20, 0,0, 0,0, 0,0,
978	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
979	SEQ;
980
981	// ===== l.sh 0x3fa(r10),r20
982	request [0].push_back (entry_t(
983	0xdc0aa3fa,x,y,z,
984	0,0,0,0,0,0,
985	TYPE_MEMORY,OPERATION_MEMORY_STORE_16,false,
986	1,0x3fa, 1,10, 1,20, 0,0, 0,0, 0,0,
987	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
988	SEQ;
989
990	// ===== l.sh 0xfffffc06(r10),r20
991	request [0].push_back (entry_t(
992	0xdfeaa406,x,y,z,
993	0,0,0,0,0,0,
994	TYPE_MEMORY,OPERATION_MEMORY_STORE_16,false,
995	1,0xfffffc06, 1,10, 1,20, 0,0, 0,0, 0,0,
996	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
997	SEQ;
998
999	// ===== l.sw 0x3fa(r10),r20
1000	request [0].push_back (entry_t(
1001	0xd40aa3fa,x,y,z,
1002	0,0,0,0,0,0,
1003	TYPE_MEMORY,OPERATION_MEMORY_STORE_32,false,
1004	1,0x3fa, 1,10, 1,20, 0,0, 0,0, 0,0,
1005	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
1006	SEQ;
1007
1008	// ===== l.sw 0xfffffc06(r10),r20
1009	request [0].push_back (entry_t(
1010	0xd7eaa406,x,y,z,
1011	0,0,0,0,0,0,
1012	TYPE_MEMORY,OPERATION_MEMORY_STORE_32,false,
1013	1,0xfffffc06, 1,10, 1,20, 0,0, 0,0, 0,0,
1014	EXCEPTION_USE_MEMORY_WITH_ALIGNMENT,EVENT_TYPE_NONE));
1015	SEQ;
1016
1017	// ===== l.sll r30,r10,r20
1018	request [0].push_back (entry_t(
1019	0xe3caa008,x,y,z,
1020	0,0,0,0,0,0,
1021	TYPE_SHIFT,OPERATION_SHIFT_L_SLL,false,
1022	0,0, 1,10, 1,20, 0,0, 1,30, 0,0,
1023	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1024	SEQ;
1025
1026	// ===== l.slli r30,r10,0x1
1027	request [0].push_back (entry_t(
1028	0xbbca0001,x,y,z,
1029	0,0,0,0,0,0,
1030	TYPE_SHIFT,OPERATION_SHIFT_L_SLL,false,
1031	1,0x1, 1,10, 0,0, 0,0, 1,30, 0,0,
1032	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1033	SEQ;
1034
1035	// ===== l.slli r30,r10,0x3f
1036	request [0].push_back (entry_t(
1037	0xbbca003f,x,y,z,
1038	0,0,0,0,0,0,
1039	TYPE_SHIFT,OPERATION_SHIFT_L_SLL,false,
1040	1,0x3f, 1,10, 0,0, 0,0, 1,30, 0,0,
1041	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1042	SEQ;
1043
1044	// ===== l.sra r30,r10,r20
1045	request [0].push_back (entry_t(
1046	0xe3caa088,x,y,z,
1047	0,0,0,0,0,0,
1048	TYPE_SHIFT,OPERATION_SHIFT_L_SRA,false,
1049	0,0, 1,10, 1,20, 0,0, 1,30, 0,0,
1050	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1051	SEQ;
1052
1053	// ===== l.srai r30,r10,0x1
1054	request [0].push_back (entry_t(
1055	0xbbca0081,x,y,z,
1056	0,0,0,0,0,0,
1057	TYPE_SHIFT,OPERATION_SHIFT_L_SRA,false,
1058	1,0x1, 1,10, 0,0, 0,0, 1,30, 0,0,
1059	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1060	SEQ;
1061
1062	// ===== l.srai r30,r10,0x3f
1063	request [0].push_back (entry_t(
1064	0xbbca00bf,x,y,z,
1065	0,0,0,0,0,0,
1066	TYPE_SHIFT,OPERATION_SHIFT_L_SRA,false,
1067	1,0x3f, 1,10, 0,0, 0,0, 1,30, 0,0,
1068	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1069	SEQ;
1070
1071	// ===== l.srl r30,r10,r20
1072	request [0].push_back (entry_t(
1073	0xe3caa048,x,y,z,
1074	0,0,0,0,0,0,
1075	TYPE_SHIFT,OPERATION_SHIFT_L_SRL,false,
1076	0,0, 1,10, 1,20, 0,0, 1,30, 0,0,
1077	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1078	SEQ;
1079
1080	// ===== l.srli r30,r10,0x1
1081	request [0].push_back (entry_t(
1082	0xbbca0041,x,y,z,
1083	0,0,0,0,0,0,
1084	TYPE_SHIFT,OPERATION_SHIFT_L_SRL,false,
1085	1,0x1, 1,10, 0,0, 0,0, 1,30, 0,0,
1086	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1087	SEQ;
1088
1089	// ===== l.srli r30,r10,0x3f
1090	request [0].push_back (entry_t(
1091	0xbbca007f,x,y,z,
1092	0,0,0,0,0,0,
1093	TYPE_SHIFT,OPERATION_SHIFT_L_SRL,false,
1094	1,0x3f, 1,10, 0,0, 0,0, 1,30, 0,0,
1095	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1096	SEQ;
1097
1098	// ===== l.xor r30,r10,r20
1099	request [0].push_back (entry_t(
1100	0xe3caa005,x,y,z,
1101	0,0,0,0,0,0,
1102	TYPE_ALU,OPERATION_ALU_L_XOR,false,
1103	0,0, 1,10, 1,20, 0,0, 1,30, 0,0,
1104	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1105	SEQ;
1106
1107	// ===== l.xori r30,r10,0x3fa
1108	request [0].push_back (entry_t(
1109	0xafca03fa,x,y,z,
1110	0,0,0,0,0,0,
1111	TYPE_ALU,OPERATION_ALU_L_XOR,false,
1112	1,0x3fa, 1,10, 0,0, 0,0, 1,30, 0,0,
1113	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1114	SEQ;
1115
1116	// ===== l.xori r30,r10,0xfffffc06
1117	request [0].push_back (entry_t(
1118	0xafcafc06,x,y,z,
1119	0,0,0,0,0,0,
1120	TYPE_ALU,OPERATION_ALU_L_XOR,false,
1121	1,0xfffffc06, 1,10, 0,0, 0,0, 1,30, 0,0,
1122	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1123	SEQ;
1124
1125	// ===== l.sub r30,r10,r20
1126	request [0].push_back (entry_t(
1127	0xe3caa002,x,y,z,
1128	0,0,0,0,0,0,
1129	TYPE_ALU,OPERATION_ALU_L_SUB,false,
1130	0,0, 1,10, 1,20, 0,0, 1,30, 1,SPR_LOGIC_SR_CY_OV,
1131	EXCEPTION_USE_RANGE,EVENT_TYPE_NONE));
1132	SEQ;
1133
1134	// ===== l.sys 0x3fa
1135	request [0].push_back (entry_t(
1136	0x200003fa,x,y,z,
1137	0,0,0,0,0,z,
1138	TYPE_SPECIAL,OPERATION_SPECIAL_L_SYS,false,
1139	0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
1140	EXCEPTION_USE_SYSCALL,EVENT_TYPE_EXCEPTION));
1141	SEQ;
1142
1143	// ===== l.sys 0xfc06
1144	request [0].push_back (entry_t(
1145	0x2000fc06,x,y,z,
1146	0,0,0,0,0,z,
1147	TYPE_SPECIAL,OPERATION_SPECIAL_L_SYS,false,
1148	0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
1149	EXCEPTION_USE_SYSCALL,EVENT_TYPE_EXCEPTION));
1150	SEQ;
1151
1152	// ===== l.trap 0x3fa
1153	request [0].push_back (entry_t(
1154	0x210003fa,x,y,z,
1155	0,0,0,0,0,0,
1156	TYPE_SPECIAL,OPERATION_SPECIAL_L_TRAP,false,
1157	1,0x3fa, 0,0, 0,0, 0,0, 0,0, 0,0,
1158	EXCEPTION_USE_TRAP,EVENT_TYPE_NONE));
1159	SEQ;
1160
1161	// ===== l.trap 0xfc06
1162	request [0].push_back (entry_t(
1163	0x2100fc06,x,y,z,
1164	0,0,0,0,0,0,
1165	TYPE_SPECIAL,OPERATION_SPECIAL_L_TRAP,false,
1166	1,0xfc06, 0,0, 0,0, 0,0, 0,0, 0,0,
1167	EXCEPTION_USE_TRAP,EVENT_TYPE_NONE));
1168	SEQ;
1169
1170	// ===== l.rfe
1171	request [0].push_back (entry_t(
1172	0x24000000,x,y,z,
1173	0,0,0,0,0,0,
1174	TYPE_SPECIAL,OPERATION_SPECIAL_L_RFE,false,
1175	0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
1176	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1177	SEQ;
1178
1179	// ===== l.sfeq r10,r20
1180	request [0].push_back (entry_t(
1181	0xe40aa000,x,y,z,
1182	0,0,0,0,0,0,
1183	TYPE_TEST,OPERATION_TEST_L_SFEQ,false,
1184	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1185	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1186	SEQ;
1187
1188	// ===== l.sfeqi r10,0x3fa
1189	request [0].push_back (entry_t(
1190	0xbc0a03fa,x,y,z,
1191	0,0,0,0,0,0,
1192	TYPE_TEST,OPERATION_TEST_L_SFEQ,false,
1193	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1194	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1195	SEQ;
1196
1197	// ===== l.sfeqi r10,0xfffffc06
1198	request [0].push_back (entry_t(
1199	0xbc0afc06,x,y,z,
1200	0,0,0,0,0,0,
1201	TYPE_TEST,OPERATION_TEST_L_SFEQ,false,
1202	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1203	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1204	SEQ;
1205
1206	// ===== l.sfne r10,r20
1207	request [0].push_back (entry_t(
1208	0xe42aa000,x,y,z,
1209	0,0,0,0,0,0,
1210	TYPE_TEST,OPERATION_TEST_L_SFNE,false,
1211	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1212	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1213	SEQ;
1214
1215	// ===== l.sfnei r10,0x3fa
1216	request [0].push_back (entry_t(
1217	0xbc2a03fa,x,y,z,
1218	0,0,0,0,0,0,
1219	TYPE_TEST,OPERATION_TEST_L_SFNE,false,
1220	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1221	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1222	SEQ;
1223
1224	// ===== l.sfnei r10,0xfffffc06
1225	request [0].push_back (entry_t(
1226	0xbc2afc06,x,y,z,
1227	0,0,0,0,0,0,
1228	TYPE_TEST,OPERATION_TEST_L_SFNE,false,
1229	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1230	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1231	SEQ;
1232
1233	// ===== l.sfges r10,r20
1234	request [0].push_back (entry_t(
1235	0xe56aa000,x,y,z,
1236	0,0,0,0,0,0,
1237	TYPE_TEST,OPERATION_TEST_L_SFGES,false,
1238	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1239	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1240	SEQ;
1241
1242	// ===== l.sfgesi r10,0x3fa
1243	request [0].push_back (entry_t(
1244	0xbd6a03fa,x,y,z,
1245	0,0,0,0,0,0,
1246	TYPE_TEST,OPERATION_TEST_L_SFGES,false,
1247	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1248	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1249	SEQ;
1250
1251	// ===== l.sfgesi r10,0xfffffc06
1252	request [0].push_back (entry_t(
1253	0xbd6afc06,x,y,z,
1254	0,0,0,0,0,0,
1255	TYPE_TEST,OPERATION_TEST_L_SFGES,false,
1256	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1257	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1258	SEQ;
1259
1260	// ===== l.sfgeu r10,r20
1261	request [0].push_back (entry_t(
1262	0xe46aa000,x,y,z,
1263	0,0,0,0,0,0,
1264	TYPE_TEST,OPERATION_TEST_L_SFGEU,false,
1265	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1266	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1267	SEQ;
1268
1269	// ===== l.sfgeui r10,0x3fa
1270	request [0].push_back (entry_t(
1271	0xbc6a03fa,x,y,z,
1272	0,0,0,0,0,0,
1273	TYPE_TEST,OPERATION_TEST_L_SFGEU,false,
1274	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1275	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1276	SEQ;
1277
1278	// ===== l.sfgeui r10,0xfffffc06
1279	request [0].push_back (entry_t(
1280	0xbc6afc06,x,y,z,
1281	0,0,0,0,0,0,
1282	TYPE_TEST,OPERATION_TEST_L_SFGEU,false,
1283	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1284	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1285	SEQ;
1286
1287	// ===== l.sfgts r10,r20
1288	request [0].push_back (entry_t(
1289	0xe54aa000,x,y,z,
1290	0,0,0,0,0,0,
1291	TYPE_TEST,OPERATION_TEST_L_SFGTS,false,
1292	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1293	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1294	SEQ;
1295
1296	// ===== l.sfgtsi r10,0x3fa
1297	request [0].push_back (entry_t(
1298	0xbd4a03fa,x,y,z,
1299	0,0,0,0,0,0,
1300	TYPE_TEST,OPERATION_TEST_L_SFGTS,false,
1301	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1302	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1303	SEQ;
1304
1305	// ===== l.sfgtsi r10,0xfffffc06
1306	request [0].push_back (entry_t(
1307	0xbd4afc06,x,y,z,
1308	0,0,0,0,0,0,
1309	TYPE_TEST,OPERATION_TEST_L_SFGTS,false,
1310	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1311	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1312	SEQ;
1313
1314	// ===== l.sfgtu r10,r20
1315	request [0].push_back (entry_t(
1316	0xe44aa000,x,y,z,
1317	0,0,0,0,0,0,
1318	TYPE_TEST,OPERATION_TEST_L_SFGTU,false,
1319	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1320	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1321	SEQ;
1322
1323	// ===== l.sfgtui r10,0x3fa
1324	request [0].push_back (entry_t(
1325	0xbc4a03fa,x,y,z,
1326	0,0,0,0,0,0,
1327	TYPE_TEST,OPERATION_TEST_L_SFGTU,false,
1328	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1329	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1330	SEQ;
1331
1332	// ===== l.sfgtui r10,0xfffffc06
1333	request [0].push_back (entry_t(
1334	0xbc4afc06,x,y,z,
1335	0,0,0,0,0,0,
1336	TYPE_TEST,OPERATION_TEST_L_SFGTU,false,
1337	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1338	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1339	SEQ;
1340
1341	// ===== l.sfles r10,r20
1342	request [0].push_back (entry_t(
1343	0xe5aaa000,x,y,z,
1344	0,0,0,0,0,0,
1345	TYPE_TEST,OPERATION_TEST_L_SFLES,false,
1346	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1347	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1348	SEQ;
1349
1350	// ===== l.sflesi r10,0x3fa
1351	request [0].push_back (entry_t(
1352	0xbdaa03fa,x,y,z,
1353	0,0,0,0,0,0,
1354	TYPE_TEST,OPERATION_TEST_L_SFLES,false,
1355	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1356	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1357	SEQ;
1358
1359	// ===== l.sflesi r10,0xfffffc06
1360	request [0].push_back (entry_t(
1361	0xbdaafc06,x,y,z,
1362	0,0,0,0,0,0,
1363	TYPE_TEST,OPERATION_TEST_L_SFLES,false,
1364	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1365	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1366	SEQ;
1367
1368	// ===== l.sfleu r10,r20
1369	request [0].push_back (entry_t(
1370	0xe4aaa000,x,y,z,
1371	0,0,0,0,0,0,
1372	TYPE_TEST,OPERATION_TEST_L_SFLEU,false,
1373	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1374	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1375	SEQ;
1376
1377	// ===== l.sfleui r10,0x3fa
1378	request [0].push_back (entry_t(
1379	0xbcaa03fa,x,y,z,
1380	0,0,0,0,0,0,
1381	TYPE_TEST,OPERATION_TEST_L_SFLEU,false,
1382	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1383	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1384	SEQ;
1385
1386	// ===== l.sfleui r10,0xfffffc06
1387	request [0].push_back (entry_t(
1388	0xbcaafc06,x,y,z,
1389	0,0,0,0,0,0,
1390	TYPE_TEST,OPERATION_TEST_L_SFLEU,false,
1391	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1392	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1393	SEQ;
1394
1395	// ===== l.sflts r10,r20
1396	request [0].push_back (entry_t(
1397	0xe58aa000,x,y,z,
1398	0,0,0,0,0,0,
1399	TYPE_TEST,OPERATION_TEST_L_SFLTS,false,
1400	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1401	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1402	SEQ;
1403
1404	// ===== l.sfltsi r10,0x3fa
1405	request [0].push_back (entry_t(
1406	0xbd8a03fa,x,y,z,
1407	0,0,0,0,0,0,
1408	TYPE_TEST,OPERATION_TEST_L_SFLTS,false,
1409	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1410	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1411	SEQ;
1412
1413	// ===== l.sfltsi r10,0xfffffc06
1414	request [0].push_back (entry_t(
1415	0xbd8afc06,x,y,z,
1416	0,0,0,0,0,0,
1417	TYPE_TEST,OPERATION_TEST_L_SFLTS,false,
1418	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1419	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1420	SEQ;
1421
1422	// ===== l.sfltu r10,r20
1423	request [0].push_back (entry_t(
1424	0xe48aa000,x,y,z,
1425	0,0,0,0,0,0,
1426	TYPE_TEST,OPERATION_TEST_L_SFLTU,false,
1427	0,0, 1,10, 1,20, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1428	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1429	SEQ;
1430
1431	// ===== l.sfltui r10,0x3fa
1432	request [0].push_back (entry_t(
1433	0xbc8a03fa,x,y,z,
1434	0,0,0,0,0,0,
1435	TYPE_TEST,OPERATION_TEST_L_SFLTU,false,
1436	1,0x3fa, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1437	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1438	SEQ;
1439
1440	// ===== l.sfltui r10,0xfffffc06
1441	request [0].push_back (entry_t(
1442	0xbc8afc06,x,y,z,
1443	0,0,0,0,0,0,
1444	TYPE_TEST,OPERATION_TEST_L_SFLTU,false,
1445	1,0xfffffc06, 1,10, 0,0, 0,0, 0,0, 1,SPR_LOGIC_SR_F,
1446	EXCEPTION_USE_NONE,EVENT_TYPE_NONE));
1447	SEQ;
1448
1449	for (uint32_t i=1; i<_param->_nb_context; i++)
1450	{
1451	request[i] = request [0];
1452	}
1453
1454	for (uint32_t i=0; i<_param->_nb_context; i++)
1455	{
1456	delay_slot_current [i] = false;
1457	delay_slot_next [i] = false;
1458	}
1459
1460	uint32_t nb_request = request[0].size() * _param->_nb_context;
1461
1462	while (nb_request > 0)
1463	{
1464	for (uint32_t i=0; i<_param->_nb_context; i++)
1465	{
1466	delay_slot_previous [i] = false;
1467
1468	in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)<percent_transaction_decod);
1469
1470	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
1471	in_IFETCH_VAL [i][j]->write(0);
1472
1473	if ((rand()%100)<percent_transaction_ifetch)
1474	{
1475	list<entry_t>::iterator it = request [i].begin();
1476
1477	if (it!=request [i].end())
1478	{
1479	uint32_t lsb = (it->_address>>2)%_param->_nb_inst_fetch[i];
1480
1481	in_IFETCH_ADDRESS [i]->write(it->_address-(lsb<<2));
1482	in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE);
1483	if (_param->_have_port_inst_ifetch_ptr)
1484	in_IFETCH_INST_IFETCH_PTR [i]->write(0);
1485
1486	// Alignement
1487	for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++)
1488	{
1489	in_IFETCH_VAL [i][j]->write(1);
1490	in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction);
1491	// in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next);
1492	if (it->_type == TYPE_BRANCH)
1493	in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state);
1494	in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id);
1495
1496	if ((it->_is_delay_slot) or
1497	((++it)==request [i].end()))
1498	break;
1499	}
1500	}
1501	}
1502	}
1503
1504	{
1505	bool previous_ack = true;
1506
1507	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
1508	{
1509	bool ack = previous_ack and ((rand()%100)<percent_transaction_decod);
1510	in_DECOD_ACK [i]->write(ack);
1511
1512	previous_ack = ack;
1513
1514	in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict);
1515	// in_PREDICT_CAN_CONTINUE [i]->write(0);
1516	}
1517	}
1518
1519	in_CONTEXT_EVENT_ACK->write((rand()%100)<percent_transaction_event);
1520
1521	SC_START(0);
1522
1523
1524	uint32_t nb_inst_ifetch = 0;
1525	for (uint32_t i=0; i<_param->_nb_context; i++)
1526	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
1527	if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read())
1528	{
1529	LABEL("IFETCH [%d][%d] : transaction",i,j);
1530	nb_inst_ifetch ++;
1531	}
1532
1533	uint32_t nb_inst_decod = 0;
1534	uint32_t find_event = false;
1535
1536	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
1537	if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read())
1538	{
1539	Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0;
1540
1541	LABEL("DECOD [%d] : transaction",i );
1542	LABEL(" * context : %d",context);
1543
1544	if (_param->_have_port_depth)
1545	TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), request [context].front()._depth );
1546	TEST(Ttype_t , out_DECOD_TYPE [i]->read(), request [context].front()._type );
1547	TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), request [context].front()._operation );
1548	TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), request [context].front()._is_delay_slot);
1549	TEST(Tcontrol_t , delay_slot_current [context] , request [context].front()._is_delay_slot);
1550	TEST(Tgeneral_data_t , out_DECOD_ADDRESS [i]->read(), request [context].front()._address );
1551	TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), request [context].front()._has_immediat );
1552	if (request [context].front()._has_immediat)
1553	TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), request [context].front()._immediat );
1554	TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), request [context].front()._read_ra );
1555	if (request [context].front()._read_ra)
1556	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), request [context].front()._num_reg_ra );
1557	TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), request [context].front()._read_rb );
1558	if (request [context].front()._read_rb)
1559	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), request [context].front()._num_reg_rb );
1560	TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), request [context].front()._read_rc );
1561	if (request [context].front()._read_rc)
1562	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), request [context].front()._num_reg_rc );
1563	TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), request [context].front()._write_rd );
1564	if (request [context].front()._write_rd)
1565	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), request [context].front()._num_reg_rd );
1566	TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), request [context].front()._write_re );
1567	if (request [context].front()._write_re)
1568	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), request [context].front()._num_reg_re );
1569	TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), request [context].front()._exception_use);
1570
1571	if (request [context].front()._type == TYPE_BRANCH)
1572	{
1573	delay_slot_next [context] = true;
1574
1575	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), true);
1576	TEST(Tcontrol_t, in_PREDICT_ACK[i]->read(), true);
1577
1578	LABEL("PREDICT [%d] : transaction",i );
1579
1580	if (_param->_have_port_context_id)
1581	TEST(Tcontext_t , out_PREDICT_CONTEXT_ID [i]->read(), context);
1582	TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [i]->read(),((request [context].front()._address>>2)%_param->_nb_inst_fetch[context]) == 0);
1583	TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [i]->read(), request [context].front()._branch_state );
1584	if (_param->_have_port_branch_update_prediction_id)
1585	TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id);
1586	TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [i]->read(), request [context].front()._branch_condition );
1587	// TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [i]->read(), request [context].front()._branch_stack_write );
1588	TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [i]->read(), request [context].front()._branch_direction );
1589	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i]->read(), request [context].front()._address );
1590	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i]->read(), request [context].front()._branch_address_dest );
1591	}
1592	else
1593	{
1594	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), false);
1595	}
1596
1597	TEST(bool, find_event, false); // can continue decod after event
1598	if (request [context].front()._context_event_type != EVENT_TYPE_NONE)
1599	{
1600	find_event = true;
1601
1602	LABEL("CONTEXT_EVENT : transaction");
1603
1604	if (_param->_have_port_context_id)
1605	TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), context);
1606	TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), request [context].front()._context_event_type);
1607	TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot);
1608	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), request [context].front()._address );
1609	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), request [context].front()._address_next );
1610
1611	}
1612
1613	TEST(bool, delay_slot_previous [context], false); // can't continue
1614	delay_slot_previous [context] = delay_slot_current [context];
1615	delay_slot_current [context] = delay_slot_next [context];
1616	delay_slot_next [context] = false;
1617
1618	request [context].pop_front();
1619	nb_inst_decod ++;
1620	nb_request --;
1621	}
1622
1623	TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event);
1624	TEST(uint32_t, nb_inst_decod, nb_inst_ifetch);
1625
1626	SC_START(1);
1627	}
1628	}
1629
1630	/********************************************************
1631	* Simulation - End
1632	********************************************************/
1633
1634	TEST_OK ("End of Simulation");
1635	delete _time;
1636
1637	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
1638
1639	delete in_CLOCK;
1640	delete in_NRESET;
1641
1642	delete [] in_IFETCH_VAL ;
1643	delete [] out_IFETCH_ACK ;
1644	delete [] in_IFETCH_INSTRUCTION ;
1645	delete [] in_IFETCH_CONTEXT_ID ;
1646	delete [] in_IFETCH_ADDRESS ;
1647	// delete [] in_IFETCH_ADDRESS_NEXT ;
1648	delete [] in_IFETCH_INST_IFETCH_PTR ;
1649	delete [] in_IFETCH_BRANCH_STATE ;
1650	delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;
1651
1652	delete [] out_DECOD_VAL ;
1653	delete [] in_DECOD_ACK ;
1654	delete [] out_DECOD_CONTEXT_ID ;
1655	delete [] out_DECOD_DEPTH ;
1656	delete [] out_DECOD_TYPE ;
1657	delete [] out_DECOD_OPERATION ;
1658	delete [] out_DECOD_IS_DELAY_SLOT ;
1659	delete [] out_DECOD_ADDRESS ;
1660	delete [] out_DECOD_HAS_IMMEDIAT ;
1661	delete [] out_DECOD_IMMEDIAT ;
1662	delete [] out_DECOD_READ_RA ;
1663	delete [] out_DECOD_NUM_REG_RA ;
1664	delete [] out_DECOD_READ_RB ;
1665	delete [] out_DECOD_NUM_REG_RB ;
1666	delete [] out_DECOD_READ_RC ;
1667	delete [] out_DECOD_NUM_REG_RC ;
1668	delete [] out_DECOD_WRITE_RD ;
1669	delete [] out_DECOD_NUM_REG_RD ;
1670	delete [] out_DECOD_WRITE_RE ;
1671	delete [] out_DECOD_NUM_REG_RE ;
1672	delete [] out_DECOD_EXCEPTION_USE ;
1673
1674	delete [] out_PREDICT_VAL ;
1675	delete [] in_PREDICT_ACK ;
1676	delete [] out_PREDICT_CONTEXT_ID ;
1677	delete [] out_PREDICT_MATCH_INST_IFETCH_PTR ;
1678	delete [] out_PREDICT_BRANCH_STATE ;
1679	delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
1680	delete [] out_PREDICT_BRANCH_CONDITION ;
1681	// delete [] out_PREDICT_BRANCH_STACK_WRITE ;
1682	delete [] out_PREDICT_BRANCH_DIRECTION ;
1683	delete [] out_PREDICT_ADDRESS_SRC ;
1684	delete [] out_PREDICT_ADDRESS_DEST ;
1685	// delete [] in_PREDICT_CAN_CONTINUE ;
1686
1687	delete [] in_CONTEXT_DECOD_ENABLE ;
1688	delete [] in_CONTEXT_DEPTH ;
1689
1690	delete out_CONTEXT_EVENT_VAL ;
1691	delete in_CONTEXT_EVENT_ACK ;
1692	delete out_CONTEXT_EVENT_CONTEXT_ID ;
1693	delete out_CONTEXT_EVENT_TYPE ;
1694	delete out_CONTEXT_EVENT_IS_DELAY_SLOT ;
1695	delete out_CONTEXT_EVENT_ADDRESS ;
1696	delete out_CONTEXT_EVENT_ADDRESS_EPCR ;
1697	#endif
1698
1699	delete _Decod;
1700	#ifdef STATISTICS
1701	delete _parameters_statistics;
1702	#endif
1703	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp @ 78

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