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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/src/test.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 16 years ago
Almost complete design with Test and test platform
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1	/*
2	* $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (2048*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/test.h"
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h"
14	#include <list>
15	#include "Common/include/Test.h"
16	#include "Behavioural/include/Allocation.h"
17
18	void test (string name,
19	morpheo::behavioural::core::multi_front_end::front_end::decod_unit::decod::Parameters * _param)
20	{
21	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
22
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,0);
25	#endif
26
27	Tusage_t _usage = USE_ALL;
28
29	// _usage = usage_unset(_usage,USE_SYSTEMC );
30	// _usage = usage_unset(_usage,USE_VHDL );
31	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
32	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
33	// _usage = usage_unset(_usage,USE_POSITION );
34	// _usage = usage_unset(_usage,USE_STATISTICS );
35	// _usage = usage_unset(_usage,USE_INFORMATION );
36
37	Decod * _Decod = new Decod
38	(name.c_str(),
39	#ifdef STATISTICS
40	_parameters_statistics,
41	#endif
42	_param,
43	_usage);
44
45	#ifdef SYSTEMC
46	/*********************************************************************
47	* Déclarations des signaux
48	*********************************************************************/
49	string rename;
50
51	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
52	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
53
54	ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
55	ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
56	ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
57	ALLOC1_SC_SIGNAL( in_IFETCH_CONTEXT_ID ," in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
58	ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS ," in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context);
59	// ALLOC1_SC_SIGNAL( in_IFETCH_ADDRESS_NEXT ," in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context);
60	ALLOC1_SC_SIGNAL( in_IFETCH_INST_IFETCH_PTR ," in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context);
61	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_STATE ," in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context);
62	ALLOC1_SC_SIGNAL( in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ," in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context);
63	ALLOC1_SC_SIGNAL( in_IFETCH_EXCEPTION ," in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context);
64
65	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
66	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
67	ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
68	ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
69	ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod);
70	ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod);
71	ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod);
72	ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod);
73	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod);
74	ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod);
75	ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod);
76	ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod);
77	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod);
78	ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod);
79	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod);
80	ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod);
81	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod);
82	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod);
83	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod);
84	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod);
85	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod);
86	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod);
87	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
95	// ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod);
98	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod);
99	// ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context);
101	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context);
102	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t );
103	ALLOC_SC_SIGNAL ( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t );
104	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t );
105	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t );
106	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t );
107	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
108	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t );
109	ALLOC_SC_SIGNAL (out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t );
110
111	/********************************************************
112	* Instanciation
113	********************************************************/
114
115	msg(_("<%s> : Instanciation of _Decod.\n"),name.c_str());
116
117	((_Decod->in_CLOCK)) ((in_CLOCK));
118	((_Decod->in_NRESET)) ((in_NRESET));
119
120	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_VAL ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
121	INSTANCE2_SC_SIGNAL(_Decod,out_IFETCH_ACK ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
122	INSTANCE2_SC_SIGNAL(_Decod, in_IFETCH_INSTRUCTION ,_param->_nb_context,_param->_nb_inst_fetch[it1]);
123	if (_param->_have_port_context_id)
124	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_CONTEXT_ID ,_param->_nb_context);
125	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS ,_param->_nb_context);
126	// INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_ADDRESS_NEXT ,_param->_nb_context);
127	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_STATE ,_param->_nb_context);
128	INSTANCE1_SC_SIGNAL(_Decod, in_IFETCH_EXCEPTION ,_param->_nb_context);
129
130	for (uint32_t i=0; i<_param->_nb_context; i++)
131	{
132	if (_param->_have_port_inst_ifetch_ptr)
133	INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_INST_IFETCH_PTR [i]);
134	// if (_param->_have_port_branch_update_prediction_id)
135	if (_param->_have_port_depth)
136	INSTANCE_SC_SIGNAL(_Decod, in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]);
137	}
138
139	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_VAL ,_param->_nb_inst_decod);
140	INSTANCE1_SC_SIGNAL(_Decod, in_DECOD_ACK ,_param->_nb_inst_decod);
141	if (_param->_have_port_context_id)
142	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
143	if (_param->_have_port_depth)
144	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_DEPTH ,_param->_nb_inst_decod);
145	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_TYPE ,_param->_nb_inst_decod);
146	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_OPERATION ,_param->_nb_inst_decod);
147	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod);
148	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod);
149	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_ADDRESS ,_param->_nb_inst_decod);
150	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod);
151	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod);
152	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RA ,_param->_nb_inst_decod);
153	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod);
154	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RB ,_param->_nb_inst_decod);
155	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod);
156	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_READ_RC ,_param->_nb_inst_decod);
157	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod);
158	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RD ,_param->_nb_inst_decod);
159	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod);
160	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_WRITE_RE ,_param->_nb_inst_decod);
161	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod);
162	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod);
163	INSTANCE1_SC_SIGNAL(_Decod,out_DECOD_EXCEPTION ,_param->_nb_inst_decod);
164	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_VAL ,_param->_nb_inst_decod);
165	INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_ACK ,_param->_nb_inst_decod);
166	if (_param->_have_port_context_id)
167	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod);
168	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod);
169	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod);
170	// if (_param->_have_port_branch_update_prediction_id)
171	if (_param->_have_port_depth)
172	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod);
173	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod);
174	// INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod);
175	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod);
176	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod);
177	INSTANCE1_SC_SIGNAL(_Decod,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod);
178	// INSTANCE1_SC_SIGNAL(_Decod, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);
179	INSTANCE1_SC_SIGNAL(_Decod, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context);
180	for (uint32_t i=0; i<_param->_nb_context; i++)
181	if (_param->_have_port_depth)
182	INSTANCE_SC_SIGNAL(_Decod, in_CONTEXT_DEPTH [i]);
183	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_VAL );
184	INSTANCE_SC_SIGNAL (_Decod, in_CONTEXT_EVENT_ACK );
185	if (_param->_have_port_context_id)
186	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_CONTEXT_ID );
187	if (_param->_have_port_depth)
188	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_DEPTH );
189	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_TYPE );
190	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_IS_DELAY_SLOT );
191	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS );
192	INSTANCE_SC_SIGNAL (_Decod,out_CONTEXT_EVENT_ADDRESS_EPCR );
193
194	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
195
196	Time * _time = new Time();
197
198	/********************************************************
199	* Simulation - Begin
200	********************************************************/
201
202	// Initialisation
203
204	const uint32_t seed = 0;
205	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
206
207	const int32_t percent_transaction_ifetch = 75;
208	const int32_t percent_transaction_decod = 75;
209	const int32_t percent_transaction_predict = 75;
210	const int32_t percent_transaction_event = 75;
211
212	srand(seed);
213
214	SC_START(0);
215	LABEL("Initialisation");
216
217	LABEL("Reset");
218	in_NRESET->write(0);
219	SC_START(5);
220	in_NRESET->write(1);
221
222	LABEL("Loop of Test");
223
224	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
225	{
226	LABEL("Iteration %d",iteration);
227
228	Decod_request request [_param->_nb_context];
229
230	uint32_t nb_request = 0;
231
232	uint32_t delay_slot_previous [_param->_nb_context];
233	uint32_t delay_slot_current [_param->_nb_context];
234	uint32_t delay_slot_next [_param->_nb_context];
235
236	for (uint32_t i=0; i<_param->_nb_context; i++)
237	{
238	nb_request += request[i].size();
239	delay_slot_current [i] = false;
240	delay_slot_next [i] = false;
241	}
242
243	while (nb_request > 0)
244	{
245	for (uint32_t i=0; i<_param->_nb_context; i++)
246	{
247	delay_slot_previous [i] = false;
248
249	in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)<percent_transaction_decod);
250
251	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
252	in_IFETCH_VAL [i][j]->write(0);
253
254	if ((rand()%100)<percent_transaction_ifetch)
255	{
256	list<entry_t>::iterator it = request[i].begin();
257
258	if (it!=request [i].end())
259	{
260	uint32_t lsb = it->_address%_param->_nb_inst_fetch[i];
261
262	in_IFETCH_ADDRESS [i]->write(it->_address-lsb);
263	in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE);
264	if (_param->_have_port_inst_ifetch_ptr)
265	in_IFETCH_INST_IFETCH_PTR [i]->write(0);
266	in_IFETCH_EXCEPTION [i]->write(EXCEPTION_IFETCH_NONE);
267
268	// Alignement
269	for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++)
270	{
271	in_IFETCH_VAL [i][j]->write(1);
272	in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction);
273	// in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next);
274	if (it->_type == TYPE_BRANCH)
275	in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state);
276	in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id);
277
278	if ((it->_is_delay_slot) or
279	((++it)==request [i].end()))
280	break;
281	}
282	}
283	}
284	}
285
286	{
287	bool previous_ack = true;
288
289	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
290	{
291	bool ack = previous_ack and ((rand()%100)<percent_transaction_decod);
292	in_DECOD_ACK [i]->write(ack);
293
294	previous_ack = ack;
295
296	in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict);
297	// in_PREDICT_CAN_CONTINUE [i]->write(0);
298	}
299	}
300
301	in_CONTEXT_EVENT_ACK->write((rand()%100)<percent_transaction_event);
302
303	SC_START(0);
304
305
306	uint32_t nb_inst_ifetch = 0;
307	for (uint32_t i=0; i<_param->_nb_context; i++)
308	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
309	if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read())
310	{
311	LABEL("IFETCH [%d][%d] : transaction",i,j);
312	nb_inst_ifetch ++;
313	}
314
315	uint32_t nb_inst_decod = 0;
316	uint32_t find_event = false;
317
318	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
319	if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read())
320	{
321	Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0;
322
323	LABEL("DECOD [%d] : transaction",i );
324	LABEL(" * context : %d",context);
325	LABEL(" * instruction : 0x%x",request [context].front()._instruction);
326
327	if (_param->_have_port_depth)
328	TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), request [context].front()._depth );
329	TEST(Ttype_t , out_DECOD_TYPE [i]->read(), request [context].front()._type );
330	TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), request [context].front()._operation );
331	TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), request [context].front()._is_delay_slot);
332	TEST(Tcontrol_t , delay_slot_current [context] , request [context].front()._is_delay_slot);
333	TEST(Tgeneral_data_t , out_DECOD_ADDRESS [i]->read(), request [context].front()._address );
334	TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), request [context].front()._has_immediat );
335	if (request [context].front()._has_immediat)
336	TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), request [context].front()._immediat );
337	TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), request [context].front()._read_ra );
338	if (request [context].front()._read_ra)
339	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), request [context].front()._num_reg_ra );
340	TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), request [context].front()._read_rb );
341	if (request [context].front()._read_rb)
342	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), request [context].front()._num_reg_rb );
343	TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), request [context].front()._read_rc );
344	if (request [context].front()._read_rc)
345	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), request [context].front()._num_reg_rc );
346	TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), request [context].front()._write_rd );
347	if (request [context].front()._write_rd)
348	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), request [context].front()._num_reg_rd );
349	TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), request [context].front()._write_re );
350	if (request [context].front()._write_re)
351	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), request [context].front()._num_reg_re );
352	TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), request [context].front()._exception_use);
353
354	if (request [context].front()._type == TYPE_BRANCH)
355	{
356	delay_slot_next [context] = true;
357
358	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), true);
359	TEST(Tcontrol_t, in_PREDICT_ACK[i]->read(), true);
360
361	LABEL("PREDICT [%d] : transaction",i );
362
363	if (_param->_have_port_context_id)
364	TEST(Tcontext_t , out_PREDICT_CONTEXT_ID [i]->read(), context);
365	TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [i]->read(),((request [context].front()._address)%_param->_nb_inst_fetch[context]) == 0);
366	TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [i]->read(), request [context].front()._branch_state );
367	// if (_param->_have_port_branch_update_prediction_id)
368	if (_param->_have_port_depth)
369	TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i]->read(), request [context].front()._branch_update_prediction_id);
370	TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [i]->read(), request [context].front()._branch_condition );
371	// TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [i]->read(), request [context].front()._branch_stack_write );
372	TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [i]->read(), request [context].front()._branch_direction );
373	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [i]->read(), request [context].front()._address );
374	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [i]->read(), request [context].front()._branch_address_dest );
375	}
376	else
377	{
378	TEST(Tcontrol_t, out_PREDICT_VAL[i]->read(), false);
379	}
380
381	TEST(bool, find_event, false); // can continue decod after event
382	if (request [context].front()._context_event_type != EVENT_TYPE_NONE)
383	{
384	find_event = true;
385
386	LABEL("CONTEXT_EVENT : transaction");
387
388	if (_param->_have_port_context_id)
389	TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), context);
390	if (_param->_have_port_depth )
391	TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), request [context].front()._depth );
392	TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), request [context].front()._context_event_type);
393	TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), request [context].front()._is_delay_slot);
394	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), request [context].front()._address );
395	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), request [context].front()._address_next );
396
397	}
398
399	TEST(bool, delay_slot_previous [context], false); // can't continue
400	delay_slot_previous [context] = delay_slot_current [context];
401	delay_slot_current [context] = delay_slot_next [context];
402	delay_slot_next [context] = false;
403
404	request [context].pop_front();
405	nb_inst_decod ++;
406	nb_request --;
407	}
408
409	TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event);
410	TEST(uint32_t, nb_inst_decod, nb_inst_ifetch);
411
412	SC_START(1);
413	}
414	}
415
416	/********************************************************
417	* Simulation - End
418	********************************************************/
419
420	TEST_OK ("End of Simulation");
421	delete _time;
422
423	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
424
425	delete in_CLOCK;
426	delete in_NRESET;
427
428	delete [] in_IFETCH_VAL ;
429	delete [] out_IFETCH_ACK ;
430	delete [] in_IFETCH_INSTRUCTION ;
431	delete [] in_IFETCH_CONTEXT_ID ;
432	delete [] in_IFETCH_ADDRESS ;
433	// delete [] in_IFETCH_ADDRESS_NEXT ;
434	delete [] in_IFETCH_INST_IFETCH_PTR ;
435	delete [] in_IFETCH_BRANCH_STATE ;
436	delete [] in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;
437	delete [] in_IFETCH_EXCEPTION ;
438
439	delete [] out_DECOD_VAL ;
440	delete [] in_DECOD_ACK ;
441	delete [] out_DECOD_CONTEXT_ID ;
442	delete [] out_DECOD_DEPTH ;
443	delete [] out_DECOD_TYPE ;
444	delete [] out_DECOD_OPERATION ;
445	delete [] out_DECOD_NO_EXECUTE ;
446	delete [] out_DECOD_IS_DELAY_SLOT ;
447	delete [] out_DECOD_ADDRESS ;
448	delete [] out_DECOD_HAS_IMMEDIAT ;
449	delete [] out_DECOD_IMMEDIAT ;
450	delete [] out_DECOD_READ_RA ;
451	delete [] out_DECOD_NUM_REG_RA ;
452	delete [] out_DECOD_READ_RB ;
453	delete [] out_DECOD_NUM_REG_RB ;
454	delete [] out_DECOD_READ_RC ;
455	delete [] out_DECOD_NUM_REG_RC ;
456	delete [] out_DECOD_WRITE_RD ;
457	delete [] out_DECOD_NUM_REG_RD ;
458	delete [] out_DECOD_WRITE_RE ;
459	delete [] out_DECOD_NUM_REG_RE ;
460	delete [] out_DECOD_EXCEPTION_USE ;
461	delete [] out_DECOD_EXCEPTION ;
462
463	delete [] out_PREDICT_VAL ;
464	delete [] in_PREDICT_ACK ;
465	delete [] out_PREDICT_CONTEXT_ID ;
466	delete [] out_PREDICT_MATCH_INST_IFETCH_PTR ;
467	delete [] out_PREDICT_BRANCH_STATE ;
468	delete [] out_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
469	delete [] out_PREDICT_BRANCH_CONDITION ;
470	//delete [] out_PREDICT_BRANCH_STACK_WRITE ;
471	delete [] out_PREDICT_BRANCH_DIRECTION ;
472	delete [] out_PREDICT_ADDRESS_SRC ;
473	delete [] out_PREDICT_ADDRESS_DEST ;
474	//delete [] in_PREDICT_CAN_CONTINUE ;
475
476	delete [] in_CONTEXT_DECOD_ENABLE ;
477	delete [] in_CONTEXT_DEPTH ;
478
479	delete out_CONTEXT_EVENT_VAL ;
480	delete in_CONTEXT_EVENT_ACK ;
481	delete out_CONTEXT_EVENT_CONTEXT_ID ;
482	delete out_CONTEXT_EVENT_DEPTH ;
483	delete out_CONTEXT_EVENT_TYPE ;
484	delete out_CONTEXT_EVENT_IS_DELAY_SLOT ;
485	delete out_CONTEXT_EVENT_ADDRESS ;
486	delete out_CONTEXT_EVENT_ADDRESS_EPCR ;
487	#endif
488
489	delete _Decod;
490	#ifdef STATISTICS
491	delete _parameters_statistics;
492	#endif
493	}

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