1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Decod_genMealy.cpp 81 2008-04-15 18:40:01Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace decod_unit { |
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17 | namespace decod { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Decod::genMealy" |
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22 | void Decod::genMealy (void) |
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23 | { |
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24 | log_printf(TRACE,Decod,FUNCTION,"Begin"); |
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25 | |
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26 | //----------------------------------- |
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27 | // Initialization |
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28 | //----------------------------------- |
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29 | Tcontrol_t context_event_val; |
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30 | Tcontrol_t ifetch_ack [_param->_nb_context][_param->_max_nb_inst_fetch]; |
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31 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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32 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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33 | ifetch_ack [i][j] = false; |
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34 | |
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35 | Tcontrol_t predict_val [_param->_nb_inst_decod]; |
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36 | Tcontrol_t decod_val [_param->_nb_inst_decod]; |
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37 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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38 | { |
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39 | decod_val [i] = false; |
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40 | } |
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41 | |
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42 | Tcontrol_t can_continue [_param->_nb_context]; |
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43 | Tcontrol_t can_continue_next [_param->_nb_context]; |
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44 | |
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45 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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46 | { |
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47 | internal_CONTEXT_HAVE_TRANSACTION [i] = false; |
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48 | internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i]; |
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49 | internal_CONTEXT_IS_DELAY_SLOT [i] = reg_CONTEXT_IS_DELAY_SLOT [i]; |
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50 | |
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51 | can_continue [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); |
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52 | can_continue_next [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]); |
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53 | } |
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54 | |
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55 | //----------------------------------- |
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56 | // Loop of decod |
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57 | //----------------------------------- |
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58 | // scan all decod "slot_out" |
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59 | std::list<select_t>::iterator it=select.begin(); |
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60 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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61 | { |
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62 | while ((it != select.end()) and // have a no scanned "slot_in" ? |
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63 | (decod_val [i] == false) and // have not a previous selected entry? |
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64 | (context_event_val == false)) // Have not a context_event (spr_access, exception, ...) |
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65 | { |
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66 | predict_val [i] = false; |
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67 | context_event_val = false; |
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68 | |
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69 | Tcontext_t x = it->_context ; |
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70 | uint32_t y = it->_inst_fetch; |
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71 | |
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72 | // Test if this instruction is valid |
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73 | if ((PORT_READ(in_IFETCH_VAL [x][y]) == 1) and // entry is valid |
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74 | (can_continue [x] == 1)) // context can decod instruction (have not a previous event) |
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75 | { |
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76 | can_continue [x] = can_continue_next [x]; |
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77 | |
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78 | decod_val [i] = true; // fetch_val and decod_enable |
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79 | ifetch_ack [x][y] = PORT_READ(in_DECOD_ACK [i]); // fetch_val and decod_enable and decod_ack |
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80 | |
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81 | Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x])+4*y; |
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82 | |
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83 | _decod_instruction->_instruction = PORT_READ(in_IFETCH_INSTRUCTION [x][y]); |
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84 | _decod_instruction->_context_id = x; |
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85 | _decod_instruction->_address_previous = internal_CONTEXT_ADDRESS_PREVIOUS [x]; |
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86 | _decod_instruction->_address = addr; //Compute the current address |
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87 | _decod_instruction->_address_next = addr+4; |
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88 | _decod_instruction->_is_delay_slot = internal_CONTEXT_IS_DELAY_SLOT [x]; |
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89 | |
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90 | // Decod ! |
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91 | log_printf(TRACE,Decod,FUNCTION,"DECOD [%d]",i); |
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92 | log_printf(TRACE,Decod,FUNCTION," * context : %d",x); |
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93 | log_printf(TRACE,Decod,FUNCTION," * fetch : %d",y); |
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94 | log_printf(TRACE,Decod,FUNCTION," * address : %.8x",addr); |
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95 | log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]); |
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96 | instruction_decod (_decod_instruction, _decod_param[x]); |
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97 | |
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98 | Ttype_t type = _decod_instruction->_type; |
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99 | |
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100 | if (_param->_have_port_context_id) |
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101 | PORT_WRITE(out_DECOD_CONTEXT_ID [i], x); |
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102 | if (_param->_have_port_depth) |
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103 | PORT_WRITE(out_DECOD_DEPTH [i], PORT_READ(in_CONTEXT_DEPTH [x])); |
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104 | PORT_WRITE(out_DECOD_TYPE [i], type); |
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105 | PORT_WRITE(out_DECOD_OPERATION [i], _decod_instruction->_operation ); |
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106 | PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot ); |
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107 | PORT_WRITE(out_DECOD_ADDRESS [i], addr); |
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108 | PORT_WRITE(out_DECOD_HAS_IMMEDIAT [i], _decod_instruction->_has_immediat ); |
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109 | PORT_WRITE(out_DECOD_IMMEDIAT [i], _decod_instruction->_immediat ); |
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110 | PORT_WRITE(out_DECOD_READ_RA [i], _decod_instruction->_read_ra ); |
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111 | PORT_WRITE(out_DECOD_NUM_REG_RA [i], _decod_instruction->_num_reg_ra ); |
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112 | PORT_WRITE(out_DECOD_READ_RB [i], _decod_instruction->_read_rb ); |
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113 | PORT_WRITE(out_DECOD_NUM_REG_RB [i], _decod_instruction->_num_reg_rb ); |
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114 | PORT_WRITE(out_DECOD_READ_RC [i], _decod_instruction->_read_rc ); |
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115 | PORT_WRITE(out_DECOD_NUM_REG_RC [i], _decod_instruction->_num_reg_rc ); |
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116 | PORT_WRITE(out_DECOD_WRITE_RD [i], _decod_instruction->_write_rd ); |
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117 | PORT_WRITE(out_DECOD_NUM_REG_RD [i], _decod_instruction->_num_reg_rd ); |
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118 | PORT_WRITE(out_DECOD_WRITE_RE [i], _decod_instruction->_write_re ); |
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119 | PORT_WRITE(out_DECOD_NUM_REG_RE [i], _decod_instruction->_num_reg_re ); |
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120 | PORT_WRITE(out_DECOD_EXCEPTION_USE [i], _decod_instruction->_exception_use ); |
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121 | |
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122 | if (type == TYPE_BRANCH) |
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123 | { |
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124 | predict_val [i] = ifetch_ack [x][y] // and decod_val [i] |
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125 | ; |
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126 | decod_val [i] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable |
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127 | ifetch_ack [x][y] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack |
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128 | |
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129 | if (_param->_have_port_context_id) |
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130 | PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x); |
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131 | PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0)); |
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132 | PORT_WRITE(out_PREDICT_BRANCH_STATE [i],PORT_READ(in_IFETCH_BRANCH_STATE [x])); |
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133 | if (_param->_have_port_branch_update_prediction_id) |
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134 | PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x])); |
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135 | PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],_decod_instruction->_branch_condition ); |
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136 | // PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write); |
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137 | PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction ); |
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138 | PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],_decod_instruction->_address ); |
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139 | PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],_decod_instruction->_address_next ); |
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140 | |
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141 | //can_continue_next [x] = PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // can continue is set if direction is "not take" (also, continue is sequential order) |
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142 | can_continue_next [x] = false; // one branch per context |
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143 | } |
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144 | |
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145 | Tevent_type_t event_type = _decod_instruction->_event_type; |
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146 | if (event_type != EVENT_TYPE_NONE) |
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147 | { |
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148 | // speculative jump at the exception handler |
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149 | // if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE |
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150 | context_event_val = ifetch_ack [x][y] // and decod_val [i] |
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151 | ; |
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152 | decod_val [i] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable |
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153 | ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack |
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154 | |
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155 | if (_param->_have_port_context_id) |
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156 | PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID , x); |
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157 | PORT_WRITE(out_CONTEXT_EVENT_TYPE , _decod_instruction->_event_type ); |
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158 | PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, _decod_instruction->_is_delay_slot ); |
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159 | PORT_WRITE(out_CONTEXT_EVENT_ADDRESS , _decod_instruction->_address ); |
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160 | PORT_WRITE(out_CONTEXT_EVENT_ADDRESS_EPCR , _decod_instruction->_address_next ); |
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161 | } |
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162 | |
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163 | // fetch_ack = |
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164 | // ((event_type == EVENT_TYPE_NONE) or ((event_type != EVENT_TYPE_NONE) and context_event_ack)) and |
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165 | // ((type == TYPE_BRANCH ) or ((type != TYPE_BRANCH ) and predict_ack )) and |
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166 | // fetch_val and decod_ack and decod_enable and true (is decod_val) |
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167 | |
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168 | // To compute the "next previous" address |
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169 | Tcontrol_t have_transaction = ifetch_ack [x][y]; |
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170 | |
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171 | internal_CONTEXT_HAVE_TRANSACTION [x] |= have_transaction; |
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172 | if (have_transaction) |
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173 | { |
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174 | #ifdef STATISTICS |
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175 | (*_stat_sum_inst_decod) ++; |
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176 | #endif |
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177 | internal_CONTEXT_ADDRESS_PREVIOUS [x] = addr; |
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178 | internal_CONTEXT_IS_DELAY_SLOT [x] = (type == TYPE_BRANCH); // next is a delay slot if current have branch type |
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179 | } |
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180 | |
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181 | can_continue [x] &= have_transaction; // to have a in order decod !!! if a previous instruction can decod, also next instruction can't decod. |
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182 | } |
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183 | |
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184 | it ++; |
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185 | } |
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186 | } |
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187 | |
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188 | //----------------------------------- |
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189 | // Write output |
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190 | //----------------------------------- |
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191 | |
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192 | for (uint32_t i=0; i<_param->_nb_context; i++) |
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193 | for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++) |
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194 | PORT_WRITE(out_IFETCH_ACK [i][j], ifetch_ack [i][j]); |
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195 | |
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196 | PORT_WRITE(out_CONTEXT_EVENT_VAL, context_event_val); |
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197 | |
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198 | for (uint32_t i=0; i<_param->_nb_inst_decod; i++) |
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199 | { |
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200 | PORT_WRITE(out_PREDICT_VAL [i], predict_val [i]); |
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201 | PORT_WRITE(out_DECOD_VAL [i], decod_val [i]); |
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202 | } |
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203 | |
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204 | log_printf(FUNC,Decod,FUNCTION,"End"); |
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205 | }; |
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206 | |
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207 | }; // end namespace decod |
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208 | }; // end namespace decod_unit |
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209 | }; // end namespace front_end |
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210 | }; // end namespace multi_front_end |
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211 | }; // end namespace core |
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212 | |
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213 | }; // end namespace behavioural |
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214 | }; // end namespace morpheo |
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215 | #endif |
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