Context Navigation

source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp @ 101

Last change on this file since 101 was 101, checked in by rosiere, 15 years ago
1) Add soc test 2) fix bug (Pc management, Decod and execute, Update prediction ...)
Property svn:keywords set to `Id`
File size: 12.5 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Decod_genMealy.cpp 101 2009-01-15 17:19:08Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/include/Decod.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace decod_unit {
17	namespace decod {
18
19
20	#undef FUNCTION
21	#define FUNCTION "Decod::genMealy"
22	void Decod::genMealy (void)
23	{
24	log_begin(Decod,FUNCTION);
25	log_function(Decod,FUNCTION,_name.c_str());
26
27	//-----------------------------------
28	// Initialization
29	//-----------------------------------
30	Tcontrol_t context_event_val = false;
31	Tcontrol_t ifetch_ack [_param->_nb_context][_param->_max_nb_inst_fetch];
32	for (uint32_t i=0; i<_param->_nb_context; i++)
33	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
34	ifetch_ack [i][j] = false;
35
36	Tcontrol_t predict_val [_param->_nb_inst_decod];
37	Tcontrol_t decod_val [_param->_nb_inst_decod];
38	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
39	{
40	decod_val [i] = false;
41	predict_val [i] = false;
42	}
43
44	Tcontrol_t can_continue [_param->_nb_context];
45	Tcontrol_t can_continue_next [_param->_nb_context];
46
47	for (uint32_t i=0; i<_param->_nb_context; i++)
48	{
49	internal_CONTEXT_HAVE_TRANSACTION [i] = false;
50	internal_CONTEXT_ADDRESS_PREVIOUS [i] = reg_CONTEXT_ADDRESS_PREVIOUS [i];
51	internal_CONTEXT_IS_DELAY_SLOT [i] = reg_CONTEXT_IS_DELAY_SLOT [i];
52
53	can_continue [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]);
54	can_continue_next [i] = PORT_READ(in_CONTEXT_DECOD_ENABLE [i]);
55	}
56
57	//-----------------------------------
58	// Loop of decod
59	//-----------------------------------
60	// scan all decod "slot_out"
61	std::list<generic::priority::select_t> * select = _priority->select();
62	std::list<generic::priority::select_t>::iterator it=select->begin();
63	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
64	{
65	while ((it != select->end()) and // have a no scanned "slot_in" ?
66	(decod_val [i] == false) and // have not a previous selected entry?
67	(context_event_val == false)) // Have not a context_event (spr_access, exception, ...)
68	{
69	predict_val [i] = false;
70
71	Tcontext_t x = it->grp;
72	uint32_t y = it->elt;
73
74	// Test if this instruction is valid
75	if ((PORT_READ(in_IFETCH_VAL [x][y]) == 1) and // entry is valid
76	(can_continue [x] == 1)) // context can decod instruction (have not a previous event)
77	{
78	log_printf(TRACE,Decod,FUNCTION," * IFETCH [%d][%d]",x,y);
79	log_printf(TRACE,Decod,FUNCTION," * decod_ack [%d] : %d",i,PORT_READ(in_DECOD_ACK [i]));
80
81	can_continue [x] = can_continue_next [x];
82
83	decod_val [i] = true; // fetch_val and decod_enable
84	ifetch_ack [x][y] = PORT_READ(in_DECOD_ACK [i]); // fetch_val and decod_enable and decod_ack
85
86	Tgeneral_data_t addr = PORT_READ(in_IFETCH_ADDRESS [x])+y;
87
88	_decod_instruction->_instruction = PORT_READ(in_IFETCH_INSTRUCTION [x][y]);
89	_decod_instruction->_context_id = x;
90	_decod_instruction->_address_previous = internal_CONTEXT_ADDRESS_PREVIOUS [x];
91	_decod_instruction->_address = addr; //Compute the current address
92	_decod_instruction->_address_next = addr+1;
93	_decod_instruction->_is_delay_slot = internal_CONTEXT_IS_DELAY_SLOT [x];
94
95	// Test IFetch exception
96	Texception_t ifetch_exception = PORT_READ(in_IFETCH_EXCEPTION [x]);
97
98	if (ifetch_exception == EXCEPTION_IFETCH_NONE)
99	{
100	// Decod !
101	log_printf(TRACE,Decod,FUNCTION," * DECOD [%d]",i);
102	log_printf(TRACE,Decod,FUNCTION," * context : %d",x);
103	log_printf(TRACE,Decod,FUNCTION," * fetch : %d",y);
104	log_printf(TRACE,Decod,FUNCTION," * address : %.8x (%.8x)",addr,(addr<<2));
105	log_printf(TRACE,Decod,FUNCTION," * is_delay_slot : %d",internal_CONTEXT_IS_DELAY_SLOT [x]);
106
107	instruction_decod (_decod_instruction, _decod_param[x]);
108	}
109	else
110	{
111	// No decod : nop
112	instruction_l_nop (_decod_instruction, _decod_param[x]);
113
114	_decod_instruction->_exception_use = EXCEPTION_USE_NONE;
115	_decod_instruction->_exception = exception_ifetch_to_exception_decod(ifetch_exception);
116
117	// INSTRUCTION_TLB
118	// INSTRUCTION_PAGE
119	// BUS_ERROR
120	if (_decod_instruction->_is_delay_slot)
121	_decod_instruction->_address_next = _decod_instruction->_address_previous;
122	else
123	_decod_instruction->_address_next = _decod_instruction->_address;
124
125	_decod_instruction->_event_type = EVENT_TYPE_EXCEPTION;
126	}
127
128	Ttype_t type = _decod_instruction->_type;
129	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_CONTEXT_DEPTH [x]):0; // DEPTH_CURRENT
130
131	if (_param->_have_port_context_id)
132	PORT_WRITE(out_DECOD_CONTEXT_ID [i], x);
133	if (_param->_have_port_depth)
134	PORT_WRITE(out_DECOD_DEPTH [i], depth);
135	PORT_WRITE(out_DECOD_TYPE [i], type);
136	PORT_WRITE(out_DECOD_OPERATION [i], _decod_instruction->_operation );
137	PORT_WRITE(out_DECOD_NO_EXECUTE [i], _decod_instruction->_no_execute );
138	PORT_WRITE(out_DECOD_IS_DELAY_SLOT [i], _decod_instruction->_is_delay_slot );
139	PORT_WRITE(out_DECOD_ADDRESS [i], addr);
140	PORT_WRITE(out_DECOD_HAS_IMMEDIAT [i], _decod_instruction->_has_immediat );
141	PORT_WRITE(out_DECOD_IMMEDIAT [i], _decod_instruction->_immediat );
142	PORT_WRITE(out_DECOD_READ_RA [i], _decod_instruction->_read_ra );
143	PORT_WRITE(out_DECOD_NUM_REG_RA [i], _decod_instruction->_num_reg_ra );
144	PORT_WRITE(out_DECOD_READ_RB [i], _decod_instruction->_read_rb );
145	PORT_WRITE(out_DECOD_NUM_REG_RB [i], _decod_instruction->_num_reg_rb );
146	PORT_WRITE(out_DECOD_READ_RC [i], _decod_instruction->_read_rc );
147	PORT_WRITE(out_DECOD_NUM_REG_RC [i], _decod_instruction->_num_reg_rc );
148	PORT_WRITE(out_DECOD_WRITE_RD [i],(_decod_instruction->_num_reg_rd!=0)?_decod_instruction->_write_rd:0);
149	PORT_WRITE(out_DECOD_NUM_REG_RD [i], _decod_instruction->_num_reg_rd );
150	PORT_WRITE(out_DECOD_WRITE_RE [i], _decod_instruction->_write_re );
151	PORT_WRITE(out_DECOD_NUM_REG_RE [i], _decod_instruction->_num_reg_re );
152	PORT_WRITE(out_DECOD_EXCEPTION_USE [i], _decod_instruction->_exception_use );
153	// PORT_WRITE(out_DECOD_EXCEPTION [i], _decod_instruction->_exception );
154
155	// Branch predictor can accept : the depth is valid
156	log_printf(TRACE,Decod,FUNCTION," * context_depth_val : %d",PORT_READ(in_CONTEXT_DEPTH_VAL [x]));
157	decod_val [i] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]);
158	ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_DEPTH_VAL [x]);
159
160	if (type == TYPE_BRANCH)
161	{
162	log_printf(TRACE,Decod,FUNCTION," * type is branch");
163	log_printf(TRACE,Decod,FUNCTION," * predict_ack : %d",PORT_READ(in_PREDICT_ACK [i]));
164
165	log_printf(TRACE,Decod,FUNCTION," * address src : %.8x (%.8x)",_decod_instruction->_address ,_decod_instruction->_address <<2);
166	log_printf(TRACE,Decod,FUNCTION," * address dest : %.8x (%.8x)",_decod_instruction->_address_next,_decod_instruction->_address_next<<2);
167
168	predict_val [i] = ifetch_ack [x][y] // and decod_val [i]
169	;
170	decod_val [i] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable
171	ifetch_ack [x][y] &= PORT_READ(in_PREDICT_ACK [i]);// predict_ack and fetch_val and decod_enable and decod_ack
172
173	if (_param->_have_port_context_id)
174	PORT_WRITE(out_PREDICT_CONTEXT_ID [i],x);
175	PORT_WRITE(out_PREDICT_MATCH_INST_IFETCH_PTR [i],y == ((_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_IFETCH_INST_IFETCH_PTR [x]):0));
176	PORT_WRITE(out_PREDICT_BRANCH_STATE [i],PORT_READ(in_IFETCH_BRANCH_STATE [x]));
177	if (_param->_have_port_depth)
178	PORT_WRITE(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [i],PORT_READ(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [x]));
179	PORT_WRITE(out_PREDICT_BRANCH_CONDITION [i],_decod_instruction->_branch_condition );
180	// PORT_WRITE(out_PREDICT_BRANCH_STACK_WRITE [i],_decod_instruction->_branch_stack_write);
181	PORT_WRITE(out_PREDICT_BRANCH_DIRECTION [i],_decod_instruction->_branch_direction );
182	PORT_WRITE(out_PREDICT_ADDRESS_SRC [i],_decod_instruction->_address );
183	PORT_WRITE(out_PREDICT_ADDRESS_DEST [i],_decod_instruction->_address_next );
184
185	//can_continue_next [x] = PORT_READ(in_PREDICT_CAN_CONTINUE [i]); // can continue is set if direction is "not take" (also, continue is sequential order)
186	can_continue_next [x] = false; // one branch per context, the DS don't execute
187	}
188
189	Tevent_type_t event_type = _decod_instruction->_event_type;
190	if (event_type != EVENT_TYPE_NONE)
191	{
192	// speculative jump at the exception handler
193	// if type = TYPE_BRANCH, also event_type == EVENT_TYPE_NONE
194	context_event_val = ifetch_ack [x][y] // and decod_val [i]
195	;
196	decod_val [i] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable
197	ifetch_ack [x][y] &= PORT_READ(in_CONTEXT_EVENT_ACK);// context_event_ack and fetch_val and decod_enable and decod_ack
198
199	if (_param->_have_port_context_id)
200	PORT_WRITE(out_CONTEXT_EVENT_CONTEXT_ID , x);
201	if (_param->_have_port_depth)
202	PORT_WRITE(out_CONTEXT_EVENT_DEPTH , depth);
203	PORT_WRITE(out_CONTEXT_EVENT_TYPE , _decod_instruction->_event_type );
204	PORT_WRITE(out_CONTEXT_EVENT_IS_DELAY_SLOT, _decod_instruction->_is_delay_slot );
205	PORT_WRITE(out_CONTEXT_EVENT_ADDRESS , _decod_instruction->_address );
206	PORT_WRITE(out_CONTEXT_EVENT_ADDRESS_EPCR , _decod_instruction->_address_next );
207	}
208
209	// fetch_ack =
210	// ((event_type == EVENT_TYPE_NONE) or ((event_type != EVENT_TYPE_NONE) and context_event_ack)) and
211	// ((type == TYPE_BRANCH ) or ((type != TYPE_BRANCH ) and predict_ack )) and
212	// fetch_val and decod_ack and decod_enable and true (is decod_val)
213
214	// To compute the "next previous" address
215	Tcontrol_t have_transaction = ifetch_ack [x][y];
216
217	internal_CONTEXT_HAVE_TRANSACTION [x] \|= have_transaction;
218	if (have_transaction)
219	{
220	internal_CONTEXT_ADDRESS_PREVIOUS [x] = addr;
221	internal_CONTEXT_IS_DELAY_SLOT [x] = (type == TYPE_BRANCH); // next is a delay slot if current have branch type
222	}
223
224	can_continue [x] &= have_transaction; // to have a in order decod !!! if a previous instruction can decod, also next instruction can't decod.
225	}
226
227	log_printf(TRACE,Decod,FUNCTION," - num_(decod, context, fetch) : %d %d %d",i, x, y);
228	log_printf(TRACE,Decod,FUNCTION," - ifetch_ack : %d",ifetch_ack [x][y]);
229	log_printf(TRACE,Decod,FUNCTION," - context_event_val : %d",context_event_val );
230	log_printf(TRACE,Decod,FUNCTION," - predict_val : %d",predict_val [i] );
231	log_printf(TRACE,Decod,FUNCTION," - decod_val : %d",decod_val [i] );
232
233	it ++;
234	}
235	}
236	//-----------------------------------
237	// Write output
238	//-----------------------------------
239
240	for (uint32_t i=0; i<_param->_nb_context; i++)
241	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
242	PORT_WRITE(out_IFETCH_ACK [i][j], ifetch_ack [i][j]);
243
244	PORT_WRITE(out_CONTEXT_EVENT_VAL, context_event_val);
245
246	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
247	{
248	PORT_WRITE(out_PREDICT_VAL [i], predict_val [i]);
249	PORT_WRITE(out_DECOD_VAL [i], decod_val [i]);
250
251	#ifdef STATISTICS
252	internal_DECOD_VAL [i] = decod_val [i];
253	#endif
254	}
255
256	log_end(Decod,FUNCTION);
257	};
258
259	}; // end namespace decod
260	}; // end namespace decod_unit
261	}; // end namespace front_end
262	}; // end namespace multi_front_end
263	}; // end namespace core
264
265	}; // end namespace behavioural
266	}; // end namespace morpheo
267	#endif

Note: See TracBrowser for help on using the repository browser.

Download in other formats: