source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/src/Decod_queue_function_one_fifo_genMoore.cpp @ 111

Last change on this file since 111 was 111, checked in by rosiere, 15 years ago

1) Decod_queue : multi implementation (one_fifo, multi_fifo)
2) Issue_queue : multi implementation (in_order, out_of_order)
3) Direction : Add Meta predictor
4) Context_State : re add Branch_complete, More priority to Load miss (is not speculative)
5) Return_Address_Stack : update reg_PREDICT pointer on decod miss prediction
6) UPT : Fix bug in multi event
7) Prediction_glue : in read_stack case, insert in UPT pc_next
8) Rename select : when rob have an event (need flush), read_r{a,b,c} and write_r{d,e} is set at 0
  • Property svn:keywords set to Id
File size: 4.1 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id: Decod_queue_function_one_fifo_genMoore.cpp 111 2009-02-27 18:37:40Z rosiere $
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod_queue/include/Decod_queue.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace decod_unit {
17namespace decod_queue {
18
19
20#undef  FUNCTION
21#define FUNCTION "Decod_queue::function_one_fifo_genMoore"
22  void Decod_queue::function_one_fifo_genMoore (void)
23  {
24    log_begin(Decod_queue,FUNCTION);
25    log_function(Decod_queue,FUNCTION,_name.c_str());
26
27    //--------------------------------------------------------------------
28    //-----[ DECOD_IN ]---------------------------------------------------
29    //--------------------------------------------------------------------
30    {
31      Tcontrol_t ack = reg_QUEUE->size() < _param->_size_queue;
32
33      for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
34        {
35          internal_DECOD_IN_ACK [i] = ack;
36          PORT_WRITE(out_DECOD_IN_ACK [i],ack);
37        }
38    }
39
40    //--------------------------------------------------------------------
41    //-----[ DECOD_OUT ]--------------------------------------------------
42    //--------------------------------------------------------------------
43    if (not reg_QUEUE->empty())
44      for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
45        {
46          uint32_t index = reg_LAST_SLOT + i;
47
48          // Stop
49          if (index >= _param->_nb_inst_decod)
50            break;
51
52          if (_param->_have_port_context_id)
53          PORT_WRITE(out_DECOD_OUT_CONTEXT_ID    [i],reg_QUEUE->front()->_context_id    [index]);
54          if (_param->_have_port_depth)
55          PORT_WRITE(out_DECOD_OUT_DEPTH         [i],reg_QUEUE->front()->_depth         [index]);
56          PORT_WRITE(out_DECOD_OUT_TYPE          [i],reg_QUEUE->front()->_type          [index]);
57          PORT_WRITE(out_DECOD_OUT_OPERATION     [i],reg_QUEUE->front()->_operation     [index]);
58          PORT_WRITE(out_DECOD_OUT_NO_EXECUTE    [i],reg_QUEUE->front()->_no_execute    [index]);
59          PORT_WRITE(out_DECOD_OUT_IS_DELAY_SLOT [i],reg_QUEUE->front()->_is_delay_slot [index]);
60#ifdef DEBUG
61          PORT_WRITE(out_DECOD_OUT_ADDRESS       [i],reg_QUEUE->front()->_address       [index]);
62#endif
63          PORT_WRITE(out_DECOD_OUT_ADDRESS_NEXT  [i],reg_QUEUE->front()->_address_next  [index]);
64          PORT_WRITE(out_DECOD_OUT_HAS_IMMEDIAT  [i],reg_QUEUE->front()->_has_immediat  [index]);
65          PORT_WRITE(out_DECOD_OUT_IMMEDIAT      [i],reg_QUEUE->front()->_immediat      [index]);
66          PORT_WRITE(out_DECOD_OUT_READ_RA       [i],reg_QUEUE->front()->_read_ra       [index]);
67          PORT_WRITE(out_DECOD_OUT_NUM_REG_RA    [i],reg_QUEUE->front()->_num_reg_ra    [index]);
68          PORT_WRITE(out_DECOD_OUT_READ_RB       [i],reg_QUEUE->front()->_read_rb       [index]);
69          PORT_WRITE(out_DECOD_OUT_NUM_REG_RB    [i],reg_QUEUE->front()->_num_reg_rb    [index]);
70          PORT_WRITE(out_DECOD_OUT_READ_RC       [i],reg_QUEUE->front()->_read_rc       [index]);
71          PORT_WRITE(out_DECOD_OUT_NUM_REG_RC    [i],reg_QUEUE->front()->_num_reg_rc    [index]);
72          PORT_WRITE(out_DECOD_OUT_WRITE_RD      [i],reg_QUEUE->front()->_write_rd      [index]);
73          PORT_WRITE(out_DECOD_OUT_NUM_REG_RD    [i],reg_QUEUE->front()->_num_reg_rd    [index]);
74          PORT_WRITE(out_DECOD_OUT_WRITE_RE      [i],reg_QUEUE->front()->_write_re      [index]);
75          PORT_WRITE(out_DECOD_OUT_NUM_REG_RE    [i],reg_QUEUE->front()->_num_reg_re    [index]);
76          PORT_WRITE(out_DECOD_OUT_EXCEPTION_USE [i],reg_QUEUE->front()->_exception_use [index]);
77          PORT_WRITE(out_DECOD_OUT_EXCEPTION     [i],reg_QUEUE->front()->_exception     [index]);
78        }
79
80    //--------------------------------------------------------------------
81    //-----[ NB_INST ]----------------------------------------------------
82    //--------------------------------------------------------------------
83    for (uint32_t i=0; i<_param->_nb_context; i++)
84      PORT_WRITE(out_NB_INST_ALL [i], reg_NB_INST [i]);
85
86    log_end(Decod_queue,FUNCTION);
87  };
88
89}; // end namespace decod_queue
90}; // end namespace decod_unit
91}; // end namespace front_end
92}; // end namespace multi_front_end
93}; // end namespace core
94
95}; // end namespace behavioural
96}; // end namespace morpheo             
97#endif
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