Context Navigation

test.cpp @ 117

Last change on this file since 117 was 117, checked in by rosiere, 15 years ago
1) Platforms : add new organization for test 2) Load_Store_Unit : add array to count nb_check in store_queue 3) Issue_queue and Core_Glue : rewrite the issue network 4) Special_Register_Unit : add reset value to register CID 5) Softwares : add multicontext test 6) Softwares : add SPECINT 7) Softwares : add MiBench? 7) Read_queue : inhib access for r0 8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
Property svn:keywords set to `Id`
File size: 36.4 KB

Line
1	/*
2	* $Id: test.cpp 117 2009-05-16 14:42:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (10240*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/include/test.h"
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/SelfTest/include/Decod_request.h"
14	#include "Common/include/Test.h"
15	#include "Behavioural/include/Allocation.h"
16
17	void test (string name,
18	morpheo::behavioural::core::multi_front_end::front_end::decod_unit::Parameters * _param)
19	{
20	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
21
22	#ifdef STATISTICS
23	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
24	#endif
25
26	Tusage_t _usage = USE_ALL;
27
28	// _usage = usage_unset(_usage,USE_SYSTEMC );
29	// _usage = usage_unset(_usage,USE_VHDL );
30	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
31	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
32	// _usage = usage_unset(_usage,USE_POSITION );
33	// _usage = usage_unset(_usage,USE_STATISTICS );
34	// _usage = usage_unset(_usage,USE_INFORMATION );
35
36	Decod_unit * _Decod_unit = new Decod_unit
37	(name.c_str(),
38	#ifdef STATISTICS
39	_parameters_statistics,
40	#endif
41	_param,
42	_usage);
43
44	#ifdef SYSTEMC
45	if (usage_is_set(_usage,USE_SYSTEMC))
46	{
47	/*********************************************************************
48	* Déclarations des signaux
49	*********************************************************************/
50	string rename;
51
52	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
53	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
54
55	sc_signal<Tcontrol_t > *** in_IFETCH_VAL ;
56	sc_signal<Tcontrol_t > *** out_IFETCH_ACK ;
57	sc_signal<Tinstruction_t > *** in_IFETCH_INSTRUCTION ;
58
59	sc_signal<Tcontext_t > ** in_IFETCH_CONTEXT_ID ;
60	sc_signal<Tgeneral_address_t > ** in_IFETCH_ADDRESS ;
61	//sc_signal<Tgeneral_address_t > ** in_IFETCH_ADDRESS_NEXT ;
62	sc_signal<Tinst_ifetch_ptr_t > ** in_IFETCH_INST_IFETCH_PTR ;
63	sc_signal<Tbranch_state_t > ** in_IFETCH_BRANCH_STATE ;
64	sc_signal<Tprediction_ptr_t > ** in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ;
65	sc_signal<Texception_t > ** in_IFETCH_EXCEPTION ;
66
67	sc_signal<Tcontrol_t > ** out_DECOD_VAL ;
68	sc_signal<Tcontrol_t > ** in_DECOD_ACK ;
69	sc_signal<Tcontext_t > ** out_DECOD_CONTEXT_ID ;
70	sc_signal<Tdepth_t > ** out_DECOD_DEPTH ;
71	sc_signal<Ttype_t > ** out_DECOD_TYPE ;
72	sc_signal<Toperation_t > ** out_DECOD_OPERATION ;
73	sc_signal<Tcontrol_t > ** out_DECOD_NO_EXECUTE ;
74	sc_signal<Tcontrol_t > ** out_DECOD_IS_DELAY_SLOT ;
75	sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS ;
76
77	sc_signal<Tgeneral_data_t > ** out_DECOD_ADDRESS_NEXT ;
78	sc_signal<Tcontrol_t > ** out_DECOD_HAS_IMMEDIAT ;
79	sc_signal<Tgeneral_data_t > ** out_DECOD_IMMEDIAT ;
80	sc_signal<Tcontrol_t > ** out_DECOD_READ_RA ;
81	sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RA ;
82	sc_signal<Tcontrol_t > ** out_DECOD_READ_RB ;
83	sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RB ;
84	sc_signal<Tcontrol_t > ** out_DECOD_READ_RC ;
85	sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RC ;
86	sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RD ;
87	sc_signal<Tgeneral_address_t > ** out_DECOD_NUM_REG_RD ;
88	sc_signal<Tcontrol_t > ** out_DECOD_WRITE_RE ;
89	sc_signal<Tspecial_address_t > ** out_DECOD_NUM_REG_RE ;
90	sc_signal<Texception_t > ** out_DECOD_EXCEPTION_USE ;
91	sc_signal<Texception_t > ** out_DECOD_EXCEPTION ;
92
93	sc_signal<Tcontrol_t > ** out_PREDICT_VAL ;
94	sc_signal<Tcontrol_t > ** in_PREDICT_ACK ;
95	sc_signal<Tcontext_t > ** out_PREDICT_CONTEXT_ID ;
96	sc_signal<Tcontrol_t > ** out_PREDICT_MATCH_INST_IFETCH_PTR ;
97	sc_signal<Tbranch_state_t > ** out_PREDICT_BRANCH_STATE ;
98	sc_signal<Tprediction_ptr_t > ** out_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
99	sc_signal<Tbranch_condition_t> ** out_PREDICT_BRANCH_CONDITION ;
100	//sc_signal<Tcontrol_t > ** out_PREDICT_BRANCH_STACK_WRITE ;
101	sc_signal<Tcontrol_t > ** out_PREDICT_BRANCH_DIRECTION ;
102	sc_signal<Tgeneral_data_t > ** out_PREDICT_ADDRESS_SRC ;
103	sc_signal<Tgeneral_data_t > ** out_PREDICT_ADDRESS_DEST ;
104	sc_signal<Tcontrol_t > ** in_PREDICT_CAN_CONTINUE ;
105
106	sc_signal<Tdepth_t > ** in_DEPTH_MIN ;
107	sc_signal<Tdepth_t > ** in_DEPTH_MAX ;
108	sc_signal<Tcontrol_t > ** in_DEPTH_FULL ;
109
110	sc_signal<Tcounter_t > ** out_NB_INST_DECOD_ALL ;
111
112	sc_signal<Tcontrol_t > ** in_CONTEXT_DECOD_ENABLE ;
113	sc_signal<Tcontrol_t > ** in_CONTEXT_DEPTH_VAL ;
114	sc_signal<Tdepth_t > ** in_CONTEXT_DEPTH ;
115
116	sc_signal<Tcontrol_t > * out_CONTEXT_EVENT_VAL ;
117	sc_signal<Tcontrol_t > * in_CONTEXT_EVENT_ACK ;
118	sc_signal<Tcontext_t > * out_CONTEXT_EVENT_CONTEXT_ID ;
119	sc_signal<Tdepth_t > * out_CONTEXT_EVENT_DEPTH ;
120	sc_signal<Tevent_type_t > * out_CONTEXT_EVENT_TYPE ;
121	sc_signal<Tcontrol_t > * out_CONTEXT_EVENT_IS_DELAY_SLOT ;
122	sc_signal<Tgeneral_data_t > * out_CONTEXT_EVENT_ADDRESS ;
123	sc_signal<Tgeneral_data_t > * out_CONTEXT_EVENT_ADDRESS_EPCR ;
124
125
126
127	ALLOC2_SC_SIGNAL( in_IFETCH_VAL ," in_IFETCH_VAL ",Tcontrol_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]);
128	ALLOC2_SC_SIGNAL(out_IFETCH_ACK ,"out_IFETCH_ACK ",Tcontrol_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]);
129	ALLOC2_SC_SIGNAL( in_IFETCH_INSTRUCTION ," in_IFETCH_INSTRUCTION ",Tinstruction_t ,_param->_nb_context, _param->_nb_inst_fetch[it1]);
130
131	ALLOC1_SC_SIGNAL(in_IFETCH_CONTEXT_ID ,"in_IFETCH_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
132	ALLOC1_SC_SIGNAL(in_IFETCH_ADDRESS ,"in_IFETCH_ADDRESS ",Tgeneral_address_t ,_param->_nb_context);
133	//ALLOC1_SC_SIGNAL(in_IFETCH_ADDRESS_NEXT ,"in_IFETCH_ADDRESS_NEXT ",Tgeneral_address_t ,_param->_nb_context);
134	ALLOC1_SC_SIGNAL(in_IFETCH_INST_IFETCH_PTR ,"in_IFETCH_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ,_param->_nb_context);
135	ALLOC1_SC_SIGNAL(in_IFETCH_BRANCH_STATE ,"in_IFETCH_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_context);
136	ALLOC1_SC_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,"in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_context);
137	ALLOC1_SC_SIGNAL(in_IFETCH_EXCEPTION ,"in_IFETCH_EXCEPTION ",Texception_t ,_param->_nb_context);
138
139	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
140	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
141	ALLOC1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,"out_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
142	ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
143	ALLOC1_SC_SIGNAL(out_DECOD_TYPE ,"out_DECOD_TYPE ",Ttype_t ,_param->_nb_inst_decod);
144	ALLOC1_SC_SIGNAL(out_DECOD_OPERATION ,"out_DECOD_OPERATION ",Toperation_t ,_param->_nb_inst_decod);
145	ALLOC1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,"out_DECOD_NO_EXECUTE ",Tcontrol_t ,_param->_nb_inst_decod);
146	ALLOC1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,"out_DECOD_IS_DELAY_SLOT ",Tcontrol_t ,_param->_nb_inst_decod);
147	#ifdef DEBUG
148	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_data_t ,_param->_nb_inst_decod);
149	#endif
150	ALLOC1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,"out_DECOD_ADDRESS_NEXT ",Tgeneral_data_t ,_param->_nb_inst_decod);
151	ALLOC1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,"out_DECOD_HAS_IMMEDIAT ",Tcontrol_t ,_param->_nb_inst_decod);
152	ALLOC1_SC_SIGNAL(out_DECOD_IMMEDIAT ,"out_DECOD_IMMEDIAT ",Tgeneral_data_t ,_param->_nb_inst_decod);
153	ALLOC1_SC_SIGNAL(out_DECOD_READ_RA ,"out_DECOD_READ_RA ",Tcontrol_t ,_param->_nb_inst_decod);
154	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,"out_DECOD_NUM_REG_RA ",Tgeneral_address_t ,_param->_nb_inst_decod);
155	ALLOC1_SC_SIGNAL(out_DECOD_READ_RB ,"out_DECOD_READ_RB ",Tcontrol_t ,_param->_nb_inst_decod);
156	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,"out_DECOD_NUM_REG_RB ",Tgeneral_address_t ,_param->_nb_inst_decod);
157	ALLOC1_SC_SIGNAL(out_DECOD_READ_RC ,"out_DECOD_READ_RC ",Tcontrol_t ,_param->_nb_inst_decod);
158	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,"out_DECOD_NUM_REG_RC ",Tspecial_address_t ,_param->_nb_inst_decod);
159	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RD ,"out_DECOD_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_decod);
160	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,"out_DECOD_NUM_REG_RD ",Tgeneral_address_t ,_param->_nb_inst_decod);
161	ALLOC1_SC_SIGNAL(out_DECOD_WRITE_RE ,"out_DECOD_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_decod);
162	ALLOC1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,"out_DECOD_NUM_REG_RE ",Tspecial_address_t ,_param->_nb_inst_decod);
163	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,"out_DECOD_EXCEPTION_USE ",Texception_t ,_param->_nb_inst_decod);
164	ALLOC1_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Texception_t ,_param->_nb_inst_decod);
165
166	ALLOC1_SC_SIGNAL(out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
167	ALLOC1_SC_SIGNAL( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
168	ALLOC1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,"out_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
169	ALLOC1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,"out_PREDICT_MATCH_INST_IFETCH_PTR ",Tcontrol_t ,_param->_nb_inst_decod);
170	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,"out_PREDICT_BRANCH_STATE ",Tbranch_state_t ,_param->_nb_inst_decod);
171	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"out_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ,_param->_nb_inst_decod);
172	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,"out_PREDICT_BRANCH_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
173	//ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,"out_PREDICT_BRANCH_STACK_WRITE ",Tcontrol_t ,_param->_nb_inst_decod);
174	ALLOC1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,"out_PREDICT_BRANCH_DIRECTION ",Tcontrol_t ,_param->_nb_inst_decod);
175	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,"out_PREDICT_ADDRESS_SRC ",Tgeneral_data_t ,_param->_nb_inst_decod);
176	ALLOC1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,"out_PREDICT_ADDRESS_DEST ",Tgeneral_data_t ,_param->_nb_inst_decod);
177	ALLOC1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ," in_PREDICT_CAN_CONTINUE ",Tcontrol_t ,_param->_nb_inst_decod);
178
179	ALLOC1_SC_SIGNAL( in_DEPTH_MIN ," in_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
180	ALLOC1_SC_SIGNAL( in_DEPTH_MAX ," in_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
181	ALLOC1_SC_SIGNAL( in_DEPTH_FULL ," in_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
182
183	ALLOC1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,"out_NB_INST_DECOD_ALL ",Tcounter_t ,_param->_nb_context);
184
185	ALLOC1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ," in_CONTEXT_DECOD_ENABLE ",Tcontrol_t ,_param->_nb_context);
186	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ," in_CONTEXT_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
187	ALLOC1_SC_SIGNAL( in_CONTEXT_DEPTH ," in_CONTEXT_DEPTH ",Tdepth_t ,_param->_nb_context);
188
189	ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_VAL ,"out_CONTEXT_EVENT_VAL ",Tcontrol_t );
190	ALLOC0_SC_SIGNAL( in_CONTEXT_EVENT_ACK ," in_CONTEXT_EVENT_ACK ",Tcontrol_t );
191	ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_CONTEXT_ID ,"out_CONTEXT_EVENT_CONTEXT_ID ",Tcontext_t );
192	ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_DEPTH ,"out_CONTEXT_EVENT_DEPTH ",Tdepth_t );
193	ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_TYPE ,"out_CONTEXT_EVENT_TYPE ",Tevent_type_t );
194	ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_IS_DELAY_SLOT ,"out_CONTEXT_EVENT_IS_DELAY_SLOT ",Tcontrol_t );
195	ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS ,"out_CONTEXT_EVENT_ADDRESS ",Tgeneral_data_t );
196	ALLOC0_SC_SIGNAL( out_CONTEXT_EVENT_ADDRESS_EPCR ,"out_CONTEXT_EVENT_ADDRESS_EPCR ",Tgeneral_data_t );
197
198	/********************************************************
199	* Instanciation
200	********************************************************/
201
202	msg(_("<%s> : Instanciation of _Decod_unit.\n"),name.c_str());
203
204	((_Decod_unit->in_CLOCK)) ((in_CLOCK));
205	((_Decod_unit->in_NRESET)) ((in_NRESET));
206
207	INSTANCE2_SC_SIGNAL(_Decod_unit, in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[it1]);
208	INSTANCE2_SC_SIGNAL(_Decod_unit,out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[it1]);
209	INSTANCE2_SC_SIGNAL(_Decod_unit, in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[it1]);
210	if (_param->_have_port_context_id)
211	INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_CONTEXT_ID ,_param->_nb_context);
212	INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_ADDRESS ,_param->_nb_context);
213	//INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_ADDRESS_NEXT ,_param->_nb_context);
214
215	for (uint32_t i=0; i<_param->_nb_context; ++i)
216	{
217	if (_param->_have_port_inst_ifetch_ptr)
218	INSTANCE0_SC_SIGNAL(_Decod_unit,in_IFETCH_INST_IFETCH_PTR[i]);
219	if (_param->_have_port_depth)
220	INSTANCE0_SC_SIGNAL(_Decod_unit,in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]);
221	}
222
223	INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_BRANCH_STATE ,_param->_nb_context);
224	INSTANCE1_SC_SIGNAL(_Decod_unit,in_IFETCH_EXCEPTION ,_param->_nb_context);
225
226	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_VAL ,_param->_nb_inst_decod);
227	INSTANCE1_SC_SIGNAL(_Decod_unit, in_DECOD_ACK ,_param->_nb_inst_decod);
228	if (_param->_have_port_context_id)
229	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
230	if (_param->_have_port_depth)
231	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_DEPTH ,_param->_nb_inst_decod);
232	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_TYPE ,_param->_nb_inst_decod);
233	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_OPERATION ,_param->_nb_inst_decod);
234	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod);
235	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod);
236	#ifdef DEBUG
237	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS ,_param->_nb_inst_decod);
238	#endif
239	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod);
240	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod);
241	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_IMMEDIAT ,_param->_nb_inst_decod);
242	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_READ_RA ,_param->_nb_inst_decod);
243	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod);
244	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_READ_RB ,_param->_nb_inst_decod);
245	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod);
246	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_READ_RC ,_param->_nb_inst_decod);
247	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod);
248	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_WRITE_RD ,_param->_nb_inst_decod);
249	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod);
250	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_WRITE_RE ,_param->_nb_inst_decod);
251	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod);
252	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod);
253	INSTANCE1_SC_SIGNAL(_Decod_unit,out_DECOD_EXCEPTION ,_param->_nb_inst_decod);
254
255	INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_VAL ,_param->_nb_inst_decod);
256	INSTANCE1_SC_SIGNAL(_Decod_unit, in_PREDICT_ACK ,_param->_nb_inst_decod);
257	if (_param->_have_port_context_id)
258	INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod);
259	INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod);
260	INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod);
261	if (_param->_have_port_depth)
262	INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod);
263	INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod);
264	//INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod);
265	INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod);
266	INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod);
267	INSTANCE1_SC_SIGNAL(_Decod_unit,out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod);
268	INSTANCE1_SC_SIGNAL(_Decod_unit, in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);
269
270	if (_param->_have_port_depth)
271	{
272	INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_MIN ,_param->_nb_context);
273	INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_MAX ,_param->_nb_context);
274	}
275	INSTANCE1_SC_SIGNAL(_Decod_unit, in_DEPTH_FULL ,_param->_nb_context);
276	INSTANCE1_SC_SIGNAL(_Decod_unit,out_NB_INST_DECOD_ALL ,_param->_nb_context);
277
278	INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DECOD_ENABLE ,_param->_nb_context);
279
280	INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DEPTH_VAL ,_param->_nb_context);
281	if (_param->_have_port_depth)
282	INSTANCE1_SC_SIGNAL(_Decod_unit, in_CONTEXT_DEPTH ,_param->_nb_context);
283
284	INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_VAL );
285	INSTANCE0_SC_SIGNAL( _Decod_unit, in_CONTEXT_EVENT_ACK );
286	if (_param->_have_port_context_id)
287	INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_CONTEXT_ID );
288	if (_param->_have_port_depth)
289	INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_DEPTH );
290	INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_TYPE );
291	INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_IS_DELAY_SLOT );
292	INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS );
293	INSTANCE0_SC_SIGNAL( _Decod_unit,out_CONTEXT_EVENT_ADDRESS_EPCR );
294
295	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
296
297	Time * _time = new Time();
298
299	/********************************************************
300	* Simulation - Begin
301	********************************************************/
302
303	// Initialisation
304
305	const uint32_t seed = 0;
306	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
307
308	const int32_t percent_transaction_ifetch = 100;
309	const int32_t percent_transaction_decod = 100;
310	const int32_t percent_transaction_predict = 100;
311	const int32_t percent_transaction_event = 100;
312
313	srand(seed);
314
315	SC_START(0);
316	LABEL("Initialisation");
317
318	LABEL("Reset");
319	in_NRESET->write(0);
320	SC_START(5);
321	in_NRESET->write(1);
322
323	for (uint32_t i=0; i<_param->_nb_context; i++)
324	in_CONTEXT_DEPTH_VAL [i]->write(1);
325
326	LABEL("Loop of Test");
327
328	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
329	{
330	LABEL("Iteration %d",iteration);
331
332	Decod_request request [_param->_nb_context];
333	list<entry_t> respons [_param->_nb_context];
334
335	uint32_t nb_request = 0;
336
337	uint32_t delay_slot_previous [_param->_nb_context];
338	uint32_t delay_slot_current [_param->_nb_context];
339	uint32_t delay_slot_next [_param->_nb_context];
340
341	for (uint32_t i=0; i<_param->_nb_context; i++)
342	{
343	nb_request += request[i].size();
344	delay_slot_current [i] = false;
345	delay_slot_next [i] = false;
346
347	in_DEPTH_MIN [i]->write(0);
348	in_DEPTH_MAX [i]->write(0);
349	in_CONTEXT_DEPTH [i]->write(0);
350	}
351
352	while (nb_request > 0)
353	{
354	for (uint32_t i=0; i<_param->_nb_context; i++)
355	{
356	delay_slot_previous [i] = false;
357
358	in_CONTEXT_DECOD_ENABLE [i]->write((rand()%100)<percent_transaction_decod);
359
360	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
361	in_IFETCH_VAL [i][j]->write(0);
362
363	if ((rand()%100)<percent_transaction_ifetch)
364	{
365	list<entry_t>::iterator it = request[i].begin();
366
367	if (it!=request [i].end())
368	{
369	uint32_t lsb = it->_address%_param->_nb_inst_fetch[i];
370
371	in_IFETCH_ADDRESS [i]->write(it->_address-lsb);
372	in_IFETCH_BRANCH_STATE [i]->write(BRANCH_STATE_NONE);
373	if (_param->_have_port_inst_ifetch_ptr)
374	in_IFETCH_INST_IFETCH_PTR [i]->write(0);
375
376	// Alignement
377	for (uint32_t j=lsb; j<_param->_nb_inst_fetch[i]; j++)
378	{
379	in_IFETCH_VAL [i][j]->write(1);
380	in_IFETCH_INSTRUCTION [i][j]->write(it->_instruction);
381	// in_IFETCH_ADDRESS_NEXT [i]->write(it->_address_next);
382	if (it->_type == TYPE_BRANCH)
383	in_IFETCH_BRANCH_STATE [i]->write(it->_branch_state);
384	in_IFETCH_BRANCH_UPDATE_PREDICTION_ID [i]->write(it->_branch_update_prediction_id);
385	in_IFETCH_EXCEPTION [i]->write(it->_exception_ifetch);
386
387	if ((it->_is_delay_slot) or
388	((++it)==request [i].end()))
389	break;
390	}
391	}
392	}
393	}
394
395	{
396	bool previous_ack = true;
397
398	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
399	{
400	bool ack = previous_ack and ((rand()%100)<percent_transaction_decod);
401	in_DECOD_ACK [i]->write(ack);
402
403	previous_ack = ack;
404
405	in_PREDICT_ACK [i]->write((rand()%100)<percent_transaction_predict);
406	in_PREDICT_CAN_CONTINUE [i]->write(0);
407	}
408	}
409
410	in_CONTEXT_EVENT_ACK->write((rand()%100)<percent_transaction_event);
411
412	SC_START(0);
413
414	uint32_t find_event = false;
415	for (uint32_t i=0; i<_param->_nb_context; i++)
416	for (uint32_t j=0; j<_param->_nb_inst_fetch[i]; j++)
417	if (in_IFETCH_VAL[i][j]->read() and out_IFETCH_ACK[i][j]->read())
418	{
419	LABEL("IFETCH [%d][%d] : transaction",i,j);
420
421	entry_t entry = request [i].front();
422	LABEL(" * address 0x%x",entry._address);
423
424	respons [i].push_back(entry);
425	request [i].pop_front();
426
427	if (entry._type == TYPE_BRANCH)
428	{
429	delay_slot_next [i] = true;
430
431	// find good decod
432	uint32_t x;
433
434	for (x=0; x<=_param->_nb_inst_decod; x++)
435	{
436	if (x==_param->_nb_inst_decod)
437	TEST_KO("No find predict transaction");
438
439	Tcontext_t ctxt = (_param->_have_port_context_id)?out_PREDICT_CONTEXT_ID[x]->read():0;
440
441	if ((ctxt == i) and
442	(out_PREDICT_VAL [x]->read() and in_PREDICT_ACK [x]->read()))
443	break;
444	}
445
446	LABEL("PREDICT [%d] : transaction",x );
447
448
449	TEST(Tcontrol_t , out_PREDICT_MATCH_INST_IFETCH_PTR [x]->read(),((entry._address)%_param->_nb_inst_fetch[i]) == 0);
450	TEST(Tbranch_state_t , out_PREDICT_BRANCH_STATE [x]->read(), entry._branch_state );
451	if (_param->_have_port_depth)
452	TEST(Tprediction_ptr_t , out_PREDICT_BRANCH_UPDATE_PREDICTION_ID [x]->read(), entry._branch_update_prediction_id);
453	TEST(Tbranch_condition_t, out_PREDICT_BRANCH_CONDITION [x]->read(), entry._branch_condition );
454	// TEST(Tcontrol_t , out_PREDICT_BRANCH_STACK_WRITE [x]->read(), entry._branch_stack_write );
455	TEST(Tcontrol_t , out_PREDICT_BRANCH_DIRECTION [x]->read(), entry._branch_direction );
456	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_SRC [x]->read(), entry._address );
457	TEST(Tgeneral_data_t , out_PREDICT_ADDRESS_DEST [x]->read(), entry._branch_address_dest );
458	}
459
460	// TEST(bool, find_event, false); // can continue decod after event
461	if (entry._context_event_type != EVENT_TYPE_NONE)
462	{
463	find_event = true;
464
465	LABEL("CONTEXT_EVENT : transaction");
466
467	if (_param->_have_port_context_id)
468	TEST(Tcontext_t ,out_CONTEXT_EVENT_CONTEXT_ID ->read(), i);
469	if (_param->_have_port_depth)
470	TEST(Tcontext_t ,out_CONTEXT_EVENT_DEPTH ->read(), entry._depth);
471	TEST(Tevent_type_t ,out_CONTEXT_EVENT_TYPE ->read(), entry._context_event_type);
472	TEST(Tcontrol_t ,out_CONTEXT_EVENT_IS_DELAY_SLOT->read(), entry._is_delay_slot);
473	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS ->read(), entry._address );
474	TEST(Tgeneral_data_t,out_CONTEXT_EVENT_ADDRESS_EPCR ->read(), entry._address_next );
475	}
476
477	TEST(bool, delay_slot_previous [i], false); // can't continue
478	delay_slot_previous [i] = delay_slot_current [i];
479	delay_slot_current [i] = delay_slot_next [i];
480	delay_slot_next [i] = false;
481	}
482
483	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
484	if (out_DECOD_VAL[i]->read() and in_DECOD_ACK[i]->read())
485	{
486	Tcontext_t context = (_param->_have_port_context_id)?out_DECOD_CONTEXT_ID[i]->read():0;
487
488	LABEL("DECOD [%d] : transaction",i );
489
490	TEST(bool ,respons [context].empty(), false);
491
492	LABEL(" * context : %d",context);
493	LABEL(" * instruction : 0x%x",respons [context].front()._instruction);
494
495	if (_param->_have_port_depth)
496	TEST(Tdepth_t , out_DECOD_DEPTH [i]->read(), respons [context].front()._depth );
497	TEST(Ttype_t , out_DECOD_TYPE [i]->read(), respons [context].front()._type );
498	TEST(Toperation_t , out_DECOD_OPERATION [i]->read(), respons [context].front()._operation );
499	// TEST(Tcontrol_t , out_DECOD_NO_EXECUTE [i]->read(), respons [context].front()._no_execute );
500	TEST(Tcontrol_t , out_DECOD_IS_DELAY_SLOT [i]->read(), respons [context].front()._is_delay_slot);
501	// TEST(Tgeneral_data_t , out_DECOD_ADDRESS_NEXT [i]->read(), respons [context].front()._address_next );
502	TEST(Tcontrol_t , out_DECOD_HAS_IMMEDIAT [i]->read(), respons [context].front()._has_immediat );
503	if (respons [context].front()._has_immediat)
504	TEST(Tgeneral_data_t , out_DECOD_IMMEDIAT [i]->read(), respons [context].front()._immediat );
505	TEST(Tcontrol_t , out_DECOD_READ_RA [i]->read(), respons [context].front()._read_ra );
506	if (respons [context].front()._read_ra)
507	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RA [i]->read(), respons [context].front()._num_reg_ra );
508	TEST(Tcontrol_t , out_DECOD_READ_RB [i]->read(), respons [context].front()._read_rb );
509	if (respons [context].front()._read_rb)
510	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RB [i]->read(), respons [context].front()._num_reg_rb );
511	TEST(Tcontrol_t , out_DECOD_READ_RC [i]->read(), respons [context].front()._read_rc );
512	if (respons [context].front()._read_rc)
513	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RC [i]->read(), respons [context].front()._num_reg_rc );
514	TEST(Tcontrol_t , out_DECOD_WRITE_RD [i]->read(), respons [context].front()._write_rd );
515	if (respons [context].front()._write_rd)
516	TEST(Tgeneral_address_t, out_DECOD_NUM_REG_RD [i]->read(), respons [context].front()._num_reg_rd );
517	TEST(Tcontrol_t , out_DECOD_WRITE_RE [i]->read(), respons [context].front()._write_re );
518	if (respons [context].front()._write_re)
519	TEST(Tspecial_address_t, out_DECOD_NUM_REG_RE [i]->read(), respons [context].front()._num_reg_re );
520	TEST(Texception_t , out_DECOD_EXCEPTION_USE [i]->read(), respons [context].front()._exception_use);
521	// TEST(Texception_t , out_DECOD_EXCEPTION [i]->read(), respons [context].front()._exception );
522
523	respons [context].pop_front();
524	nb_request --;
525	}
526
527	TEST(bool, (out_CONTEXT_EVENT_VAL->read() and in_CONTEXT_EVENT_ACK->read()), find_event);
528
529	SC_START(1);
530	}
531
532	for (uint32_t i=0; i<_param->_nb_context; i++)
533	{
534	TEST(Tcounter_t,out_NB_INST_DECOD_ALL [i]->read(), respons[i].size());
535
536	}
537	}
538
539	/********************************************************
540	* Simulation - End
541	********************************************************/
542
543	TEST_OK ("End of Simulation");
544	delete _time;
545
546	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
547
548	delete in_CLOCK;
549	delete in_NRESET;
550
551	DELETE2_SC_SIGNAL( in_IFETCH_VAL ,_param->_nb_context, _param->_nb_inst_fetch[it1]);
552	DELETE2_SC_SIGNAL(out_IFETCH_ACK ,_param->_nb_context, _param->_nb_inst_fetch[it1]);
553	DELETE2_SC_SIGNAL( in_IFETCH_INSTRUCTION ,_param->_nb_context, _param->_nb_inst_fetch[it1]);
554	DELETE1_SC_SIGNAL(in_IFETCH_CONTEXT_ID ,_param->_nb_context);
555	DELETE1_SC_SIGNAL(in_IFETCH_ADDRESS ,_param->_nb_context);
556	//DELETE1_SC_SIGNAL(in_IFETCH_ADDRESS_NEXT ,_param->_nb_context);
557	DELETE1_SC_SIGNAL(in_IFETCH_INST_IFETCH_PTR ,_param->_nb_context);
558	DELETE1_SC_SIGNAL(in_IFETCH_BRANCH_STATE ,_param->_nb_context);
559	DELETE1_SC_SIGNAL(in_IFETCH_BRANCH_UPDATE_PREDICTION_ID ,_param->_nb_context);
560	DELETE1_SC_SIGNAL(in_IFETCH_EXCEPTION ,_param->_nb_context);
561
562	DELETE1_SC_SIGNAL(out_DECOD_VAL ,_param->_nb_inst_decod);
563	DELETE1_SC_SIGNAL( in_DECOD_ACK ,_param->_nb_inst_decod);
564	DELETE1_SC_SIGNAL(out_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
565	DELETE1_SC_SIGNAL(out_DECOD_DEPTH ,_param->_nb_inst_decod);
566	DELETE1_SC_SIGNAL(out_DECOD_TYPE ,_param->_nb_inst_decod);
567	DELETE1_SC_SIGNAL(out_DECOD_OPERATION ,_param->_nb_inst_decod);
568	DELETE1_SC_SIGNAL(out_DECOD_NO_EXECUTE ,_param->_nb_inst_decod);
569	DELETE1_SC_SIGNAL(out_DECOD_IS_DELAY_SLOT ,_param->_nb_inst_decod);
570	#ifdef DEBUG
571	DELETE1_SC_SIGNAL(out_DECOD_ADDRESS ,_param->_nb_inst_decod);
572	#endif
573	DELETE1_SC_SIGNAL(out_DECOD_ADDRESS_NEXT ,_param->_nb_inst_decod);
574	DELETE1_SC_SIGNAL(out_DECOD_HAS_IMMEDIAT ,_param->_nb_inst_decod);
575	DELETE1_SC_SIGNAL(out_DECOD_IMMEDIAT ,_param->_nb_inst_decod);
576	DELETE1_SC_SIGNAL(out_DECOD_READ_RA ,_param->_nb_inst_decod);
577	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RA ,_param->_nb_inst_decod);
578	DELETE1_SC_SIGNAL(out_DECOD_READ_RB ,_param->_nb_inst_decod);
579	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RB ,_param->_nb_inst_decod);
580	DELETE1_SC_SIGNAL(out_DECOD_READ_RC ,_param->_nb_inst_decod);
581	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RC ,_param->_nb_inst_decod);
582	DELETE1_SC_SIGNAL(out_DECOD_WRITE_RD ,_param->_nb_inst_decod);
583	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RD ,_param->_nb_inst_decod);
584	DELETE1_SC_SIGNAL(out_DECOD_WRITE_RE ,_param->_nb_inst_decod);
585	DELETE1_SC_SIGNAL(out_DECOD_NUM_REG_RE ,_param->_nb_inst_decod);
586	DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION_USE ,_param->_nb_inst_decod);
587	DELETE1_SC_SIGNAL(out_DECOD_EXCEPTION ,_param->_nb_inst_decod);
588
589	DELETE1_SC_SIGNAL(out_PREDICT_VAL ,_param->_nb_inst_decod);
590	DELETE1_SC_SIGNAL( in_PREDICT_ACK ,_param->_nb_inst_decod);
591	DELETE1_SC_SIGNAL(out_PREDICT_CONTEXT_ID ,_param->_nb_inst_decod);
592	DELETE1_SC_SIGNAL(out_PREDICT_MATCH_INST_IFETCH_PTR ,_param->_nb_inst_decod);
593	DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_STATE ,_param->_nb_inst_decod);
594	DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_UPDATE_PREDICTION_ID,_param->_nb_inst_decod);
595	DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_CONDITION ,_param->_nb_inst_decod);
596	//DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_STACK_WRITE ,_param->_nb_inst_decod);
597	DELETE1_SC_SIGNAL(out_PREDICT_BRANCH_DIRECTION ,_param->_nb_inst_decod);
598	DELETE1_SC_SIGNAL(out_PREDICT_ADDRESS_SRC ,_param->_nb_inst_decod);
599	DELETE1_SC_SIGNAL(out_PREDICT_ADDRESS_DEST ,_param->_nb_inst_decod);
600	DELETE1_SC_SIGNAL( in_PREDICT_CAN_CONTINUE ,_param->_nb_inst_decod);
601
602	DELETE1_SC_SIGNAL( in_DEPTH_MIN ,_param->_nb_context);
603	DELETE1_SC_SIGNAL( in_DEPTH_MAX ,_param->_nb_context);
604	DELETE1_SC_SIGNAL( in_DEPTH_FULL ,_param->_nb_context);
605
606	DELETE1_SC_SIGNAL(out_NB_INST_DECOD_ALL ,_param->_nb_context);
607
608	DELETE1_SC_SIGNAL( in_CONTEXT_DECOD_ENABLE ,_param->_nb_context);
609	DELETE1_SC_SIGNAL( in_CONTEXT_DEPTH_VAL ,_param->_nb_context);
610	DELETE1_SC_SIGNAL( in_CONTEXT_DEPTH ,_param->_nb_context);
611
612	DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_VAL );
613	DELETE0_SC_SIGNAL( in_CONTEXT_EVENT_ACK );
614	DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_CONTEXT_ID );
615	DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_DEPTH );
616	DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_TYPE );
617	DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_IS_DELAY_SLOT );
618	DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS );
619	DELETE0_SC_SIGNAL(out_CONTEXT_EVENT_ADDRESS_EPCR );
620	}
621	#endif
622
623	delete _Decod_unit;
624	#ifdef STATISTICS
625	delete _parameters_statistics;
626	#endif
627	}

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/SelfTest/src/test.cpp @ 117

Download in other formats: