[78] | 1 | /* |
---|
| 2 | * $Id: test.cpp 81 2008-04-15 18:40:01Z rosiere $ |
---|
| 3 | * |
---|
| 4 | * [ Description ] |
---|
| 5 | * |
---|
| 6 | * Test |
---|
| 7 | */ |
---|
| 8 | |
---|
| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h" |
---|
| 10 | #include "Common/include/Test.h" |
---|
| 11 | #include "Behavioural/include/Allocation.h" |
---|
| 12 | |
---|
| 13 | #define NB_ITERATION 1024 |
---|
| 14 | #define CYCLE_MAX (128*NB_ITERATION) |
---|
| 15 | |
---|
| 16 | #define LABEL(str...) \ |
---|
| 17 | { \ |
---|
| 18 | msg (_("{%d} "),static_cast<uint32_t>(sc_simulation_time())); \ |
---|
| 19 | msg (str); \ |
---|
| 20 | msg (_("\n")); \ |
---|
| 21 | } while(0) |
---|
| 22 | |
---|
| 23 | #define SC_START(cycle_offset) \ |
---|
| 24 | do \ |
---|
| 25 | { \ |
---|
| 26 | /*cout << "SC_START (begin)" << endl;*/ \ |
---|
| 27 | \ |
---|
| 28 | uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ |
---|
| 29 | if (cycle_offset != 0) \ |
---|
| 30 | { \ |
---|
| 31 | cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \ |
---|
| 32 | } \ |
---|
| 33 | \ |
---|
| 34 | if (cycle_current > CYCLE_MAX) \ |
---|
| 35 | { \ |
---|
| 36 | TEST_KO("Maximal cycles Reached"); \ |
---|
| 37 | } \ |
---|
| 38 | \ |
---|
| 39 | sc_start(cycle_offset); \ |
---|
| 40 | \ |
---|
| 41 | /*cout << "SC_START (end )" << endl;*/ \ |
---|
| 42 | } while(0) |
---|
| 43 | |
---|
| 44 | void test (string name, |
---|
| 45 | morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param) |
---|
| 46 | { |
---|
| 47 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
---|
| 48 | |
---|
| 49 | #ifdef STATISTICS |
---|
| 50 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
---|
| 51 | #endif |
---|
| 52 | |
---|
| 53 | Address_management * _Address_management = new Address_management (name.c_str(), |
---|
| 54 | #ifdef STATISTICS |
---|
| 55 | _parameters_statistics, |
---|
| 56 | #endif |
---|
| 57 | _param); |
---|
| 58 | |
---|
| 59 | #ifdef SYSTEMC |
---|
| 60 | /********************************************************************* |
---|
| 61 | * Déclarations des signaux |
---|
| 62 | *********************************************************************/ |
---|
| 63 | string rename; |
---|
| 64 | |
---|
| 65 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
---|
| 66 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
---|
| 67 | |
---|
| 68 | ALLOC_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t ); |
---|
| 69 | ALLOC_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t ); |
---|
| 70 | ALLOC_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t); |
---|
| 71 | ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
---|
| 72 | ALLOC_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); |
---|
| 73 | ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); |
---|
| 74 | ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
---|
| 75 | ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); |
---|
| 76 | ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); |
---|
| 77 | ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t); |
---|
| 78 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t); |
---|
| 79 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); |
---|
| 80 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t); |
---|
| 81 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); |
---|
| 82 | ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
---|
| 83 | ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); |
---|
| 84 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); |
---|
| 85 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
---|
| 86 | ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); |
---|
| 87 | ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); |
---|
| 88 | ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t); |
---|
| 89 | |
---|
| 90 | /******************************************************** |
---|
| 91 | * Instanciation |
---|
| 92 | ********************************************************/ |
---|
| 93 | |
---|
| 94 | msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str()); |
---|
| 95 | |
---|
| 96 | (*(_Address_management->in_CLOCK)) (*(in_CLOCK)); |
---|
| 97 | (*(_Address_management->in_NRESET)) (*(in_NRESET)); |
---|
| 98 | |
---|
| 99 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_VAL ); |
---|
| 100 | INSTANCE_SC_SIGNAL (_Address_management, in_ADDRESS_ACK ); |
---|
| 101 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS ); |
---|
| 102 | INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
---|
| 103 | if (_param->_have_port_instruction_ptr) |
---|
| 104 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR ); |
---|
| 105 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE ); |
---|
| 106 | if (_param->_have_port_branch_update_prediction_id) |
---|
| 107 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); |
---|
| 108 | INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL ); |
---|
| 109 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_ACK ); |
---|
| 110 | INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS ); |
---|
| 111 | INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT ); |
---|
| 112 | INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); |
---|
| 113 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT ); |
---|
| 114 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
---|
| 115 | INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
---|
| 116 | if (_param->_have_port_instruction_ptr) |
---|
| 117 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); |
---|
| 118 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); |
---|
| 119 | if (_param->_have_port_branch_update_prediction_id) |
---|
| 120 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
---|
| 121 | INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL ); |
---|
| 122 | INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK ); |
---|
| 123 | INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS ); |
---|
| 124 | |
---|
| 125 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
---|
| 126 | |
---|
| 127 | Time * _time = new Time(); |
---|
| 128 | |
---|
| 129 | /******************************************************** |
---|
| 130 | * Simulation - Begin |
---|
| 131 | ********************************************************/ |
---|
| 132 | |
---|
| 133 | // Initialisation |
---|
| 134 | |
---|
| 135 | const uint32_t seed = 0; |
---|
| 136 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
---|
| 137 | |
---|
| 138 | srand(seed); |
---|
| 139 | |
---|
| 140 | const int32_t percent_transaction_address = 75; |
---|
| 141 | const int32_t percent_transaction_predict = 75; |
---|
| 142 | const int32_t percent_transaction_event = 10; |
---|
| 143 | |
---|
| 144 | SC_START(0); |
---|
| 145 | LABEL("Initialisation"); |
---|
| 146 | |
---|
| 147 | LABEL("Reset"); |
---|
| 148 | |
---|
| 149 | in_ADDRESS_ACK->write(0); |
---|
| 150 | out_PREDICT_VAL->write(0); |
---|
| 151 | in_EVENT_VAL ->write(0); |
---|
| 152 | |
---|
| 153 | in_NRESET->write(0); |
---|
| 154 | SC_START(5); |
---|
| 155 | in_NRESET->write(1); |
---|
| 156 | |
---|
| 157 | LABEL("Test Reset"); |
---|
| 158 | |
---|
| 159 | TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false); |
---|
| 160 | TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction |
---|
| 161 | TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event |
---|
| 162 | |
---|
| 163 | Tcontrol_t p_val = false; |
---|
| 164 | Tcontrol_t c_val = false; |
---|
| 165 | Tcontrol_t n_val = false; |
---|
| 166 | |
---|
| 167 | Tgeneral_data_t p_addr = 0x100; |
---|
| 168 | Tgeneral_data_t c_addr = 0x100; |
---|
| 169 | Tgeneral_data_t n_addr = 0x100; |
---|
| 170 | Tcontrol_t c_enable [_param->_nb_instruction]; |
---|
| 171 | Tcontrol_t n_enable [_param->_nb_instruction]; |
---|
| 172 | |
---|
| 173 | Tcontrol_t c_is_ds_take = 0; |
---|
| 174 | Tinst_ifetch_ptr_t c_ifetch_ptr = 0; |
---|
| 175 | Tbranch_state_t c_branch_state = BRANCH_STATE_NONE; |
---|
| 176 | Tprediction_ptr_t c_branch_ptr = 0; |
---|
| 177 | |
---|
| 178 | Tcontrol_t n_is_ds_take = 0; |
---|
| 179 | Tinst_ifetch_ptr_t n_ifetch_ptr = 0; |
---|
| 180 | Tbranch_state_t n_branch_state = BRANCH_STATE_NONE; |
---|
| 181 | Tprediction_ptr_t n_branch_ptr = 0; |
---|
| 182 | |
---|
| 183 | c_enable [0] = 1; |
---|
| 184 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
---|
| 185 | c_enable [i] = 0; |
---|
| 186 | |
---|
| 187 | LABEL("Send Reset"); |
---|
| 188 | do |
---|
| 189 | { |
---|
| 190 | in_EVENT_VAL ->write(1); |
---|
| 191 | in_EVENT_ADDRESS->write(c_addr); |
---|
| 192 | SC_START(1); |
---|
| 193 | } while (out_EVENT_ACK->read() == false); |
---|
| 194 | in_EVENT_VAL ->write(0); |
---|
| 195 | |
---|
| 196 | LABEL("Loop of Test"); |
---|
| 197 | |
---|
| 198 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
---|
| 199 | { |
---|
| 200 | LABEL("Iteration %d",iteration); |
---|
| 201 | |
---|
| 202 | in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address); |
---|
| 203 | in_EVENT_VAL ->write((rand()%100)<percent_transaction_event ); |
---|
| 204 | in_EVENT_ADDRESS->write(rand() << 2); |
---|
| 205 | |
---|
| 206 | uint32_t begin = rand() % _param->_nb_instruction; |
---|
| 207 | uint32_t end = (begin + (rand() % _param->_nb_instruction)); |
---|
| 208 | end = (end > _param->_nb_instruction)?_param->_nb_instruction:end; |
---|
| 209 | |
---|
| 210 | in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); |
---|
| 211 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
| 212 | in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); |
---|
| 213 | in_PREDICT_PC_NEXT ->write(rand() << 2); |
---|
| 214 | in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(rand()%2); |
---|
| 215 | in_PREDICT_INST_IFETCH_PTR ->write(begin); |
---|
| 216 | in_PREDICT_BRANCH_STATE ->write(c_addr%SIZE_BRANCH_STATE); |
---|
| 217 | in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(c_addr%_param->_size_branch_update_prediction); |
---|
| 218 | |
---|
| 219 | SC_START(0); |
---|
| 220 | |
---|
| 221 | LABEL("---------------------"); |
---|
| 222 | LABEL(" * pc-4 : %d %.8x",p_val, p_addr); |
---|
| 223 | LABEL(" * pc : %d %.8x",c_val, c_addr); |
---|
| 224 | LABEL(" * pc+4 : %d %.8x",n_val, n_addr); |
---|
| 225 | LABEL("---------------------"); |
---|
| 226 | |
---|
| 227 | if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) |
---|
| 228 | { |
---|
| 229 | LABEL("PREDICT : Transaction accepted"); |
---|
| 230 | |
---|
| 231 | TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),p_addr); |
---|
| 232 | TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),c_addr); |
---|
| 233 | TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),c_is_ds_take); |
---|
| 234 | } |
---|
| 235 | |
---|
| 236 | if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read()) |
---|
| 237 | { |
---|
| 238 | LABEL("ADDRESS : Transaction accepted"); |
---|
| 239 | LABEL(" * address wait : %.8x",c_addr); |
---|
| 240 | |
---|
| 241 | TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),c_addr); |
---|
| 242 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
| 243 | TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),c_enable[i]); |
---|
| 244 | if (_param->_have_port_instruction_ptr) |
---|
| 245 | TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),c_ifetch_ptr ); |
---|
| 246 | TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),c_branch_state); |
---|
| 247 | if (_param->_have_port_branch_update_prediction_id) |
---|
| 248 | TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),c_branch_ptr ); |
---|
| 249 | |
---|
| 250 | p_val = true; |
---|
| 251 | c_val = n_val; |
---|
| 252 | |
---|
| 253 | p_addr = c_addr; |
---|
| 254 | |
---|
| 255 | if (n_val) |
---|
| 256 | { |
---|
| 257 | c_addr = n_addr; |
---|
| 258 | |
---|
| 259 | c_ifetch_ptr = n_ifetch_ptr ; |
---|
| 260 | c_branch_state = n_branch_state; |
---|
| 261 | c_branch_ptr = n_branch_ptr ; |
---|
| 262 | c_is_ds_take = n_is_ds_take ; |
---|
| 263 | |
---|
| 264 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
| 265 | c_enable [i] = n_enable [i]; |
---|
| 266 | } |
---|
| 267 | |
---|
| 268 | n_val = false; |
---|
| 269 | |
---|
| 270 | LABEL(" * pc-4 : %d %.8x",p_val, p_addr); |
---|
| 271 | LABEL(" * pc : %d %.8x",c_val, c_addr); |
---|
| 272 | LABEL(" * pc+4 : %d %.8x",n_val, n_addr); |
---|
| 273 | } |
---|
| 274 | |
---|
| 275 | if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) |
---|
| 276 | { |
---|
| 277 | LABEL("PREDICT : Update information"); |
---|
| 278 | |
---|
| 279 | if (c_val) |
---|
| 280 | { |
---|
| 281 | LABEL(" * current is valid -> new next"); |
---|
| 282 | n_val = true; |
---|
| 283 | |
---|
| 284 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
| 285 | n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read(); |
---|
| 286 | n_addr = in_PREDICT_PC_NEXT ->read(); |
---|
| 287 | n_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read(); |
---|
| 288 | n_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read(); |
---|
| 289 | n_branch_state = in_PREDICT_BRANCH_STATE ->read(); |
---|
| 290 | n_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read(); |
---|
| 291 | } |
---|
| 292 | else |
---|
| 293 | { |
---|
| 294 | LABEL(" * current is not valid -> new current"); |
---|
| 295 | c_val = true; |
---|
| 296 | |
---|
| 297 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
| 298 | c_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read(); |
---|
| 299 | c_addr = in_PREDICT_PC_NEXT ->read(); |
---|
| 300 | c_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read(); |
---|
| 301 | c_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read(); |
---|
| 302 | c_branch_state = in_PREDICT_BRANCH_STATE ->read(); |
---|
| 303 | c_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read(); |
---|
| 304 | } |
---|
| 305 | |
---|
| 306 | LABEL(" * pc-4 : %d %.8x",p_val, p_addr); |
---|
| 307 | LABEL(" * pc : %d %.8x",c_val, c_addr); |
---|
| 308 | LABEL(" * pc+4 : %d %.8x",n_val, n_addr); |
---|
| 309 | |
---|
| 310 | } |
---|
| 311 | |
---|
| 312 | if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) |
---|
| 313 | { |
---|
| 314 | LABEL("EVENT : Transaction accepted"); |
---|
| 315 | |
---|
| 316 | c_val = true; |
---|
| 317 | n_val = false; |
---|
| 318 | |
---|
| 319 | c_addr = in_EVENT_ADDRESS->read(); |
---|
| 320 | c_ifetch_ptr = 0; |
---|
| 321 | c_branch_state = BRANCH_STATE_NONE; |
---|
| 322 | c_branch_ptr = 0; |
---|
| 323 | c_is_ds_take = 0; |
---|
| 324 | |
---|
| 325 | c_enable [0] = 1; |
---|
| 326 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
---|
| 327 | c_enable [i] = 0; |
---|
| 328 | |
---|
| 329 | LABEL(" * pc-4 : %d %.8x",p_val, p_addr); |
---|
| 330 | LABEL(" * pc : %d %.8x",c_val, c_addr); |
---|
| 331 | LABEL(" * pc+4 : %d %.8x",n_val, n_addr); |
---|
| 332 | } |
---|
| 333 | SC_START(1); |
---|
| 334 | } |
---|
| 335 | |
---|
| 336 | /******************************************************** |
---|
| 337 | * Simulation - End |
---|
| 338 | ********************************************************/ |
---|
| 339 | |
---|
| 340 | TEST_OK ("End of Simulation"); |
---|
| 341 | delete _time; |
---|
| 342 | |
---|
| 343 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
---|
| 344 | |
---|
| 345 | delete in_CLOCK; |
---|
| 346 | delete in_NRESET; |
---|
| 347 | |
---|
| 348 | delete out_ADDRESS_VAL ; |
---|
| 349 | delete in_ADDRESS_ACK ; |
---|
| 350 | delete out_ADDRESS_INSTRUCTION_ADDRESS ; |
---|
| 351 | delete [] out_ADDRESS_INSTRUCTION_ENABLE ; |
---|
| 352 | delete out_ADDRESS_INST_IFETCH_PTR ; |
---|
| 353 | delete out_ADDRESS_BRANCH_STATE ; |
---|
| 354 | delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; |
---|
| 355 | delete out_PREDICT_VAL ; |
---|
| 356 | delete in_PREDICT_ACK ; |
---|
| 357 | delete out_PREDICT_PC_PREVIOUS ; |
---|
| 358 | delete out_PREDICT_PC_CURRENT ; |
---|
| 359 | delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; |
---|
| 360 | delete in_PREDICT_PC_NEXT ; |
---|
| 361 | delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; |
---|
| 362 | delete [] in_PREDICT_INSTRUCTION_ENABLE ; |
---|
| 363 | delete in_PREDICT_INST_IFETCH_PTR ; |
---|
| 364 | delete in_PREDICT_BRANCH_STATE ; |
---|
| 365 | delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID; |
---|
| 366 | delete in_EVENT_VAL ; |
---|
| 367 | delete out_EVENT_ACK ; |
---|
| 368 | delete in_EVENT_ADDRESS ; |
---|
| 369 | #endif |
---|
| 370 | |
---|
| 371 | delete _Address_management; |
---|
| 372 | #ifdef STATISTICS |
---|
| 373 | delete _parameters_statistics; |
---|
| 374 | #endif |
---|
| 375 | } |
---|