1 | /* |
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2 | * $Id: test.cpp 107 2009-02-10 23:03:25Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | |
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10 | #define NB_ITERATION 1024 |
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11 | #define CYCLE_MAX (128*NB_ITERATION) |
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12 | |
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13 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h" |
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14 | #include "Common/include/Test.h" |
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15 | #include "Behavioural/include/Allocation.h" |
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16 | |
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17 | void test (string name, |
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18 | morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param) |
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19 | { |
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20 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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21 | |
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22 | #ifdef STATISTICS |
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23 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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24 | #endif |
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25 | |
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26 | Tusage_t _usage = USE_ALL; |
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27 | |
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28 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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29 | // _usage = usage_unset(_usage,USE_VHDL ); |
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30 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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31 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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32 | // _usage = usage_unset(_usage,USE_POSITION ); |
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33 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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34 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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35 | |
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36 | Address_management * _Address_management = new Address_management |
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37 | (name.c_str(), |
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38 | #ifdef STATISTICS |
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39 | _parameters_statistics, |
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40 | #endif |
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41 | _param, |
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42 | _usage); |
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43 | |
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44 | #ifdef SYSTEMC |
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45 | /********************************************************************* |
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46 | * Déclarations des signaux |
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47 | *********************************************************************/ |
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48 | string rename; |
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49 | |
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50 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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51 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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52 | |
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53 | ALLOC_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t ); |
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54 | ALLOC_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t ); |
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55 | ALLOC_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t); |
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56 | ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
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57 | ALLOC_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); |
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58 | ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); |
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59 | ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
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60 | ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); |
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61 | ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); |
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62 | ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t); |
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63 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t); |
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64 | ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); |
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65 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t); |
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66 | ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); |
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67 | ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
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68 | ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); |
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69 | //ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT ," in_PREDICT_BRANCH_IS_CURRENT ",Tcontrol_t ); |
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70 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); |
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71 | ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
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72 | ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); |
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73 | ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); |
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74 | ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t); |
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75 | ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t); |
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76 | ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t ); |
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77 | ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t ); |
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78 | |
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79 | /******************************************************** |
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80 | * Instanciation |
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81 | ********************************************************/ |
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82 | |
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83 | msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str()); |
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84 | |
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85 | (*(_Address_management->in_CLOCK)) (*(in_CLOCK)); |
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86 | (*(_Address_management->in_NRESET)) (*(in_NRESET)); |
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87 | |
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88 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_VAL ); |
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89 | INSTANCE_SC_SIGNAL (_Address_management, in_ADDRESS_ACK ); |
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90 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS ); |
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91 | INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
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92 | if (_param->_have_port_inst_ifetch_ptr) |
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93 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR ); |
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94 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE ); |
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95 | if (_param->_have_port_depth) |
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96 | INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); |
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97 | INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL ); |
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98 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_ACK ); |
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99 | INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS ); |
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100 | INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT ); |
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101 | INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); |
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102 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT ); |
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103 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE ); |
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104 | INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
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105 | if (_param->_have_port_inst_ifetch_ptr) |
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106 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); |
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107 | //INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT ); |
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108 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); |
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109 | if (_param->_have_port_depth) |
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110 | INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); |
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111 | INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL ); |
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112 | INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK ); |
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113 | INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS ); |
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114 | INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT ); |
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115 | INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL ); |
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116 | INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE ); |
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117 | |
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118 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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119 | |
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120 | Time * _time = new Time(); |
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121 | |
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122 | /******************************************************** |
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123 | * Simulation - Begin |
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124 | ********************************************************/ |
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125 | |
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126 | // Initialisation |
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127 | |
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128 | const uint32_t seed = 0; |
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129 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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130 | |
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131 | srand(seed); |
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132 | |
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133 | const int32_t percent_transaction_address = 100; |
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134 | const int32_t percent_transaction_predict = 100; |
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135 | const int32_t percent_transaction_event = 0; |
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136 | |
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137 | SC_START(0); |
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138 | LABEL("Initialisation"); |
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139 | |
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140 | LABEL("Reset"); |
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141 | |
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142 | in_ADDRESS_ACK->write(0); |
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143 | out_PREDICT_VAL->write(0); |
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144 | in_EVENT_VAL ->write(0); |
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145 | |
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146 | in_NRESET->write(0); |
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147 | SC_START(5); |
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148 | in_NRESET->write(1); |
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149 | |
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150 | LABEL("Test Reset"); |
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151 | |
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152 | TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false); |
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153 | TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction |
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154 | TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event |
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155 | |
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156 | uint32_t jump = 7 ;// packet |
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157 | uint32_t nb_packet = 1; |
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158 | |
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159 | Tcontrol_t a_val = false; |
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160 | Tcontrol_t c_val = false; |
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161 | Tcontrol_t n_val = true ; |
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162 | Tcontrol_t nn_val = false; |
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163 | |
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164 | Tgeneral_data_t a_addr = 0x100>>2; |
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165 | Tgeneral_data_t c_addr = 0x100>>2; |
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166 | Tgeneral_data_t n_addr = 0x100>>2; |
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167 | Tgeneral_data_t nn_addr = 0x100>>2; |
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168 | |
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169 | Tcontrol_t a_enable [_param->_nb_instruction]; |
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170 | Tcontrol_t c_enable [_param->_nb_instruction]; |
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171 | Tcontrol_t n_enable [_param->_nb_instruction]; |
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172 | |
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173 | Tcontrol_t a_is_ds_take = 0; |
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174 | Tcontrol_t c_is_ds_take = 0; |
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175 | Tcontrol_t n_is_ds_take = 0; |
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176 | Tcontrol_t nn_is_ds_take = 0; |
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177 | |
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178 | n_enable [0] = 1; |
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179 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
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180 | n_enable [i] = 0; |
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181 | |
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182 | LABEL("Send Reset"); |
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183 | // do |
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184 | // { |
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185 | // in_EVENT_VAL ->write(1); |
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186 | // in_EVENT_ADDRESS ->write(n_addr); |
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187 | // in_EVENT_ADDRESS_NEXT ->write(nn_addr); |
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188 | // in_EVENT_ADDRESS_NEXT_VAL->write(0); |
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189 | // in_EVENT_IS_DS_TAKE ->write(0); |
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190 | // SC_START(1); |
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191 | // } while (out_EVENT_ACK->read() == false); |
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192 | // in_EVENT_VAL ->write(0); |
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193 | |
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194 | n_val = 1; |
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195 | |
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196 | LABEL("Loop of Test"); |
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197 | |
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198 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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199 | { |
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200 | LABEL("Iteration %d",iteration); |
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201 | |
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202 | // PREDICT |
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203 | { |
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204 | in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict); |
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205 | |
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206 | SC_START(0); |
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207 | |
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208 | Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read(); |
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209 | |
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210 | uint32_t begin = addr%_param->_nb_instruction; |
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211 | uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1); |
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212 | Tcontrol_t take = (nb_packet%jump)==0; |
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213 | |
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214 | if (take) |
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215 | addr += 0x100; |
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216 | else |
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217 | addr += end-begin+1; |
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218 | |
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219 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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220 | in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); |
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221 | in_PREDICT_PC_NEXT ->write(addr); |
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222 | in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); |
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223 | in_PREDICT_INST_IFETCH_PTR ->write(0); |
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224 | // in_PREDICT_BRANCH_IS_CURRENT ->write(0); |
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225 | in_PREDICT_BRANCH_STATE ->write(0); |
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226 | in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); |
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227 | } |
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228 | |
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229 | // ADDRESS |
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230 | { |
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231 | in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address); |
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232 | } |
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233 | |
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234 | in_EVENT_VAL ->write((rand()%100)<percent_transaction_event ); |
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235 | in_EVENT_ADDRESS ->write(0x77); |
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236 | in_EVENT_ADDRESS_NEXT ->write(0x171); |
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237 | Tcontrol_t next_val = rand()%2; |
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238 | in_EVENT_ADDRESS_NEXT_VAL->write(next_val); |
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239 | in_EVENT_IS_DS_TAKE ->write(next_val); |
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240 | |
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241 | //------------------------------------------------- |
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242 | SC_START(0); |
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243 | //------------------------------------------------- |
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244 | |
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245 | if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) |
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246 | { |
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247 | LABEL("PREDICT : Transaction accepted"); |
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248 | |
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249 | if (c_val) |
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250 | TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr ); |
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251 | TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr ); |
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252 | TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take); |
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253 | |
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254 | nn_val = true; |
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255 | nn_addr = in_PREDICT_PC_NEXT ->read(); |
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256 | nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read(); |
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257 | |
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258 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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259 | n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); |
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260 | |
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261 | LABEL(" * nn_addr : %.8x",nn_addr); |
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262 | } |
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263 | |
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264 | if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read()) |
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265 | { |
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266 | LABEL("ADDRESS : Transaction accepted"); |
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267 | LABEL(" * address wait : %.8x",a_addr); |
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268 | |
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269 | TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),a_addr-a_addr%_param->_nb_instruction); |
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270 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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271 | TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),a_enable[i]); |
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272 | if (_param->_have_port_inst_ifetch_ptr) |
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273 | TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0); |
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274 | TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0); |
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275 | if (_param->_have_port_depth) |
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276 | TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0); |
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277 | |
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278 | a_val = 0; |
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279 | nb_packet ++; |
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280 | } |
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281 | |
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282 | { |
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283 | string str_a_enable = ""; |
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284 | string str_c_enable = ""; |
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285 | string str_n_enable = ""; |
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286 | |
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287 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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288 | { |
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289 | str_a_enable += " " + toString(a_enable [i]); |
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290 | str_c_enable += " " + toString(c_enable [i]); |
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291 | str_n_enable += " " + toString(n_enable [i]); |
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292 | } |
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293 | |
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294 | LABEL("----[ Before ]---------------------"); |
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295 | LABEL(" * nb_packet : %d",nb_packet); |
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296 | LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); |
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297 | LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); |
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298 | LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); |
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299 | LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); |
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300 | LABEL("-----------------------------------"); |
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301 | } |
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302 | |
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303 | if (not a_val) |
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304 | { |
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305 | if (c_val and n_val and nn_val) |
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306 | { |
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307 | a_val = 1; |
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308 | c_val = 0; |
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309 | a_addr = c_addr; |
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310 | a_is_ds_take = c_is_ds_take; |
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311 | |
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312 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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313 | a_enable [i] = c_enable [i]; |
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314 | } |
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315 | } |
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316 | |
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317 | if (not c_val) |
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318 | { |
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319 | c_val = n_val; |
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320 | if (n_val) |
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321 | { |
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322 | c_addr = n_addr; |
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323 | c_is_ds_take = n_is_ds_take; |
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324 | |
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325 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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326 | c_enable [i] = n_enable [i]; |
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327 | } |
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328 | n_val = 0; |
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329 | } |
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330 | |
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331 | if (not n_val) |
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332 | { |
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333 | n_val = nn_val; |
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334 | if (nn_val) |
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335 | { |
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336 | n_addr = nn_addr; |
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337 | n_is_ds_take = nn_is_ds_take; |
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338 | |
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339 | // for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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340 | // n_enable [i] = nn_enable [i]; |
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341 | } |
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342 | nn_val = 0; |
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343 | } |
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344 | |
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345 | if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) |
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346 | { |
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347 | LABEL("EVENT : Transaction accepted"); |
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348 | |
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349 | a_val = false; |
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350 | c_val = false; |
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351 | n_val = true; |
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352 | n_addr = in_EVENT_ADDRESS ->read(); |
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353 | n_is_ds_take = in_EVENT_IS_DS_TAKE ->read(); |
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354 | nn_val = in_EVENT_ADDRESS_NEXT_VAL->read(); |
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355 | nn_addr = in_EVENT_ADDRESS_NEXT ->read(); |
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356 | nn_is_ds_take= false; |
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357 | // nn_val = false; |
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358 | // n_is_ds_take = 0; |
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359 | |
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360 | n_enable [0] = 1; |
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361 | for (uint32_t i=1; i<_param->_nb_instruction; i++) |
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362 | n_enable [i] = 0; |
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363 | } |
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364 | |
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365 | |
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366 | { |
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367 | string str_a_enable = ""; |
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368 | string str_c_enable = ""; |
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369 | string str_n_enable = ""; |
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370 | |
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371 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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372 | { |
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373 | str_a_enable += " " + toString(a_enable [i]); |
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374 | str_c_enable += " " + toString(c_enable [i]); |
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375 | str_n_enable += " " + toString(n_enable [i]); |
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376 | } |
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377 | |
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378 | LABEL("----[ After ]----------------------"); |
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379 | LABEL(" * nb_packet : %d",nb_packet); |
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380 | LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); |
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381 | LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); |
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382 | LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); |
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383 | LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); |
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384 | LABEL("-----------------------------------"); |
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385 | } |
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386 | |
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387 | SC_START(1); |
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388 | |
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389 | } |
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390 | |
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391 | /******************************************************** |
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392 | * Simulation - End |
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393 | ********************************************************/ |
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394 | |
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395 | TEST_OK ("End of Simulation"); |
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396 | delete _time; |
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397 | |
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398 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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399 | |
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400 | delete in_CLOCK; |
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401 | delete in_NRESET; |
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402 | |
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403 | delete out_ADDRESS_VAL ; |
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404 | delete in_ADDRESS_ACK ; |
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405 | delete out_ADDRESS_INSTRUCTION_ADDRESS ; |
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406 | delete [] out_ADDRESS_INSTRUCTION_ENABLE ; |
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407 | delete out_ADDRESS_INST_IFETCH_PTR ; |
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408 | delete out_ADDRESS_BRANCH_STATE ; |
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409 | delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; |
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410 | delete out_PREDICT_VAL ; |
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411 | delete in_PREDICT_ACK ; |
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412 | delete out_PREDICT_PC_PREVIOUS ; |
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413 | delete out_PREDICT_PC_CURRENT ; |
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414 | delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; |
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415 | delete in_PREDICT_PC_NEXT ; |
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416 | delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; |
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417 | delete [] in_PREDICT_INSTRUCTION_ENABLE ; |
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418 | delete in_PREDICT_INST_IFETCH_PTR ; |
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419 | //delete in_PREDICT_BRANCH_IS_CURRENT ; |
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420 | delete in_PREDICT_BRANCH_STATE ; |
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421 | delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID; |
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422 | delete in_EVENT_VAL ; |
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423 | delete out_EVENT_ACK ; |
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424 | delete in_EVENT_ADDRESS ; |
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425 | delete in_EVENT_ADDRESS_NEXT ; |
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426 | delete in_EVENT_ADDRESS_NEXT_VAL ; |
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427 | delete in_EVENT_IS_DS_TAKE ; |
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428 | #endif |
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429 | |
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430 | delete _Address_management; |
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431 | #ifdef STATISTICS |
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432 | delete _parameters_statistics; |
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433 | #endif |
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434 | } |
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