/* * $Id: test.cpp 82 2008-05-01 16:48:45Z rosiere $ * * [ Description ] * * Test */ #define NB_ITERATION 1024 #define CYCLE_MAX (128*NB_ITERATION) #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h" #include "Common/include/Test.h" #include "Behavioural/include/Allocation.h" void test (string name, morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param) { msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); #ifdef STATISTICS morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); #endif Address_management * _Address_management = new Address_management (name.c_str(), #ifdef STATISTICS _parameters_statistics, #endif _param, USE_ALL); #ifdef SYSTEMC /********************************************************************* * Déclarations des signaux *********************************************************************/ string rename; sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); sc_signal * in_NRESET = new sc_signal ("NRESET"); ALLOC_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t ); ALLOC_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t ); ALLOC_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t); ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); ALLOC_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t ); ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t ); ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t); ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t); ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t ); ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t); ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t ); ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ); ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ); ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t); /******************************************************** * Instanciation ********************************************************/ msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str()); (*(_Address_management->in_CLOCK)) (*(in_CLOCK)); (*(_Address_management->in_NRESET)) (*(in_NRESET)); INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_VAL ); INSTANCE_SC_SIGNAL (_Address_management, in_ADDRESS_ACK ); INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS ); INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); if (_param->_have_port_instruction_ptr) INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR ); INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE ); if (_param->_have_port_branch_update_prediction_id) INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL ); INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_ACK ); INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS ); INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT ); INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE ); INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT ); INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE ); INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction); if (_param->_have_port_instruction_ptr) INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); if (_param->_have_port_branch_update_prediction_id) INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID); INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL ); INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK ); INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS ); msg(_("<%s> : Start Simulation ............\n"),name.c_str()); Time * _time = new Time(); /******************************************************** * Simulation - Begin ********************************************************/ // Initialisation const uint32_t seed = 0; //const uint32_t seed = static_cast(time(NULL)); srand(seed); const int32_t percent_transaction_address = 75; const int32_t percent_transaction_predict = 75; const int32_t percent_transaction_event = 10; SC_START(0); LABEL("Initialisation"); LABEL("Reset"); in_ADDRESS_ACK->write(0); out_PREDICT_VAL->write(0); in_EVENT_VAL ->write(0); in_NRESET->write(0); SC_START(5); in_NRESET->write(1); LABEL("Test Reset"); TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false); TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event Tcontrol_t p_val = false; Tcontrol_t c_val = false; Tcontrol_t n_val = false; Tgeneral_data_t p_addr = 0x100; Tgeneral_data_t c_addr = 0x100; Tgeneral_data_t n_addr = 0x100; Tcontrol_t c_enable [_param->_nb_instruction]; Tcontrol_t n_enable [_param->_nb_instruction]; Tcontrol_t c_is_ds_take = 0; Tinst_ifetch_ptr_t c_ifetch_ptr = 0; Tbranch_state_t c_branch_state = BRANCH_STATE_NONE; Tprediction_ptr_t c_branch_ptr = 0; Tcontrol_t n_is_ds_take = 0; Tinst_ifetch_ptr_t n_ifetch_ptr = 0; Tbranch_state_t n_branch_state = BRANCH_STATE_NONE; Tprediction_ptr_t n_branch_ptr = 0; c_enable [0] = 1; for (uint32_t i=1; i<_param->_nb_instruction; i++) c_enable [i] = 0; LABEL("Send Reset"); do { in_EVENT_VAL ->write(1); in_EVENT_ADDRESS->write(c_addr); SC_START(1); } while (out_EVENT_ACK->read() == false); in_EVENT_VAL ->write(0); LABEL("Loop of Test"); for (uint32_t iteration=0; iterationwrite((rand()%100)write((rand()%100)write(rand() << 2); uint32_t begin = rand() % _param->_nb_instruction; uint32_t end = (begin + (rand() % _param->_nb_instruction)); end = (end > _param->_nb_instruction)?_param->_nb_instruction:end; in_PREDICT_ACK ->write((rand()%100)_nb_instruction; i++) in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end)); in_PREDICT_PC_NEXT ->write(rand() << 2); in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(rand()%2); in_PREDICT_INST_IFETCH_PTR ->write(begin); in_PREDICT_BRANCH_STATE ->write(c_addr%SIZE_BRANCH_STATE); in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(c_addr%_param->_size_branch_update_prediction); SC_START(0); LABEL("---------------------"); LABEL(" * pc-4 : %d %.8x",p_val, p_addr); LABEL(" * pc : %d %.8x",c_val, c_addr); LABEL(" * pc+4 : %d %.8x",n_val, n_addr); LABEL("---------------------"); if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) { LABEL("PREDICT : Transaction accepted"); TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),p_addr); TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),c_addr); TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),c_is_ds_take); } if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read()) { LABEL("ADDRESS : Transaction accepted"); LABEL(" * address wait : %.8x",c_addr); TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),c_addr); for (uint32_t i=0; i<_param->_nb_instruction; i++) TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),c_enable[i]); if (_param->_have_port_instruction_ptr) TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),c_ifetch_ptr ); TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),c_branch_state); if (_param->_have_port_branch_update_prediction_id) TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),c_branch_ptr ); p_val = true; c_val = n_val; p_addr = c_addr; if (n_val) { c_addr = n_addr; c_ifetch_ptr = n_ifetch_ptr ; c_branch_state = n_branch_state; c_branch_ptr = n_branch_ptr ; c_is_ds_take = n_is_ds_take ; for (uint32_t i=0; i<_param->_nb_instruction; i++) c_enable [i] = n_enable [i]; } n_val = false; LABEL(" * pc-4 : %d %.8x",p_val, p_addr); LABEL(" * pc : %d %.8x",c_val, c_addr); LABEL(" * pc+4 : %d %.8x",n_val, n_addr); } if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read()) { LABEL("PREDICT : Update information"); if (c_val) { LABEL(" * current is valid -> new next"); n_val = true; for (uint32_t i=0; i<_param->_nb_instruction; i++) n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read(); n_addr = in_PREDICT_PC_NEXT ->read(); n_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read(); n_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read(); n_branch_state = in_PREDICT_BRANCH_STATE ->read(); n_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read(); } else { LABEL(" * current is not valid -> new current"); c_val = true; for (uint32_t i=0; i<_param->_nb_instruction; i++) c_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read(); c_addr = in_PREDICT_PC_NEXT ->read(); c_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read(); c_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read(); c_branch_state = in_PREDICT_BRANCH_STATE ->read(); c_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read(); } LABEL(" * pc-4 : %d %.8x",p_val, p_addr); LABEL(" * pc : %d %.8x",c_val, c_addr); LABEL(" * pc+4 : %d %.8x",n_val, n_addr); } if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) { LABEL("EVENT : Transaction accepted"); c_val = true; n_val = false; c_addr = in_EVENT_ADDRESS->read(); c_ifetch_ptr = 0; c_branch_state = BRANCH_STATE_NONE; c_branch_ptr = 0; c_is_ds_take = 0; c_enable [0] = 1; for (uint32_t i=1; i<_param->_nb_instruction; i++) c_enable [i] = 0; LABEL(" * pc-4 : %d %.8x",p_val, p_addr); LABEL(" * pc : %d %.8x",c_val, c_addr); LABEL(" * pc+4 : %d %.8x",n_val, n_addr); } SC_START(1); } /******************************************************** * Simulation - End ********************************************************/ TEST_OK ("End of Simulation"); delete _time; msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); delete in_CLOCK; delete in_NRESET; delete out_ADDRESS_VAL ; delete in_ADDRESS_ACK ; delete out_ADDRESS_INSTRUCTION_ADDRESS ; delete [] out_ADDRESS_INSTRUCTION_ENABLE ; delete out_ADDRESS_INST_IFETCH_PTR ; delete out_ADDRESS_BRANCH_STATE ; delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; delete out_PREDICT_VAL ; delete in_PREDICT_ACK ; delete out_PREDICT_PC_PREVIOUS ; delete out_PREDICT_PC_CURRENT ; delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ; delete in_PREDICT_PC_NEXT ; delete in_PREDICT_PC_NEXT_IS_DS_TAKE ; delete [] in_PREDICT_INSTRUCTION_ENABLE ; delete in_PREDICT_INST_IFETCH_PTR ; delete in_PREDICT_BRANCH_STATE ; delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID; delete in_EVENT_VAL ; delete out_EVENT_ACK ; delete in_EVENT_ADDRESS ; #endif delete _Address_management; #ifdef STATISTICS delete _parameters_statistics; #endif }