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test.cpp @ 131

Last change on this file since 131 was 131, checked in by rosiere, 15 years ago
1) add constant method 2) test with systemc 2.2.0
Property svn:keywords set to `Id`
File size: 19.3 KB

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1	/*
2	* $Id: test.cpp 131 2009-07-08 18:40:08Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9
10	#define NB_ITERATION 1024
11	#define CYCLE_MAX (128*NB_ITERATION)
12
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h"
14	#include "Common/include/Test.h"
15	#include "Behavioural/include/Allocation.h"
16
17	void test (string name,
18	morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param)
19	{
20	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
21
22	#ifdef STATISTICS
23	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
24	#endif
25
26	_model.set_model(MODEL_SYSTEMC, true);
27
28	Tusage_t _usage = USE_ALL;
29
30	// _usage = usage_unset(_usage,USE_SYSTEMC );
31	// _usage = usage_unset(_usage,USE_VHDL );
32	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
33	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
34	// _usage = usage_unset(_usage,USE_POSITION );
35	// _usage = usage_unset(_usage,USE_STATISTICS );
36	// _usage = usage_unset(_usage,USE_INFORMATION );
37
38	Address_management * _Address_management = new Address_management
39	(name.c_str(),
40	#ifdef STATISTICS
41	_parameters_statistics,
42	#endif
43	_param,
44	_usage);
45
46	#ifdef SYSTEMC
47	/*********************************************************************
48	* Déclarations des signaux
49	*********************************************************************/
50	string rename;
51
52	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
53	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
54
55	sc_signal<Tcontrol_t > * out_ADDRESS_VAL ;
56	sc_signal<Tcontrol_t > * in_ADDRESS_ACK ; //icache_req_ack and ifetch_queue_ack
57	sc_signal<Tgeneral_address_t> * out_ADDRESS_INSTRUCTION_ADDRESS ;
58	sc_signal<Tcontrol_t > ** out_ADDRESS_INSTRUCTION_ENABLE ; //[nb_instruction]
59	sc_signal<Tinst_ifetch_ptr_t> * out_ADDRESS_INST_IFETCH_PTR ;
60	sc_signal<Tbranch_state_t > * out_ADDRESS_BRANCH_STATE ;
61	sc_signal<Tprediction_ptr_t > * out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ;
62	sc_signal<Tcontrol_t > * out_PREDICT_VAL ;
63	sc_signal<Tcontrol_t > * in_PREDICT_ACK ;
64	sc_signal<Tgeneral_address_t> * out_PREDICT_PC_PREVIOUS ;
65	sc_signal<Tgeneral_address_t> * out_PREDICT_PC_CURRENT ;
66	sc_signal<Tcontrol_t > * out_PREDICT_PC_CURRENT_IS_DS_TAKE ;
67	sc_signal<Tgeneral_address_t> * in_PREDICT_PC_NEXT ;
68	sc_signal<Tcontrol_t > * in_PREDICT_PC_NEXT_IS_DS_TAKE ;
69	sc_signal<Tcontrol_t > ** in_PREDICT_INSTRUCTION_ENABLE ; //[nb_instruction]
70	//sc_signal<Tcontrol_t > * in_PREDICT_BRANCH_IS_CURRENT ;
71	sc_signal<Tbranch_state_t > * in_PREDICT_BRANCH_STATE ;
72	sc_signal<Tprediction_ptr_t > * in_PREDICT_BRANCH_UPDATE_PREDICTION_ID ;
73	sc_signal<Tinst_ifetch_ptr_t> * in_PREDICT_INST_IFETCH_PTR ;
74	sc_signal<Tcontrol_t > * in_EVENT_VAL ;
75	sc_signal<Tcontrol_t > * out_EVENT_ACK ;
76	sc_signal<Tgeneral_address_t> * in_EVENT_ADDRESS ;
77	sc_signal<Tgeneral_address_t> * in_EVENT_ADDRESS_NEXT ;
78	sc_signal<Tcontrol_t > * in_EVENT_ADDRESS_NEXT_VAL ;
79	sc_signal<Tcontrol_t > * in_EVENT_IS_DS_TAKE ;
80
81	ALLOC0_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t );
82	ALLOC0_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t );
83	ALLOC0_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t);
84	ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
85	ALLOC0_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
86	ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t );
87	ALLOC0_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
88	ALLOC0_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t );
89	ALLOC0_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t );
90	ALLOC0_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t);
91	ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t);
92	ALLOC0_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t );
93	ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t);
94	ALLOC0_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t );
95	ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
96	ALLOC0_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
97	//ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT ," in_PREDICT_BRANCH_IS_CURRENT ",Tcontrol_t );
98	ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t );
99	ALLOC0_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
100	ALLOC0_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t );
101	ALLOC0_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t );
102	ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t);
103	ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t);
104	ALLOC0_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t );
105	ALLOC0_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t );
106
107	/********************************************************
108	* Instanciation
109	********************************************************/
110
111	msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str());
112
113	((_Address_management->in_CLOCK)) ((in_CLOCK));
114	((_Address_management->in_NRESET)) ((in_NRESET));
115
116	INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_VAL );
117	INSTANCE0_SC_SIGNAL (_Address_management, in_ADDRESS_ACK );
118	INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS );
119	INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction);
120	if (_param->_have_port_inst_ifetch_ptr)
121	INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR );
122	INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE );
123	if (_param->_have_port_depth)
124	INSTANCE0_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
125	INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_VAL );
126	INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_ACK );
127	INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS );
128	INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT );
129	INSTANCE0_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE );
130	INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT );
131	INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE );
132	INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction);
133	if (_param->_have_port_inst_ifetch_ptr)
134	INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR );
135	//INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT );
136	INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE );
137	if (_param->_have_port_depth)
138	INSTANCE0_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
139	INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_VAL );
140	INSTANCE0_SC_SIGNAL (_Address_management,out_EVENT_ACK );
141	INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS );
142	INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT );
143	INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL );
144	INSTANCE0_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE );
145
146	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
147
148	Time * _time = new Time();
149
150	/********************************************************
151	* Simulation - Begin
152	********************************************************/
153
154	// Initialisation
155
156	const uint32_t seed = 0;
157	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
158
159	srand(seed);
160
161	const int32_t percent_transaction_address = 100;
162	const int32_t percent_transaction_predict = 100;
163	const int32_t percent_transaction_event = 0;
164
165	SC_START(0);
166	LABEL("Initialisation");
167
168	LABEL("Reset");
169
170	in_ADDRESS_ACK->write(0);
171	out_PREDICT_VAL->write(0);
172	in_EVENT_VAL ->write(0);
173
174	in_NRESET->write(0);
175	SC_START(5);
176	in_NRESET->write(1);
177
178	LABEL("Test Reset");
179
180	TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false);
181	TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction
182	TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event
183
184	#ifdef SELFTEST
185	uint32_t jump = 7 ;// packet
186	uint32_t nb_packet = 1;
187
188	Tcontrol_t a_val = false;
189	Tcontrol_t c_val = false;
190	Tcontrol_t n_val = true ;
191	Tcontrol_t nn_val = false;
192
193	Tgeneral_data_t a_addr = 0x100>>2;
194	Tgeneral_data_t c_addr = 0x100>>2;
195	Tgeneral_data_t n_addr = 0x100>>2;
196	Tgeneral_data_t nn_addr = 0x100>>2;
197
198	Tcontrol_t a_enable [_param->_nb_instruction];
199	Tcontrol_t c_enable [_param->_nb_instruction];
200	Tcontrol_t n_enable [_param->_nb_instruction];
201
202	Tcontrol_t a_is_ds_take = 0;
203	Tcontrol_t c_is_ds_take = 0;
204	Tcontrol_t n_is_ds_take = 0;
205	Tcontrol_t nn_is_ds_take = 0;
206
207	n_enable [0] = 1;
208	for (uint32_t i=1; i<_param->_nb_instruction; i++)
209	n_enable [i] = 0;
210
211	LABEL("Send Reset");
212	// do
213	// {
214	// in_EVENT_VAL ->write(1);
215	// in_EVENT_ADDRESS ->write(n_addr);
216	// in_EVENT_ADDRESS_NEXT ->write(nn_addr);
217	// in_EVENT_ADDRESS_NEXT_VAL->write(0);
218	// in_EVENT_IS_DS_TAKE ->write(0);
219	// SC_START(1);
220	// } while (out_EVENT_ACK->read() == false);
221	// in_EVENT_VAL ->write(0);
222
223	n_val = 1;
224
225	LABEL("Loop of Test");
226
227	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
228	{
229	LABEL("Iteration %d",iteration);
230
231	// PREDICT
232	{
233	in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict);
234
235	SC_START(0);
236
237	Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read();
238
239	uint32_t begin = addr%_param->_nb_instruction;
240	uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1);
241	Tcontrol_t take = (nb_packet%jump)==0;
242
243	if (take)
244	addr += 0x100;
245	else
246	addr += end-begin+1;
247
248	for (uint32_t i=0; i<_param->_nb_instruction; i++)
249	in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end));
250	in_PREDICT_PC_NEXT ->write(addr);
251	in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take);
252	in_PREDICT_INST_IFETCH_PTR ->write(0);
253	// in_PREDICT_BRANCH_IS_CURRENT ->write(0);
254	in_PREDICT_BRANCH_STATE ->write(0);
255	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
256	}
257
258	// ADDRESS
259	{
260	in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address);
261	}
262
263	in_EVENT_VAL ->write((rand()%100)<percent_transaction_event );
264	in_EVENT_ADDRESS ->write(0x77);
265	in_EVENT_ADDRESS_NEXT ->write(0x171);
266	Tcontrol_t next_val = rand()%2;
267	in_EVENT_ADDRESS_NEXT_VAL->write(next_val);
268	in_EVENT_IS_DS_TAKE ->write(next_val);
269
270	//-------------------------------------------------
271	SC_START(0);
272	//-------------------------------------------------
273
274	if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
275	{
276	LABEL("PREDICT : Transaction accepted");
277
278	if (c_val)
279	TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr );
280	TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr );
281	TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take);
282
283	nn_val = true;
284	nn_addr = in_PREDICT_PC_NEXT ->read();
285	nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read();
286
287	for (uint32_t i=0; i<_param->_nb_instruction; i++)
288	n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
289
290	LABEL(" * nn_addr : %.8x",nn_addr);
291	}
292
293	if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read())
294	{
295	LABEL("ADDRESS : Transaction accepted");
296	LABEL(" * address wait : %.8x",a_addr);
297
298	TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),a_addr-a_addr%_param->_nb_instruction);
299	for (uint32_t i=0; i<_param->_nb_instruction; i++)
300	TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),a_enable[i]);
301	if (_param->_have_port_inst_ifetch_ptr)
302	TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0);
303	TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0);
304	if (_param->_have_port_depth)
305	TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0);
306
307	a_val = 0;
308	nb_packet ++;
309	}
310
311	{
312	string str_a_enable = "";
313	string str_c_enable = "";
314	string str_n_enable = "";
315
316	for (uint32_t i=0; i<_param->_nb_instruction; i++)
317	{
318	str_a_enable += " " + toString(a_enable [i]);
319	str_c_enable += " " + toString(c_enable [i]);
320	str_n_enable += " " + toString(n_enable [i]);
321	}
322
323	LABEL("----[ Before ]---------------------");
324	LABEL(" * nb_packet : %d",nb_packet);
325	LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str());
326	LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str());
327	LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str());
328	LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr);
329	LABEL("-----------------------------------");
330	}
331
332	if (not a_val)
333	{
334	if (c_val and n_val and nn_val)
335	{
336	a_val = 1;
337	c_val = 0;
338	a_addr = c_addr;
339	a_is_ds_take = c_is_ds_take;
340
341	for (uint32_t i=0; i<_param->_nb_instruction; i++)
342	a_enable [i] = c_enable [i];
343	}
344	}
345
346	if (not c_val)
347	{
348	c_val = n_val;
349	if (n_val)
350	{
351	c_addr = n_addr;
352	c_is_ds_take = n_is_ds_take;
353
354	for (uint32_t i=0; i<_param->_nb_instruction; i++)
355	c_enable [i] = n_enable [i];
356	}
357	n_val = 0;
358	}
359
360	if (not n_val)
361	{
362	n_val = nn_val;
363	if (nn_val)
364	{
365	n_addr = nn_addr;
366	n_is_ds_take = nn_is_ds_take;
367
368	// for (uint32_t i=0; i<_param->_nb_instruction; i++)
369	// n_enable [i] = nn_enable [i];
370	}
371	nn_val = 0;
372	}
373
374	if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
375	{
376	LABEL("EVENT : Transaction accepted");
377
378	a_val = false;
379	c_val = false;
380	n_val = true;
381	n_addr = in_EVENT_ADDRESS ->read();
382	n_is_ds_take = in_EVENT_IS_DS_TAKE ->read();
383	nn_val = in_EVENT_ADDRESS_NEXT_VAL->read();
384	nn_addr = in_EVENT_ADDRESS_NEXT ->read();
385	nn_is_ds_take= false;
386	// nn_val = false;
387	// n_is_ds_take = 0;
388
389	n_enable [0] = 1;
390	for (uint32_t i=1; i<_param->_nb_instruction; i++)
391	n_enable [i] = 0;
392	}
393
394
395	{
396	string str_a_enable = "";
397	string str_c_enable = "";
398	string str_n_enable = "";
399
400	for (uint32_t i=0; i<_param->_nb_instruction; i++)
401	{
402	str_a_enable += " " + toString(a_enable [i]);
403	str_c_enable += " " + toString(c_enable [i]);
404	str_n_enable += " " + toString(n_enable [i]);
405	}
406
407	LABEL("----[ After ]----------------------");
408	LABEL(" * nb_packet : %d",nb_packet);
409	LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str());
410	LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str());
411	LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str());
412	LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr);
413	LABEL("-----------------------------------");
414	}
415
416	SC_START(1);
417	}
418	#else
419	SC_START(100);
420	#endif // SELFTEST
421
422	/********************************************************
423	* Simulation - End
424	********************************************************/
425
426	TEST_OK ("End of Simulation");
427	delete _time;
428
429	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
430
431	delete in_CLOCK;
432	delete in_NRESET;
433
434	delete out_ADDRESS_VAL ;
435	delete in_ADDRESS_ACK ;
436	delete out_ADDRESS_INSTRUCTION_ADDRESS ;
437	delete [] out_ADDRESS_INSTRUCTION_ENABLE ;
438	delete out_ADDRESS_INST_IFETCH_PTR ;
439	delete out_ADDRESS_BRANCH_STATE ;
440	delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
441	delete out_PREDICT_VAL ;
442	delete in_PREDICT_ACK ;
443	delete out_PREDICT_PC_PREVIOUS ;
444	delete out_PREDICT_PC_CURRENT ;
445	delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ;
446	delete in_PREDICT_PC_NEXT ;
447	delete in_PREDICT_PC_NEXT_IS_DS_TAKE ;
448	delete [] in_PREDICT_INSTRUCTION_ENABLE ;
449	delete in_PREDICT_INST_IFETCH_PTR ;
450	//delete in_PREDICT_BRANCH_IS_CURRENT ;
451	delete in_PREDICT_BRANCH_STATE ;
452	delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
453	delete in_EVENT_VAL ;
454	delete out_EVENT_ACK ;
455	delete in_EVENT_ADDRESS ;
456	delete in_EVENT_ADDRESS_NEXT ;
457	delete in_EVENT_ADDRESS_NEXT_VAL ;
458	delete in_EVENT_IS_DS_TAKE ;
459	#endif
460
461	delete _Address_management;
462	#ifdef STATISTICS
463	delete _parameters_statistics;
464	#endif
465	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp @ 131

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