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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 16 years ago
Almost complete design with Test and test platform
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1	/*
2	* $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9
10	#define NB_ITERATION 1024
11	#define CYCLE_MAX (128*NB_ITERATION)
12
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h"
14	#include "Common/include/Test.h"
15	#include "Behavioural/include/Allocation.h"
16
17	void test (string name,
18	morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param)
19	{
20	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
21
22	#ifdef STATISTICS
23	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
24	#endif
25
26	Tusage_t _usage = USE_ALL;
27
28	// _usage = usage_unset(_usage,USE_SYSTEMC );
29	// _usage = usage_unset(_usage,USE_VHDL );
30	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
31	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
32	// _usage = usage_unset(_usage,USE_POSITION );
33	// _usage = usage_unset(_usage,USE_STATISTICS );
34	// _usage = usage_unset(_usage,USE_INFORMATION );
35
36	Address_management * _Address_management = new Address_management
37	(name.c_str(),
38	#ifdef STATISTICS
39	_parameters_statistics,
40	#endif
41	_param,
42	_usage);
43
44	#ifdef SYSTEMC
45	/*********************************************************************
46	* Déclarations des signaux
47	*********************************************************************/
48	string rename;
49
50	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
51	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
52
53	ALLOC_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t );
54	ALLOC_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t );
55	ALLOC_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t);
56	ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
57	ALLOC_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
58	ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t );
59	ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
60	ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t );
61	ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t );
62	ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t);
63	ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t);
64	ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t );
65	ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t);
66	ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t );
67	ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
68	ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
69	ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t );
70	ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
71	ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t );
72	ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t );
73	ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t);
74	ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t);
75	ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t );
76	ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t );
77
78	/********************************************************
79	* Instanciation
80	********************************************************/
81
82	msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str());
83
84	((_Address_management->in_CLOCK)) ((in_CLOCK));
85	((_Address_management->in_NRESET)) ((in_NRESET));
86
87	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_VAL );
88	INSTANCE_SC_SIGNAL (_Address_management, in_ADDRESS_ACK );
89	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS );
90	INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction);
91	if (_param->_have_port_inst_ifetch_ptr)
92	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR );
93	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE );
94	if (_param->_have_port_depth)
95	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
96	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL );
97	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_ACK );
98	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS );
99	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT );
100	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE );
101	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT );
102	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE );
103	INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction);
104	if (_param->_have_port_inst_ifetch_ptr)
105	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR );
106	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE );
107	if (_param->_have_port_depth)
108	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
109	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL );
110	INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK );
111	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS );
112	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT );
113	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL );
114	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE );
115
116	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
117
118	Time * _time = new Time();
119
120	/********************************************************
121	* Simulation - Begin
122	********************************************************/
123
124	// Initialisation
125
126	const uint32_t seed = 0;
127	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
128
129	srand(seed);
130
131	const int32_t percent_transaction_address = 75;
132	const int32_t percent_transaction_predict = 75;
133	const int32_t percent_transaction_event = 5;
134
135	SC_START(0);
136	LABEL("Initialisation");
137
138	LABEL("Reset");
139
140	in_ADDRESS_ACK->write(0);
141	out_PREDICT_VAL->write(0);
142	in_EVENT_VAL ->write(0);
143
144	in_NRESET->write(0);
145	SC_START(5);
146	in_NRESET->write(1);
147
148	LABEL("Test Reset");
149
150	TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false);
151	TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction
152	TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event
153
154	uint32_t jump = 7 ;// packet
155	uint32_t nb_packet = 1;
156
157	Tcontrol_t c_val = false;
158	Tcontrol_t n_val = false;
159	Tcontrol_t nn_val = false;
160
161	Tgeneral_data_t c_addr = 0x100>>2;
162	Tgeneral_data_t n_addr = 0x100>>2;
163	Tgeneral_data_t nn_addr = 0x100>>2;
164
165	Tcontrol_t c_enable [_param->_nb_instruction];
166	Tcontrol_t n_enable [_param->_nb_instruction];
167
168	Tcontrol_t c_is_ds_take = 0;
169	Tcontrol_t n_is_ds_take = 0;
170	Tcontrol_t nn_is_ds_take = 0;
171
172	c_enable [0] = 1;
173	for (uint32_t i=1; i<_param->_nb_instruction; i++)
174	c_enable [i] = 0;
175
176	LABEL("Send Reset");
177	// do
178	// {
179	// in_EVENT_VAL ->write(1);
180	// in_EVENT_ADDRESS ->write(n_addr);
181	// in_EVENT_ADDRESS_NEXT ->write(nn_addr);
182	// in_EVENT_ADDRESS_NEXT_VAL->write(0);
183	// in_EVENT_IS_DS_TAKE ->write(0);
184	// SC_START(1);
185	// } while (out_EVENT_ACK->read() == false);
186	// in_EVENT_VAL ->write(0);
187
188	n_val = 1;
189
190	LABEL("Loop of Test");
191
192	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
193	{
194	LABEL("Iteration %d",iteration);
195
196	// PREDICT
197	{
198	in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict);
199
200	SC_START(0);
201
202	Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read();
203
204	uint32_t begin = addr%_param->_nb_instruction;
205	uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1);
206	Tcontrol_t take = (nb_packet%jump)==0;
207
208	if (take)
209	addr += 0x100;
210	else
211	addr += end-begin+1;
212
213	for (uint32_t i=0; i<_param->_nb_instruction; i++)
214	in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end));
215	in_PREDICT_PC_NEXT ->write(addr);
216	in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take);
217	in_PREDICT_INST_IFETCH_PTR ->write(0);
218	in_PREDICT_BRANCH_STATE ->write(0);
219	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
220	}
221
222	// ADDRESS
223	{
224	in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address);
225	}
226
227	in_EVENT_VAL ->write((rand()%100)<percent_transaction_event );
228	in_EVENT_ADDRESS ->write(0x77);
229	in_EVENT_ADDRESS_NEXT ->write(0x171);
230	Tcontrol_t next_val = rand()%2;
231	in_EVENT_ADDRESS_NEXT_VAL->write(next_val);
232	in_EVENT_IS_DS_TAKE ->write(next_val);
233
234	//-------------------------------------------------
235	SC_START(0);
236	//-------------------------------------------------
237
238	if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
239	{
240	LABEL("PREDICT : Transaction accepted");
241
242	if (c_val)
243	TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr );
244	TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr );
245	TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take);
246
247	nn_val = true;
248	nn_addr = in_PREDICT_PC_NEXT ->read();
249	nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read();
250
251	for (uint32_t i=0; i<_param->_nb_instruction; i++)
252	n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
253	}
254
255	if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read())
256	{
257	LABEL("ADDRESS : Transaction accepted");
258	LABEL(" * address wait : %.8x",c_addr);
259
260	TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),c_addr);
261	for (uint32_t i=0; i<_param->_nb_instruction; i++)
262	TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),c_enable[i]);
263	if (_param->_have_port_inst_ifetch_ptr)
264	TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0);
265	TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0);
266	if (_param->_have_port_depth)
267	TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0);
268
269	c_val = 0;
270	nb_packet ++;
271	}
272
273
274	if (not c_val)
275	{
276	if (n_val and nn_val)
277	{
278	c_val = 1;
279	c_addr = n_addr;
280	c_is_ds_take = n_is_ds_take;
281
282	for (uint32_t i=0; i<_param->_nb_instruction; i++)
283	c_enable [i] = n_enable [i];
284
285	n_val = 1;
286	n_addr = nn_addr;
287	n_is_ds_take = nn_is_ds_take;
288
289	nn_val = 0;
290	}
291	}
292
293	if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
294	{
295	LABEL("EVENT : Transaction accepted");
296
297	c_val = false;
298	n_val = true;
299	n_addr = in_EVENT_ADDRESS ->read();
300	n_is_ds_take = in_EVENT_IS_DS_TAKE ->read();
301	nn_val = in_EVENT_ADDRESS_NEXT_VAL->read();
302	nn_addr = in_EVENT_ADDRESS_NEXT ->read();
303	nn_is_ds_take= false;
304	// nn_val = false;
305	// n_is_ds_take = 0;
306
307	n_enable [0] = 1;
308	for (uint32_t i=1; i<_param->_nb_instruction; i++)
309	n_enable [i] = 0;
310	}
311
312
313	{
314	string str_c_enable = "";
315	string str_n_enable = "";
316
317	for (uint32_t i=0; i<_param->_nb_instruction; i++)
318	{
319	str_c_enable += " " + toString(c_enable [i]);
320	str_n_enable += " " + toString(n_enable [i]);
321	}
322
323	LABEL("-----------------------------------");
324	LABEL(" * nb_packet : %d",nb_packet);
325	LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str());
326	if (nn_val)
327	{
328	LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str());
329	}
330	else
331	{
332	LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr );
333	}
334	LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr);
335	LABEL("-----------------------------------");
336	}
337
338	SC_START(1);
339
340	}
341
342	/********************************************************
343	* Simulation - End
344	********************************************************/
345
346	TEST_OK ("End of Simulation");
347	delete _time;
348
349	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
350
351	delete in_CLOCK;
352	delete in_NRESET;
353
354	delete out_ADDRESS_VAL ;
355	delete in_ADDRESS_ACK ;
356	delete out_ADDRESS_INSTRUCTION_ADDRESS ;
357	delete [] out_ADDRESS_INSTRUCTION_ENABLE ;
358	delete out_ADDRESS_INST_IFETCH_PTR ;
359	delete out_ADDRESS_BRANCH_STATE ;
360	delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
361	delete out_PREDICT_VAL ;
362	delete in_PREDICT_ACK ;
363	delete out_PREDICT_PC_PREVIOUS ;
364	delete out_PREDICT_PC_CURRENT ;
365	delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ;
366	delete in_PREDICT_PC_NEXT ;
367	delete in_PREDICT_PC_NEXT_IS_DS_TAKE ;
368	delete [] in_PREDICT_INSTRUCTION_ENABLE ;
369	delete in_PREDICT_INST_IFETCH_PTR ;
370	delete in_PREDICT_BRANCH_STATE ;
371	delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
372	delete in_EVENT_VAL ;
373	delete out_EVENT_ACK ;
374	delete in_EVENT_ADDRESS ;
375	delete in_EVENT_ADDRESS_NEXT ;
376	delete in_EVENT_ADDRESS_NEXT_VAL ;
377	delete in_EVENT_IS_DS_TAKE ;
378	#endif
379
380	delete _Address_management;
381	#ifdef STATISTICS
382	delete _parameters_statistics;
383	#endif
384	}

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