1 | /* |
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2 | * $Id: Address_management_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | */ |
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7 | |
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8 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h" |
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9 | #include "Behavioural/include/Allocation.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace ifetch_unit { |
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17 | namespace address_management { |
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18 | |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Address_management::allocation" |
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23 | void Address_management::allocation ( |
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24 | #ifdef STATISTICS |
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25 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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26 | #else |
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27 | void |
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28 | #endif |
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29 | ) |
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30 | { |
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31 | log_printf(FUNC,Address_management,FUNCTION,"Begin"); |
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32 | |
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33 | _component = new Component (_usage); |
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34 | |
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35 | Entity * entity = _component->set_entity (_name |
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36 | ,"Address_management" |
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37 | #ifdef POSITION |
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38 | ,COMBINATORY |
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39 | #endif |
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40 | ); |
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41 | |
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42 | _interfaces = entity->set_interfaces(); |
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43 | |
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44 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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45 | { |
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46 | Interface * interface = _interfaces->set_interface("" |
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47 | #ifdef POSITION |
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48 | ,IN |
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49 | ,SOUTH, |
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50 | "Generalist interface" |
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51 | #endif |
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52 | ); |
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53 | |
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54 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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55 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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56 | } |
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57 | |
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58 | // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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59 | { |
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60 | ALLOC_INTERFACE("address", OUT, SOUTH, "Access at request icache."); |
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61 | |
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62 | ALLOC_VALACK_OUT (out_ADDRESS_VAL ,VAL); |
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63 | ALLOC_VALACK_IN ( in_ADDRESS_ACK ,ACK); |
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64 | ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS ,"instruction_address" ,Tgeneral_address_t,_param->_size_instruction_address ); |
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65 | ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr ); |
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66 | ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state ); |
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67 | ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); |
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68 | } |
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69 | |
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70 | { |
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71 | ALLOC1_INTERFACE("address", OUT, SOUTH, "Access at request icache.",_param->_nb_instruction); |
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72 | |
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73 | ALLOC1_SIGNAL_OUT(out_ADDRESS_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); |
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74 | } |
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75 | |
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76 | // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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77 | { |
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78 | ALLOC_INTERFACE("predict", IN, NORTH, "Request the prediction unit."); |
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79 | |
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80 | ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL); |
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81 | ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK); |
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82 | ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); |
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83 | ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); |
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84 | ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); |
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85 | ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); |
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86 | ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); |
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87 | ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); |
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88 | ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); |
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89 | ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); |
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90 | } |
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91 | { |
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92 | ALLOC1_INTERFACE("predict", IN, NORTH, "Request the prediction unit.",_param->_nb_instruction); |
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93 | |
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94 | ALLOC1_SIGNAL_IN (in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); |
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95 | } |
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96 | |
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97 | // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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98 | { |
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99 | ALLOC_INTERFACE("event", IN, SOUTH, "Event (miss, exception ...)"); |
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100 | |
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101 | ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); |
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102 | ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); |
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103 | ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); |
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104 | ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); |
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105 | ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1); |
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106 | ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); |
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107 | } |
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108 | |
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109 | // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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110 | if (usage_is_set(_usage,USE_SYSTEMC)) |
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111 | { |
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112 | reg_PC_CURRENT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction]; |
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113 | reg_PC_NEXT_INSTRUCTION_ENABLE = new Tcontrol_t [_param->_nb_instruction]; |
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114 | } |
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115 | |
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116 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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117 | #ifdef POSITION |
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118 | if (usage_is_set(_usage,USE_POSITION)) |
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119 | _component->generate_file(); |
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120 | #endif |
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121 | |
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122 | log_printf(FUNC,Address_management,FUNCTION,"End"); |
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123 | }; |
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124 | |
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125 | }; // end namespace address_management |
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126 | }; // end namespace ifetch_unit |
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127 | }; // end namespace front_end |
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128 | }; // end namespace multi_front_end |
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129 | }; // end namespace core |
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130 | |
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131 | }; // end namespace behavioural |
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132 | }; // end namespace morpheo |
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