source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp @ 136

Last change on this file since 136 was 136, checked in by rosiere, 15 years ago

1) Add new algo in ifetch queue
2) Add Cancel bit
3) new config
  • Property svn:keywords set to Id
File size: 14.4 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id: Address_management_transition.cpp 136 2009-10-20 18:52:15Z rosiere $
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace ifetch_unit {
17namespace address_management {
18
19
20#undef  FUNCTION
21#define FUNCTION "Address_management::transition"
22  void Address_management::transition (void)
23  {
24    log_begin(Address_management,FUNCTION);
25    log_function(Address_management,FUNCTION,_name.c_str());
26
27    if (PORT_READ(in_NRESET) == 0)
28      {
29        // nothing is valid
30        reg_PC_ACCESS_VAL                               = 0;
31        reg_PC_ACCESS                                   = 0;// not necessary
32        reg_PC_ACCESS_IS_DS_TAKE                        = 0;// not necessary
33        for (uint32_t i=0; i<_param->_nb_instruction; i++)
34        reg_PC_ACCESS_INSTRUCTION_ENABLE [i]            = 0;// not necessary
35        reg_PC_ACCESS_INST_IFETCH_PTR                   = 0;// not necessary
36        reg_PC_ACCESS_BRANCH_STATE                      = 0;// not necessary
37        reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID       = 0;// not necessary
38
39        reg_PC_CURRENT_VAL                              = 0;
40        reg_PC_CURRENT                                  = 0;// not necessary
41        reg_PC_CURRENT_IS_DS_TAKE                       = 0;// not necessary
42        for (uint32_t i=0; i<_param->_nb_instruction; i++)
43        reg_PC_CURRENT_INSTRUCTION_ENABLE [i]           = 0;// not necessary
44        reg_PC_CURRENT_INST_IFETCH_PTR                  = 0;// not necessary
45        reg_PC_CURRENT_BRANCH_STATE                     = 0;// not necessary
46        reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID      = 0;// not necessary
47
48        reg_PC_NEXT_VAL                                 = 1;
49        reg_PC_NEXT                                     = 0x100>>2;
50        reg_PC_NEXT_IS_DS_TAKE                          = 0;
51        uint32_t index = reg_PC_NEXT % _param->_nb_instruction;
52        for (uint32_t i=0; i<_param->_nb_instruction; i++)
53        reg_PC_NEXT_INSTRUCTION_ENABLE [i]              = 0;
54        reg_PC_NEXT_INSTRUCTION_ENABLE [index]          = 1;
55        reg_PC_NEXT_INST_IFETCH_PTR                     = 0;
56        reg_PC_NEXT_BRANCH_STATE                        = 0;
57        reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID         = 0;
58
59        reg_PC_NEXT_NEXT_VAL                            = 0;
60        reg_PC_NEXT_NEXT                                = 0;// not necessary
61        reg_PC_NEXT_NEXT_IS_DS_TAKE                     = 0;// not necessary
62      }
63    else
64      {
65        // =========================================
66        // ===== PREDICT ===========================
67        // =========================================
68        if (PORT_READ(in_PREDICT_ACK) and internal_PREDICT_VAL)
69          {
70            log_printf(TRACE,Address_management,FUNCTION,"  * PREDICT");
71
72            bool               branch_is_current            = reg_PC_NEXT_IS_DS_TAKE;
73            Tbranch_state_t    branch_state                 =                                      PORT_READ(in_PREDICT_BRANCH_STATE               );
74            Tprediction_ptr_t  branch_update_prediction_id  = (_param->_have_port_depth          )?PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID):0;
75            Tinst_ifetch_ptr_t inst_ifetch_ptr              = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_PREDICT_INST_IFETCH_PTR            ):0;
76
77            log_printf(TRACE,Address_management,FUNCTION,"    * branch_is_current           : %d",branch_is_current          );
78            log_printf(TRACE,Address_management,FUNCTION,"    * branch_state                : %d",branch_state               );
79            log_printf(TRACE,Address_management,FUNCTION,"    * branch_update_prediction_id : %d",branch_update_prediction_id);
80            log_printf(TRACE,Address_management,FUNCTION,"    * inst_ifetch_ptr             : %d",inst_ifetch_ptr            );
81
82            if (branch_is_current)
83              {
84                reg_PC_CURRENT_INST_IFETCH_PTR             = inst_ifetch_ptr            ;
85                reg_PC_CURRENT_BRANCH_STATE                = branch_state               ;
86                reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = branch_update_prediction_id;
87              }
88            else
89              {
90                reg_PC_NEXT_INST_IFETCH_PTR             = inst_ifetch_ptr            ;
91                reg_PC_NEXT_BRANCH_STATE                = branch_state               ;
92                reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = branch_update_prediction_id;
93              }
94
95            for (uint32_t i=0; i<_param->_nb_instruction; i++)
96            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
97           
98            reg_PC_NEXT_NEXT_VAL                    = 1; // address is valid
99            reg_PC_NEXT_NEXT                        = PORT_READ(in_PREDICT_PC_NEXT                    );
100            reg_PC_NEXT_NEXT_IS_DS_TAKE             = PORT_READ(in_PREDICT_PC_NEXT_IS_DS_TAKE         );
101
102#ifdef STATISTICS
103            if (usage_is_set(_usage,USE_STATISTICS))
104              (*_stat_nb_transaction_predict) ++;
105#endif
106          }
107
108        // =========================================
109        // ===== ADDRESS ===========================
110        // =========================================
111        // transaction with icache
112        if (internal_ADDRESS_VAL and PORT_READ(in_ADDRESS_ACK))
113          {
114
115            reg_PC_ACCESS_VAL = 0;
116#ifdef STATISTICS
117            if (usage_is_set(_usage,USE_STATISTICS))
118              {
119                  (*_stat_nb_transaction_address) ++;
120                 
121                  for (uint32_t i=0; i<_param->_nb_instruction; i++)
122                    if (reg_PC_ACCESS_INSTRUCTION_ENABLE [i] == true)
123                      (*_stat_sum_packet_size) ++;
124                }
125#endif
126          }
127
128        // =========================================
129        // ===== Shift Register ====================
130        // =========================================
131       
132        // Shift register
133        if (reg_PC_NEXT_NEXT_VAL and reg_PC_NEXT_VAL and reg_PC_CURRENT_VAL and not reg_PC_ACCESS_VAL)
134          {
135            log_printf(TRACE,Address_management,FUNCTION,"  * New PC_ACCESS");
136
137            reg_PC_ACCESS_VAL  = 1; // new request
138            reg_PC_CURRENT_VAL = 0; // invalid current
139           
140            reg_PC_ACCESS                             = reg_PC_CURRENT                            ;
141            reg_PC_ACCESS_IS_DS_TAKE                  = reg_PC_CURRENT_IS_DS_TAKE                 ;
142            reg_PC_ACCESS_INST_IFETCH_PTR             = reg_PC_CURRENT_INST_IFETCH_PTR            ;
143            reg_PC_ACCESS_BRANCH_STATE                = reg_PC_CURRENT_BRANCH_STATE               ;
144            reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID = reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID;
145           
146            for (uint32_t i=0; i<_param->_nb_instruction; i++)
147              reg_PC_ACCESS_INSTRUCTION_ENABLE [i] = reg_PC_CURRENT_INSTRUCTION_ENABLE [i];
148          }
149       
150//      if (not reg_PC_CURRENT_VAL and reg_PC_NEXT_VAL)
151        if (reg_PC_NEXT_NEXT_VAL and reg_PC_NEXT_VAL and not reg_PC_CURRENT_VAL)
152          {
153            log_printf(TRACE,Address_management,FUNCTION,"  * New PC_CURRENT");
154
155            reg_PC_CURRENT_VAL = 1; // new PC_CURRENT if PC_NEXT is valid
156            reg_PC_NEXT_VAL    = 0; // invalid next
157
158            reg_PC_CURRENT                             = reg_PC_NEXT                            ;
159            reg_PC_CURRENT_IS_DS_TAKE                  = reg_PC_NEXT_IS_DS_TAKE                 ;
160            reg_PC_CURRENT_INST_IFETCH_PTR             = reg_PC_NEXT_INST_IFETCH_PTR            ;
161            reg_PC_CURRENT_BRANCH_STATE                = reg_PC_NEXT_BRANCH_STATE               ;
162            reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;
163           
164            for (uint32_t i=0; i<_param->_nb_instruction; i++)
165              reg_PC_CURRENT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_INSTRUCTION_ENABLE [i];
166          }
167
168        if (reg_PC_NEXT_NEXT_VAL and not reg_PC_NEXT_VAL)
169          {
170            log_printf(TRACE,Address_management,FUNCTION,"  * New PC_NEXT");
171
172            reg_PC_NEXT_VAL      = 1; // new PC_NEXT if PC_NEXT_NEXT is valid
173            reg_PC_NEXT_NEXT_VAL = 0; // invalid next_next
174           
175            reg_PC_NEXT                             = reg_PC_NEXT_NEXT                            ;
176            reg_PC_NEXT_IS_DS_TAKE                  = reg_PC_NEXT_NEXT_IS_DS_TAKE                 ;
177//          reg_PC_NEXT_INST_IFETCH_PTR             = reg_PC_NEXT_NEXT_INST_IFETCH_PTR            ;
178//          reg_PC_NEXT_BRANCH_STATE                = reg_PC_NEXT_NEXT_BRANCH_STATE               ;
179//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;
180           
181//          for (uint32_t i=0; i<_param->_nb_instruction; i++)
182//            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE [i];
183          }
184
185        // =========================================
186        // ===== EVENT =============================
187        // =========================================
188
189        // Event is after shift register : because, it's to write in pc_next and in not pc_current
190
191        if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK)
192          {
193            log_printf(TRACE,Address_management,FUNCTION,"  * EVENT : Transaction");
194            log_printf(TRACE,Address_management,FUNCTION,"    * IS_DS_TAKE       : %d"  ,PORT_READ(in_EVENT_IS_DS_TAKE      ));
195            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS          : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS         ),PORT_READ(in_EVENT_ADDRESS         )<<2);
196            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT    ),PORT_READ(in_EVENT_ADDRESS_NEXT    )<<2);
197            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT_VAL : %d"  ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL));
198
199            reg_PC_ACCESS_VAL                       = 0;
200            reg_PC_CURRENT_VAL                      = 0;
201            reg_PC_NEXT_VAL                         = 1;
202            reg_PC_NEXT                             = PORT_READ(in_EVENT_ADDRESS);
203            // Event is never is ds_take :
204            //  * branch miss speculation : can't be place a branch in delay slot
205            //  * load   miss speculation : the load is execute, the event_address is the next address (also the destination of branch)
206            //  * exception               : goto the first instruction of exception handler (also is not in delay slot).
207
208            reg_PC_NEXT_IS_DS_TAKE                  = PORT_READ(in_EVENT_IS_DS_TAKE);
209//          reg_PC_NEXT_INST_IFETCH_PTR             = 0;
210            reg_PC_NEXT_BRANCH_STATE                = BRANCH_STATE_NONE;
211//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
212           
213            // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
214            uint32_t index = reg_PC_NEXT % _param->_nb_instruction;
215            for (uint32_t i=0; i<_param->_nb_instruction; i++)
216            reg_PC_NEXT_INSTRUCTION_ENABLE [i]      = 0;
217            reg_PC_NEXT_INSTRUCTION_ENABLE [index]  = 1;
218
219            reg_PC_NEXT_NEXT_VAL                    = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL);
220            reg_PC_NEXT_NEXT                        = PORT_READ(in_EVENT_ADDRESS_NEXT);
221            reg_PC_NEXT_NEXT_IS_DS_TAKE             = 0;//??
222
223            // Note : is_ds_take = address_next_val
224            // Because, is not ds take, can continue in sequence
225
226// #ifdef DEBUG_TEST
227//             if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE))
228//               throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take"));
229// #endif
230
231#ifdef STATISTICS
232            if (usage_is_set(_usage,USE_STATISTICS))
233              (*_stat_nb_transaction_event) ++;
234#endif
235          }
236      }
237
238#if defined(DEBUG) and DEBUG_Address_management and (DEBUG >= DEBUG_TRACE)
239    log_printf(TRACE,Address_management,FUNCTION,"  * Dump PC");
240    {
241      std::string instruction_enable;
242      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
243        instruction_enable += ((reg_PC_ACCESS_VAL)?(toString(reg_PC_ACCESS_INSTRUCTION_ENABLE [i])):"X") + " ";
244
245      log_printf(TRACE,Address_management,FUNCTION,"    * Access    : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
246                 reg_PC_ACCESS_VAL,
247                 reg_PC_ACCESS_IS_DS_TAKE,
248                 reg_PC_ACCESS,
249                 reg_PC_ACCESS<<2,
250                 reg_PC_ACCESS_BRANCH_STATE,
251                 reg_PC_ACCESS_INST_IFETCH_PTR,
252                 reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID,
253                 instruction_enable.c_str()
254                 );
255    }
256    {
257      std::string instruction_enable;
258      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
259        instruction_enable += ((reg_PC_CURRENT_VAL)?(toString(reg_PC_CURRENT_INSTRUCTION_ENABLE [i])):"X") + " ";
260
261      log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
262                 reg_PC_CURRENT_VAL,
263                 reg_PC_CURRENT_IS_DS_TAKE,
264                 reg_PC_CURRENT,
265                 reg_PC_CURRENT<<2,
266                 reg_PC_CURRENT_BRANCH_STATE,
267                 reg_PC_CURRENT_INST_IFETCH_PTR,
268                 reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID,
269                 instruction_enable.c_str()
270                 );
271    }
272    {
273      std::string instruction_enable;
274      for (uint32_t i=0; i<_param->_nb_instruction; ++i)
275        instruction_enable += ((reg_PC_NEXT_VAL)?(toString(reg_PC_NEXT_INSTRUCTION_ENABLE [i])):"X") + " ";
276
277      log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x) - %.2d %.2d %.2d - %s",
278                 reg_PC_NEXT_VAL,
279                 reg_PC_NEXT_IS_DS_TAKE,
280                 reg_PC_NEXT,
281                 reg_PC_NEXT<<2,
282                 reg_PC_NEXT_BRANCH_STATE,
283                 reg_PC_NEXT_INST_IFETCH_PTR,
284                 reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID,
285                 instruction_enable.c_str());
286    }
287    log_printf(TRACE,Address_management,FUNCTION,"    * Next_Next : %d %d 0x%.8x (%.8x)",
288               reg_PC_NEXT_NEXT_VAL,
289               reg_PC_NEXT_NEXT_IS_DS_TAKE,
290               reg_PC_NEXT_NEXT,
291               reg_PC_NEXT_NEXT<<2);   
292#endif
293
294#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
295    end_cycle ();
296#endif
297   
298    log_end(Address_management,FUNCTION);
299  };
300
301}; // end namespace address_management
302}; // end namespace ifetch_unit
303}; // end namespace front_end
304}; // end namespace multi_front_end
305}; // end namespace core
306
307}; // end namespace behavioural
308}; // end namespace morpheo             
309#endif
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