1 | #ifdef VHDL |
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2 | /* |
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3 | * $Id: Address_management_vhdl_body.cpp 135 2009-07-17 08:59:05Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace ifetch_unit { |
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17 | namespace address_management { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Address_management::vhdl_body" |
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22 | void Address_management::vhdl_body (Vhdl * & vhdl) |
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23 | { |
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24 | log_printf(FUNC,Address_management,FUNCTION,"Begin"); |
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25 | |
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26 | vhdl->set_body (0,""); |
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27 | vhdl->set_comment(0,"========================================="); |
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28 | vhdl->set_comment(0,"===== CONSTANT =========================="); |
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29 | vhdl->set_comment(0,"========================================="); |
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30 | vhdl->set_body (0,""); |
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31 | vhdl->set_body (0,"internal_EVENT_ACK <= '1';"); |
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32 | vhdl->set_body (0," out_EVENT_ACK <= internal_EVENT_ACK;"); |
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33 | |
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34 | vhdl->set_body (0,""); |
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35 | vhdl->set_comment(0,"========================================="); |
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36 | vhdl->set_comment(0,"===== TRANSITION ========================"); |
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37 | vhdl->set_comment(0,"========================================="); |
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38 | vhdl->set_body (0,""); |
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39 | |
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40 | vhdl->set_body (0,"TRANSITION : process (in_CLOCK)"); |
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41 | |
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42 | vhdl->set_body (0,""); |
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43 | vhdl->set_body (0,"variable var_PC_ACCESS_VAL : "+std_logic(1)+";"); |
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44 | vhdl->set_body (0,"variable var_PC_ACCESS : "+std_logic(_param->_size_instruction_address)+";"); |
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45 | vhdl->set_body (0,"variable var_PC_ACCESS_IS_DS_TAKE : "+std_logic(1)+";"); |
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46 | vhdl->set_body (0,"variable var_PC_ACCESS_INSTRUCTION_ENABLE : Tinstruction_enable;"); |
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47 | if (_param->_have_port_inst_ifetch_ptr) |
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48 | vhdl->set_body (0,"variable var_PC_ACCESS_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); |
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49 | vhdl->set_body (0,"variable var_PC_ACCESS_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); |
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50 | if (_param->_have_port_depth) |
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51 | vhdl->set_body (0,"variable var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); |
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52 | vhdl->set_body (0,""); |
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53 | vhdl->set_body (0,"variable var_PC_CURRENT_VAL : "+std_logic(1)+";"); |
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54 | vhdl->set_body (0,"variable var_PC_CURRENT : "+std_logic(_param->_size_instruction_address)+";"); |
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55 | vhdl->set_body (0,"variable var_PC_CURRENT_IS_DS_TAKE : "+std_logic(1)+";"); |
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56 | vhdl->set_body (0,"variable var_PC_CURRENT_INSTRUCTION_ENABLE : Tinstruction_enable;"); |
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57 | if (_param->_have_port_inst_ifetch_ptr) |
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58 | vhdl->set_body (0,"variable var_PC_CURRENT_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); |
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59 | vhdl->set_body (0,"variable var_PC_CURRENT_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); |
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60 | if (_param->_have_port_depth) |
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61 | vhdl->set_body (0,"variable var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); |
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62 | vhdl->set_body (0,""); |
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63 | vhdl->set_body (0,"variable var_PC_NEXT_VAL : "+std_logic(1)+";"); |
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64 | vhdl->set_body (0,"variable var_PC_NEXT : "+std_logic(_param->_size_instruction_address)+";"); |
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65 | vhdl->set_body (0,"variable var_PC_NEXT_IS_DS_TAKE : "+std_logic(1)+";"); |
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66 | vhdl->set_body (0,"variable var_PC_NEXT_INSTRUCTION_ENABLE : Tinstruction_enable;"); |
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67 | if (_param->_have_port_inst_ifetch_ptr) |
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68 | vhdl->set_body (0,"variable var_PC_NEXT_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); |
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69 | vhdl->set_body (0,"variable var_PC_NEXT_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); |
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70 | if (_param->_have_port_depth) |
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71 | vhdl->set_body (0,"variable var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); |
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72 | vhdl->set_body (0,""); |
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73 | vhdl->set_body (0,"variable var_PC_NEXT_NEXT_VAL : "+std_logic(1)+";"); |
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74 | vhdl->set_body (0,"variable var_PC_NEXT_NEXT : "+std_logic(_param->_size_instruction_address)+";"); |
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75 | vhdl->set_body (0,"variable var_PC_NEXT_NEXT_IS_DS_TAKE : "+std_logic(1)+";"); |
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76 | // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_INSTRUCTION_ENABLE : Tinstruction_enable;"); |
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77 | // if (_param->_have_port_inst_ifetch_ptr) |
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78 | // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); |
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79 | // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); |
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80 | // if (_param->_have_port_depth) |
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81 | // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); |
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82 | vhdl->set_body (0,""); |
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83 | vhdl->set_body (0,"begin -- TRANSITION"); |
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84 | vhdl->set_body (1,"if (in_CLOCK'event and in_CLOCK = '1')then"); |
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85 | vhdl->set_body (1,""); |
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86 | vhdl->set_body (2,"if (in_NRESET = '0') then"); |
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87 | vhdl->set_body (3,""); |
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88 | |
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89 | { |
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90 | vhdl->set_body (3,"reg_PC_ACCESS_VAL <= '0';"); |
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91 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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92 | vhdl->set_body (3,"reg_PC_ACCESS <= "+std_logic_cst(_param->_size_instruction_address,0)+";"); |
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93 | #endif |
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94 | vhdl->set_body (3,"reg_PC_CURRENT_VAL <= '0';"); |
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95 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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96 | vhdl->set_body (3,"reg_PC_CURRENT <= "+std_logic_cst(_param->_size_instruction_address,0)+";"); |
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97 | #endif |
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98 | vhdl->set_body (3,"reg_PC_NEXT_VAL <= '1';"); |
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99 | vhdl->set_body (3,"reg_PC_NEXT <= "+std_logic_cst(_param->_size_instruction_address,0x100>>2)+";"); |
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100 | vhdl->set_body (3,"reg_PC_NEXT_IS_DS_TAKE <= '0';"); |
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101 | uint32_t index = reg_PC_NEXT % _param->_nb_instruction; |
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102 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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103 | { |
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104 | std::string value = (i != index)?"'0'":"'1'"; |
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105 | vhdl->set_body (3,"reg_PC_NEXT_INSTRUCTION_ENABLE ("+toString(i)+") <= "+value+";"); |
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106 | } |
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107 | if (_param->_have_port_inst_ifetch_ptr) |
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108 | vhdl->set_body (3,"reg_PC_NEXT_INST_IFETCH_PTR <= "+std_logic_cst(_param->_size_inst_ifetch_ptr,0)+";"); |
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109 | vhdl->set_body (3,"reg_PC_NEXT_BRANCH_STATE <= "+std_logic_cst(_param->_size_branch_state ,0)+";"); |
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110 | if (_param->_have_port_depth) |
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111 | vhdl->set_body (3,"reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID <= "+std_logic_cst(_param->_size_depth ,0)+";"); |
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112 | vhdl->set_body (3,"reg_PC_NEXT_NEXT_VAL <= '0';"); |
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113 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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114 | vhdl->set_body (3,"reg_PC_NEXT_NEXT <= "+std_logic_cst(_param->_size_instruction_address,0)+";"); |
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115 | #endif |
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116 | } |
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117 | vhdl->set_body (3,""); |
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118 | vhdl->set_body (2,"else"); |
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119 | |
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120 | vhdl->set_body (3,"var_PC_ACCESS_VAL := reg_PC_ACCESS_VAL ;"); |
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121 | vhdl->set_body (3,"var_PC_ACCESS := reg_PC_ACCESS ;"); |
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122 | vhdl->set_body (3,"var_PC_ACCESS_IS_DS_TAKE := reg_PC_ACCESS_IS_DS_TAKE ;"); |
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123 | vhdl->set_body (3,"var_PC_ACCESS_INSTRUCTION_ENABLE := reg_PC_ACCESS_INSTRUCTION_ENABLE ;"); |
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124 | if (_param->_have_port_inst_ifetch_ptr) |
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125 | vhdl->set_body (3,"var_PC_ACCESS_INST_IFETCH_PTR := reg_PC_ACCESS_INST_IFETCH_PTR ;"); |
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126 | vhdl->set_body (3,"var_PC_ACCESS_BRANCH_STATE := reg_PC_ACCESS_BRANCH_STATE ;"); |
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127 | if (_param->_have_port_depth) |
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128 | vhdl->set_body (3,"var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID := reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID ;"); |
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129 | vhdl->set_body (3,""); |
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130 | vhdl->set_body (3,"var_PC_CURRENT_VAL := reg_PC_CURRENT_VAL ;"); |
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131 | vhdl->set_body (3,"var_PC_CURRENT := reg_PC_CURRENT ;"); |
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132 | vhdl->set_body (3,"var_PC_CURRENT_IS_DS_TAKE := reg_PC_CURRENT_IS_DS_TAKE ;"); |
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133 | vhdl->set_body (3,"var_PC_CURRENT_INSTRUCTION_ENABLE := reg_PC_CURRENT_INSTRUCTION_ENABLE ;"); |
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134 | if (_param->_have_port_inst_ifetch_ptr) |
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135 | vhdl->set_body (3,"var_PC_CURRENT_INST_IFETCH_PTR := reg_PC_CURRENT_INST_IFETCH_PTR ;"); |
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136 | vhdl->set_body (3,"var_PC_CURRENT_BRANCH_STATE := reg_PC_CURRENT_BRANCH_STATE ;"); |
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137 | if (_param->_have_port_depth) |
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138 | vhdl->set_body (3,"var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID := reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID ;"); |
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139 | vhdl->set_body (3,""); |
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140 | vhdl->set_body (3,"var_PC_NEXT_VAL := reg_PC_NEXT_VAL ;"); |
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141 | vhdl->set_body (3,"var_PC_NEXT := reg_PC_NEXT ;"); |
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142 | vhdl->set_body (3,"var_PC_NEXT_IS_DS_TAKE := reg_PC_NEXT_IS_DS_TAKE ;"); |
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143 | vhdl->set_body (3,"var_PC_NEXT_INSTRUCTION_ENABLE := reg_PC_NEXT_INSTRUCTION_ENABLE ;"); |
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144 | if (_param->_have_port_inst_ifetch_ptr) |
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145 | vhdl->set_body (3,"var_PC_NEXT_INST_IFETCH_PTR := reg_PC_NEXT_INST_IFETCH_PTR ;"); |
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146 | vhdl->set_body (3,"var_PC_NEXT_BRANCH_STATE := reg_PC_NEXT_BRANCH_STATE ;"); |
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147 | if (_param->_have_port_depth) |
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148 | vhdl->set_body (3,"var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID := reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); |
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149 | vhdl->set_body (3,""); |
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150 | vhdl->set_body (3,"var_PC_NEXT_NEXT_VAL := reg_PC_NEXT_NEXT_VAL ;"); |
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151 | vhdl->set_body (3,"var_PC_NEXT_NEXT := reg_PC_NEXT_NEXT ;"); |
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152 | vhdl->set_body (3,"var_PC_NEXT_NEXT_IS_DS_TAKE := reg_PC_NEXT_NEXT_IS_DS_TAKE ;"); |
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153 | // vhdl->set_body (3,"var_PC_NEXT_NEXT_INSTRUCTION_ENABLE := reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE ;"); |
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154 | // if (_param->_have_port_inst_ifetch_ptr) |
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155 | // vhdl->set_body (3,"var_PC_NEXT_NEXT_INST_IFETCH_PTR := reg_PC_NEXT_NEXT_INST_IFETCH_PTR ;"); |
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156 | // vhdl->set_body (3,"var_PC_NEXT_NEXT_BRANCH_STATE := reg_PC_NEXT_NEXT_BRANCH_STATE ;"); |
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157 | // if (_param->_have_port_depth) |
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158 | // vhdl->set_body (3,"var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID := reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); |
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159 | |
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160 | { |
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161 | vhdl->set_comment(3,"========================================="); |
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162 | vhdl->set_comment(3,"===== PREDICT ==========================="); |
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163 | vhdl->set_comment(3,"========================================="); |
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164 | |
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165 | vhdl->set_body (3,"if ((internal_PREDICT_VAL and in_PREDICT_ACK) = '1') then"); |
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166 | vhdl->set_body (4,"if (var_PC_NEXT_IS_DS_TAKE = '1') then"); |
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167 | if (_param->_have_port_inst_ifetch_ptr) |
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168 | vhdl->set_body (5,"var_PC_CURRENT_INST_IFETCH_PTR := in_PREDICT_INST_IFETCH_PTR;"); |
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169 | vhdl->set_body (5,"var_PC_CURRENT_BRANCH_STATE := in_PREDICT_BRANCH_STATE;"); |
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170 | if (_param->_have_port_depth) |
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171 | vhdl->set_body (5,"var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID := in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;"); |
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172 | vhdl->set_body (5,"else"); |
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173 | if (_param->_have_port_inst_ifetch_ptr) |
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174 | vhdl->set_body (5,"var_PC_NEXT_INST_IFETCH_PTR := in_PREDICT_INST_IFETCH_PTR;"); |
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175 | vhdl->set_body (5,"var_PC_NEXT_BRANCH_STATE := in_PREDICT_BRANCH_STATE;"); |
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176 | if (_param->_have_port_depth) |
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177 | vhdl->set_body (5,"var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID := in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;"); |
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178 | vhdl->set_body (4,"end if;"); |
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179 | |
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180 | vhdl->set_body (4,"var_PC_NEXT_NEXT_VAL := '1'; -- address is valid"); |
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181 | vhdl->set_body (4,"var_PC_NEXT_NEXT := in_PREDICT_PC_NEXT;"); |
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182 | vhdl->set_body (4,"var_PC_NEXT_NEXT_IS_DS_TAKE := in_PREDICT_PC_NEXT_IS_DS_TAKE;"); |
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183 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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184 | vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE;"); |
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185 | |
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186 | vhdl->set_body (3,"end if;"); |
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187 | } |
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188 | |
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189 | { |
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190 | vhdl->set_comment(3,"========================================="); |
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191 | vhdl->set_comment(3,"===== ADDRESS ==========================="); |
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192 | vhdl->set_comment(3,"========================================="); |
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193 | |
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194 | vhdl->set_body (3,"if ((internal_ADDRESS_VAL and in_ADDRESS_ACK) = '1') then"); |
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195 | |
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196 | vhdl->set_body (4,"var_PC_ACCESS_VAL := '0'; -- transaction with icache"); |
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197 | |
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198 | vhdl->set_body (3,"end if;"); |
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199 | } |
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200 | |
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201 | { |
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202 | vhdl->set_comment(3,"========================================="); |
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203 | vhdl->set_comment(3,"===== Shift Register ===================="); |
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204 | vhdl->set_comment(3,"========================================="); |
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205 | |
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206 | vhdl->set_body (3,"if ((var_PC_NEXT_NEXT_VAL and var_PC_NEXT_VAL and var_PC_CURRENT_VAL and not var_PC_ACCESS_VAL) = '1') then"); |
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207 | vhdl->set_body (4,"var_PC_ACCESS_VAL := '1'; -- new request"); |
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208 | vhdl->set_body (4,"var_PC_CURRENT_VAL := '0'; -- invalid current"); |
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209 | vhdl->set_body (4,"var_PC_ACCESS := var_PC_CURRENT;"); |
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210 | vhdl->set_body (4,"var_PC_ACCESS_IS_DS_TAKE := var_PC_CURRENT_IS_DS_TAKE;"); |
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211 | if (_param->_have_port_inst_ifetch_ptr) |
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212 | vhdl->set_body (4,"var_PC_ACCESS_INST_IFETCH_PTR := var_PC_CURRENT_INST_IFETCH_PTR;"); |
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213 | vhdl->set_body (4,"var_PC_ACCESS_BRANCH_STATE := var_PC_CURRENT_BRANCH_STATE;"); |
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214 | if (_param->_have_port_depth) |
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215 | vhdl->set_body (4,"var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID := var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID;"); |
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216 | // for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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217 | // vhdl->set_body (4,"var_PC_ACCESS_INSTRUCTION_ENABLE("+toString(i)+") := var_PC_CURRENT_INSTRUCTION_ENABLE("+toString(i)+");"); |
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218 | vhdl->set_body (4,"var_PC_ACCESS_INSTRUCTION_ENABLE := var_PC_CURRENT_INSTRUCTION_ENABLE;"); |
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219 | vhdl->set_body (3,"end if;"); |
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220 | |
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221 | vhdl->set_body (3,"if ((var_PC_NEXT_NEXT_VAL and var_PC_NEXT_VAL and not var_PC_CURRENT_VAL) = '1') then"); |
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222 | vhdl->set_body (4,"var_PC_CURRENT_VAL := '1'; -- new request"); |
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223 | vhdl->set_body (4,"var_PC_NEXT_VAL := '0'; -- invalid next"); |
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224 | vhdl->set_body (4,"var_PC_CURRENT := var_PC_NEXT;"); |
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225 | vhdl->set_body (4,"var_PC_CURRENT_IS_DS_TAKE := var_PC_NEXT_IS_DS_TAKE;"); |
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226 | if (_param->_have_port_inst_ifetch_ptr) |
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227 | vhdl->set_body (4,"var_PC_CURRENT_INST_IFETCH_PTR := var_PC_NEXT_INST_IFETCH_PTR;"); |
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228 | vhdl->set_body (4,"var_PC_CURRENT_BRANCH_STATE := var_PC_NEXT_BRANCH_STATE;"); |
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229 | if (_param->_have_port_depth) |
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230 | vhdl->set_body (4,"var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID := var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;"); |
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231 | // for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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232 | // vhdl->set_body (4,"var_PC_CURRENT_INSTRUCTION_ENABLE("+toString(i)+") := var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+");"); |
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233 | vhdl->set_body (4,"var_PC_CURRENT_INSTRUCTION_ENABLE := var_PC_NEXT_INSTRUCTION_ENABLE;"); |
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234 | vhdl->set_body (3,"end if;"); |
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235 | |
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236 | vhdl->set_body (3,"if ((var_PC_NEXT_NEXT_VAL and not var_PC_NEXT_VAL) = '1') then"); |
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237 | vhdl->set_body (4,"var_PC_NEXT_VAL := '1'; -- new request"); |
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238 | vhdl->set_body (4,"var_PC_NEXT_NEXT_VAL := '0'; -- invalid next_next"); |
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239 | vhdl->set_body (4,"var_PC_NEXT := var_PC_NEXT_NEXT;"); |
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240 | vhdl->set_body (4,"var_PC_NEXT_IS_DS_TAKE := var_PC_NEXT_NEXT_IS_DS_TAKE;"); |
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241 | // if (_param->_have_port_inst_ifetch_ptr) |
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242 | // vhdl->set_body (4,"var_PC_NEXT_INST_IFETCH_PTR := var_PC_NEXT_NEXT_INST_IFETCH_PTR;"); |
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243 | // vhdl->set_body (4,"var_PC_NEXT_BRANCH_STATE := var_PC_NEXT_NEXT_BRANCH_STATE;"); |
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244 | // if (_param->_have_port_depth) |
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245 | // vhdl->set_body (4,"var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID := var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;"); |
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246 | // for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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247 | // vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := var_PC_NEXT_NEXT_INSTRUCTION_ENABLE("+toString(i)+");"); |
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248 | // vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE := var_PC_NEXT_NEXT_INSTRUCTION_ENABLE;"); |
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249 | vhdl->set_body (3,"end if;"); |
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250 | } |
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251 | |
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252 | { |
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253 | vhdl->set_comment(3,"========================================="); |
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254 | vhdl->set_comment(3,"===== EVENT ============================="); |
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255 | vhdl->set_comment(3,"========================================="); |
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256 | |
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257 | vhdl->set_body (3,"if ((in_EVENT_VAL and internal_EVENT_ACK) = '1') then"); |
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258 | vhdl->set_body (4,"var_PC_ACCESS_VAL := '0';"); |
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259 | vhdl->set_body (4,"var_PC_CURRENT_VAL := '0';"); |
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260 | vhdl->set_body (4,"var_PC_NEXT_VAL := '1';"); |
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261 | vhdl->set_body (4,"var_PC_NEXT := in_EVENT_ADDRESS;"); |
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262 | vhdl->set_body (4,"var_PC_NEXT_IS_DS_TAKE := in_EVENT_IS_DS_TAKE;"); |
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263 | |
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264 | if (is_power2(_param->_nb_instruction)) |
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265 | { |
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266 | uint32_t size = log2(_param->_nb_instruction); |
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267 | |
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268 | if (size != 0) |
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269 | { |
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270 | std::string range = "var_PC_NEXT"+std_logic_range(size-1,0); |
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271 | |
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272 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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273 | { |
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274 | vhdl->set_body (4,"if ("+range+" = "+std_logic_cst(size,i)+") then"); |
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275 | vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := '1';"); |
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276 | vhdl->set_body (4,"else"); |
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277 | vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := '0';"); |
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278 | vhdl->set_body (4,"end if;"); |
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279 | } |
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280 | } |
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281 | else |
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282 | vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE(0) := '1';"); |
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283 | } |
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284 | else |
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285 | { |
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286 | throw ERRORMORPHEO(FUNCTION,_("Not Yet supported, Comming Soon.")); |
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287 | } |
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288 | |
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289 | vhdl->set_body (4,"var_PC_NEXT_NEXT_VAL := in_EVENT_ADDRESS_NEXT_VAL;"); |
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290 | vhdl->set_body (4,"var_PC_NEXT_NEXT := in_EVENT_ADDRESS_NEXT;"); |
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291 | vhdl->set_body (4,"var_PC_NEXT_NEXT_IS_DS_TAKE := '0';"); |
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292 | |
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293 | vhdl->set_body (3,"end if;"); |
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294 | } |
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295 | |
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296 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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297 | vhdl->set_comment(3,"WRITE Register"); |
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298 | vhdl->set_comment(3,"---------------------------------------------------------------------------"); |
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299 | |
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300 | vhdl->set_body (3,"reg_PC_ACCESS_VAL <= var_PC_ACCESS_VAL ;"); |
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301 | vhdl->set_body (3,"reg_PC_ACCESS <= var_PC_ACCESS ;"); |
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302 | vhdl->set_body (3,"reg_PC_ACCESS_IS_DS_TAKE <= var_PC_ACCESS_IS_DS_TAKE ;"); |
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303 | vhdl->set_body (3,"reg_PC_ACCESS_INSTRUCTION_ENABLE <= var_PC_ACCESS_INSTRUCTION_ENABLE ;"); |
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304 | if (_param->_have_port_inst_ifetch_ptr) |
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305 | vhdl->set_body (3,"reg_PC_ACCESS_INST_IFETCH_PTR <= var_PC_ACCESS_INST_IFETCH_PTR ;"); |
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306 | vhdl->set_body (3,"reg_PC_ACCESS_BRANCH_STATE <= var_PC_ACCESS_BRANCH_STATE ;"); |
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307 | if (_param->_have_port_depth) |
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308 | vhdl->set_body (3,"reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID <= var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID ;"); |
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309 | vhdl->set_body (3,""); |
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310 | vhdl->set_body (3,"reg_PC_CURRENT_VAL <= var_PC_CURRENT_VAL ;"); |
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311 | vhdl->set_body (3,"reg_PC_CURRENT <= var_PC_CURRENT ;"); |
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312 | vhdl->set_body (3,"reg_PC_CURRENT_IS_DS_TAKE <= var_PC_CURRENT_IS_DS_TAKE ;"); |
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313 | vhdl->set_body (3,"reg_PC_CURRENT_INSTRUCTION_ENABLE <= var_PC_CURRENT_INSTRUCTION_ENABLE ;"); |
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314 | if (_param->_have_port_inst_ifetch_ptr) |
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315 | vhdl->set_body (3,"reg_PC_CURRENT_INST_IFETCH_PTR <= var_PC_CURRENT_INST_IFETCH_PTR ;"); |
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316 | vhdl->set_body (3,"reg_PC_CURRENT_BRANCH_STATE <= var_PC_CURRENT_BRANCH_STATE ;"); |
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317 | if (_param->_have_port_depth) |
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318 | vhdl->set_body (3,"reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID <= var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID ;"); |
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319 | vhdl->set_body (3,""); |
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320 | vhdl->set_body (3,"reg_PC_NEXT_VAL <= var_PC_NEXT_VAL ;"); |
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321 | vhdl->set_body (3,"reg_PC_NEXT <= var_PC_NEXT ;"); |
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322 | vhdl->set_body (3,"reg_PC_NEXT_IS_DS_TAKE <= var_PC_NEXT_IS_DS_TAKE ;"); |
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323 | vhdl->set_body (3,"reg_PC_NEXT_INSTRUCTION_ENABLE <= var_PC_NEXT_INSTRUCTION_ENABLE ;"); |
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324 | if (_param->_have_port_inst_ifetch_ptr) |
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325 | vhdl->set_body (3,"reg_PC_NEXT_INST_IFETCH_PTR <= var_PC_NEXT_INST_IFETCH_PTR ;"); |
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326 | vhdl->set_body (3,"reg_PC_NEXT_BRANCH_STATE <= var_PC_NEXT_BRANCH_STATE ;"); |
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327 | if (_param->_have_port_depth) |
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328 | vhdl->set_body (3,"reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID <= var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); |
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329 | vhdl->set_body (3,""); |
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330 | vhdl->set_body (3,"reg_PC_NEXT_NEXT_VAL <= var_PC_NEXT_NEXT_VAL ;"); |
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331 | vhdl->set_body (3,"reg_PC_NEXT_NEXT <= var_PC_NEXT_NEXT ;"); |
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332 | vhdl->set_body (3,"reg_PC_NEXT_NEXT_IS_DS_TAKE <= var_PC_NEXT_NEXT_IS_DS_TAKE ;"); |
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333 | // vhdl->set_body (3,"reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE <= var_PC_NEXT_NEXT_INSTRUCTION_ENABLE ;"); |
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334 | // if (_param->_have_port_inst_ifetch_ptr) |
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335 | // vhdl->set_body (3,"reg_PC_NEXT_NEXT_INST_IFETCH_PTR <= var_PC_NEXT_NEXT_INST_IFETCH_PTR ;"); |
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336 | // vhdl->set_body (3,"reg_PC_NEXT_NEXT_BRANCH_STATE <= var_PC_NEXT_NEXT_BRANCH_STATE ;"); |
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337 | // if (_param->_have_port_depth) |
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338 | // vhdl->set_body (3,"reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID <= var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); |
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339 | |
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340 | |
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341 | vhdl->set_body (2,"end if; -- reset"); |
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342 | vhdl->set_body (1,"end if; -- clock"); |
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343 | vhdl->set_body (0,"end process; -- TRANSITION"); |
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344 | |
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345 | vhdl->set_comment(0,"========================================="); |
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346 | vhdl->set_comment(0,"===== ADDRESS ==========================="); |
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347 | vhdl->set_comment(0,"========================================="); |
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348 | |
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349 | vhdl->set_body (0,"internal_ADDRESS_VAL <= reg_PC_ACCESS_VAL;"); |
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350 | vhdl->set_body (0," out_ADDRESS_VAL <= internal_ADDRESS_VAL;"); |
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351 | |
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352 | if (is_power2(_param->_nb_instruction)) |
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353 | { |
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354 | uint32_t size = log2(_param->_nb_instruction); |
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355 | |
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356 | vhdl->set_body (0,"out_ADDRESS_INSTRUCTION_ADDRESS <= reg_PC_ACCESS and not "+std_logic_cst(_param->_size_instruction_address,(1<<size)-1)+";"); |
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357 | } |
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358 | else |
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359 | { |
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360 | throw ERRORMORPHEO(FUNCTION,_("Not Yet supported, Comming Soon.")); |
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361 | } |
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362 | |
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363 | |
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364 | if (_param->_have_port_inst_ifetch_ptr) |
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365 | vhdl->set_body (0,"out_ADDRESS_INST_IFETCH_PTR <= reg_PC_ACCESS_INST_IFETCH_PTR;"); |
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366 | vhdl->set_body (0,"out_ADDRESS_BRANCH_STATE <= reg_PC_ACCESS_BRANCH_STATE;"); |
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367 | if (_param->_have_port_depth) |
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368 | vhdl->set_body (0,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID<= reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID;"); |
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369 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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370 | vhdl->set_body (0,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE <= reg_PC_ACCESS_INSTRUCTION_ENABLE ("+toString(i)+");"); |
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371 | |
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372 | vhdl->set_comment(0,"========================================="); |
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373 | vhdl->set_comment(0,"===== PREDICT ==========================="); |
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374 | vhdl->set_comment(0,"========================================="); |
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375 | |
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376 | vhdl->set_body (0,"internal_PREDICT_VAL <= not reg_PC_NEXT_NEXT_VAL;"); |
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377 | vhdl->set_body (0," out_PREDICT_VAL <= internal_PREDICT_VAL; "); |
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378 | vhdl->set_body (0,"out_PREDICT_PC_PREVIOUS <= reg_PC_CURRENT; "); |
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379 | vhdl->set_body (0,"out_PREDICT_PC_CURRENT <= reg_PC_NEXT; "); |
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380 | vhdl->set_body (0,"out_PREDICT_PC_CURRENT_IS_DS_TAKE <= reg_PC_NEXT_IS_DS_TAKE;"); |
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381 | |
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382 | log_printf(FUNC,Address_management,FUNCTION,"End"); |
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383 | }; |
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384 | |
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385 | }; // end namespace address_management |
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386 | }; // end namespace ifetch_unit |
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387 | }; // end namespace front_end |
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388 | }; // end namespace multi_front_end |
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389 | }; // end namespace core |
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390 | |
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391 | }; // end namespace behavioural |
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392 | }; // end namespace morpheo |
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393 | #endif |
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