1 | #ifdef VHDL |
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2 | /* |
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3 | * $Id: Address_management_vhdl_declaration.cpp 135 2009-07-17 08:59:05Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_front_end { |
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15 | namespace front_end { |
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16 | namespace ifetch_unit { |
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17 | namespace address_management { |
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18 | |
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19 | |
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20 | #undef FUNCTION |
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21 | #define FUNCTION "Address_management::vhdl_declaration" |
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22 | void Address_management::vhdl_declaration (Vhdl * & vhdl) |
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23 | { |
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24 | log_printf(FUNC,Address_management,FUNCTION,"Begin"); |
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25 | |
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26 | vhdl->set_type ("Tinstruction_enable ","array "+_std_logic_range(_param->_nb_instruction)+" of std_logic"); |
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27 | |
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28 | vhdl->set_signal ("reg_PC_ACCESS_VAL ", 1); |
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29 | vhdl->set_signal ("reg_PC_ACCESS ", _param->_size_instruction_address); |
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30 | vhdl->set_signal ("reg_PC_ACCESS_IS_DS_TAKE ", 1); |
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31 | vhdl->set_signal ("reg_PC_ACCESS_INSTRUCTION_ENABLE ", "Tinstruction_enable"); |
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32 | if (_param->_have_port_inst_ifetch_ptr) |
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33 | vhdl->set_signal ("reg_PC_ACCESS_INST_IFETCH_PTR ", _param->_size_inst_ifetch_ptr); |
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34 | vhdl->set_signal ("reg_PC_ACCESS_BRANCH_STATE ", _param->_size_branch_state); |
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35 | if (_param->_have_port_depth) |
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36 | vhdl->set_signal ("reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID ", _param->_size_depth); |
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37 | |
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38 | |
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39 | vhdl->set_signal ("reg_PC_CURRENT_VAL ", 1); |
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40 | vhdl->set_signal ("reg_PC_CURRENT ", _param->_size_instruction_address); |
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41 | vhdl->set_signal ("reg_PC_CURRENT_IS_DS_TAKE ", 1); |
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42 | vhdl->set_signal ("reg_PC_CURRENT_INSTRUCTION_ENABLE ", "Tinstruction_enable"); |
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43 | if (_param->_have_port_inst_ifetch_ptr) |
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44 | vhdl->set_signal ("reg_PC_CURRENT_INST_IFETCH_PTR ",_param->_size_inst_ifetch_ptr); |
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45 | vhdl->set_signal ("reg_PC_CURRENT_BRANCH_STATE ", _param->_size_branch_state); |
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46 | if (_param->_have_port_depth) |
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47 | vhdl->set_signal ("reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID ", _param->_size_depth); |
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48 | |
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49 | vhdl->set_signal ("reg_PC_NEXT_VAL ", 1); |
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50 | vhdl->set_signal ("reg_PC_NEXT ", _param->_size_instruction_address); |
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51 | vhdl->set_signal ("reg_PC_NEXT_IS_DS_TAKE ", 1); |
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52 | vhdl->set_signal ("reg_PC_NEXT_INSTRUCTION_ENABLE ", "Tinstruction_enable"); |
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53 | if (_param->_have_port_inst_ifetch_ptr) |
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54 | vhdl->set_signal ("reg_PC_NEXT_INST_IFETCH_PTR ",_param->_size_inst_ifetch_ptr); |
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55 | vhdl->set_signal ("reg_PC_NEXT_BRANCH_STATE ", _param->_size_branch_state); |
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56 | if (_param->_have_port_depth) |
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57 | vhdl->set_signal ("reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID ", _param->_size_depth); |
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58 | |
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59 | vhdl->set_signal ("reg_PC_NEXT_NEXT_VAL ", 1); |
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60 | vhdl->set_signal ("reg_PC_NEXT_NEXT ", _param->_size_instruction_address); |
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61 | vhdl->set_signal ("reg_PC_NEXT_NEXT_IS_DS_TAKE ", 1); |
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62 | // vhdl->set_signal ("reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE ", "Tinstruction_enable"); |
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63 | // if (_param->_have_port_inst_ifetch_ptr) |
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64 | // vhdl->set_signal ("reg_PC_NEXT_NEXT_INST_IFETCH_PTR ",_param->_size_inst_ifetch_ptr); |
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65 | // vhdl->set_signal ("reg_PC_NEXT_NEXT_BRANCH_STATE ", _param->_size_branch_state); |
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66 | // if (_param->_have_port_depth) |
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67 | // vhdl->set_signal ("reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID", _param->_size_depth); |
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68 | |
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69 | vhdl->set_signal ("internal_PREDICT_VAL ", 1); |
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70 | vhdl->set_signal ("internal_ADDRESS_VAL ", 1); |
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71 | vhdl->set_signal ("internal_EVENT_ACK ", 1); |
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72 | |
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73 | log_printf(FUNC,Address_management,FUNCTION,"End"); |
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74 | }; |
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75 | |
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76 | }; // end namespace address_management |
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77 | }; // end namespace ifetch_unit |
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78 | }; // end namespace front_end |
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79 | }; // end namespace multi_front_end |
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80 | }; // end namespace core |
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81 | |
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82 | }; // end namespace behavioural |
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83 | }; // end namespace morpheo |
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84 | #endif |
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