[78] | 1 | /* |
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| 2 | * $Id: test.cpp 113 2009-04-14 18:39:12Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[82] | 9 | #define NB_ITERATION 1 |
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| 10 | #define CYCLE_MAX (2048*NB_ITERATION) |
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| 11 | |
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[78] | 12 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/include/test.h" |
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| 13 | #include "Common/include/Test.h" |
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| 14 | #include "Behavioural/include/Allocation.h" |
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| 15 | #include <list> |
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| 16 | #include <set> |
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| 17 | |
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| 18 | class entry_t |
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| 19 | { |
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| 20 | public : uint32_t _cycle; |
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| 21 | public : Tpacket_t _packet; |
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| 22 | public : Tgeneral_address_t _addr; |
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| 23 | |
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| 24 | public : entry_t (uint32_t cycle, |
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| 25 | Tpacket_t packet, |
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| 26 | Tgeneral_address_t addr ) |
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| 27 | { |
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| 28 | _cycle = cycle ; |
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| 29 | _packet = packet; |
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| 30 | _addr = addr ; |
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| 31 | } |
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| 32 | }; |
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| 33 | |
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| 34 | void test (string name, |
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| 35 | morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Parameters * _param) |
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| 36 | { |
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| 37 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 38 | |
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| 39 | #ifdef STATISTICS |
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| 40 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,1000); |
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| 41 | #endif |
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| 42 | |
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[88] | 43 | Tusage_t _usage = USE_ALL; |
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| 44 | |
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| 45 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 46 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 47 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 48 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 49 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 50 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 51 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 52 | |
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[82] | 53 | Ifetch_queue * _Ifetch_queue = new Ifetch_queue |
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| 54 | (name.c_str(), |
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[78] | 55 | #ifdef STATISTICS |
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[82] | 56 | _parameters_statistics, |
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[78] | 57 | #endif |
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[82] | 58 | _param, |
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[88] | 59 | _usage); |
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[78] | 60 | |
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| 61 | #ifdef SYSTEMC |
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| 62 | /********************************************************************* |
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| 63 | * Déclarations des signaux |
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| 64 | *********************************************************************/ |
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| 65 | string rename; |
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| 66 | |
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| 67 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 68 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 69 | |
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[113] | 70 | sc_signal<Tcontrol_t > * in_ADDRESS_VAL ; |
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| 71 | sc_signal<Tcontrol_t > * out_ADDRESS_ACK ; |
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| 72 | sc_signal<Tifetch_queue_ptr_t > * out_ADDRESS_IFETCH_QUEUE_ID ; |
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| 73 | sc_signal<Tcontrol_t > ** in_ADDRESS_INSTRUCTION_ENABLE ;//[nb_instruction] |
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| 74 | sc_signal<Tgeneral_address_t > * in_ADDRESS_INSTRUCTION_ADDRESS ; |
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| 75 | sc_signal<Tinst_ifetch_ptr_t > * in_ADDRESS_INST_IFETCH_PTR ; |
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| 76 | sc_signal<Tbranch_state_t > * in_ADDRESS_BRANCH_STATE ; |
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| 77 | sc_signal<Tprediction_ptr_t > * in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ; |
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| 78 | sc_signal<Tcontrol_t > ** out_DECOD_VAL ;//[nb_instruction] |
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| 79 | sc_signal<Tcontrol_t > ** in_DECOD_ACK ;//[nb_instruction] |
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| 80 | sc_signal<Tinstruction_t > ** out_DECOD_INSTRUCTION ;//[nb_instruction] |
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| 81 | sc_signal<Tgeneral_address_t > * out_DECOD_ADDRESS ; |
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| 82 | sc_signal<Tinst_ifetch_ptr_t > * out_DECOD_INST_IFETCH_PTR ; |
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| 83 | sc_signal<Tbranch_state_t > * out_DECOD_BRANCH_STATE ; |
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| 84 | sc_signal<Tprediction_ptr_t > * out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; |
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| 85 | sc_signal<Texception_t > * out_DECOD_EXCEPTION ; |
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| 86 | sc_signal<Tcontrol_t > * in_ICACHE_RSP_VAL ; |
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| 87 | sc_signal<Tcontrol_t > * out_ICACHE_RSP_ACK ; |
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| 88 | sc_signal<Tpacket_t > * in_ICACHE_RSP_PACKET_ID ; |
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| 89 | sc_signal<Ticache_instruction_t > ** in_ICACHE_RSP_INSTRUCTION ;//[nb_instruction] |
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| 90 | sc_signal<Ticache_error_t > * in_ICACHE_RSP_ERROR ; |
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| 91 | sc_signal<Tcontrol_t > * in_EVENT_RESET_VAL ;// val if : miss_speculation, exception, synchronization |
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| 92 | sc_signal<Tcontrol_t > * out_EVENT_RESET_ACK ; |
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| 93 | |
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[112] | 94 | ALLOC0_SC_SIGNAL( in_ADDRESS_VAL ," in_ADDRESS_VAL ",Tcontrol_t ); |
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| 95 | ALLOC0_SC_SIGNAL(out_ADDRESS_ACK ,"out_ADDRESS_ACK ",Tcontrol_t ); |
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| 96 | ALLOC0_SC_SIGNAL(out_ADDRESS_IFETCH_QUEUE_ID ,"out_ADDRESS_IFETCH_QUEUE_ID ",Tifetch_queue_ptr_t ); |
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[78] | 97 | ALLOC1_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE ," in_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
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[112] | 98 | ALLOC0_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ADDRESS ," in_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t ); |
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| 99 | ALLOC0_SC_SIGNAL( in_ADDRESS_INST_IFETCH_PTR ," in_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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| 100 | ALLOC0_SC_SIGNAL( in_ADDRESS_BRANCH_STATE ," in_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); |
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| 101 | ALLOC0_SC_SIGNAL( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID," in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
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[78] | 102 | ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_instruction); |
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| 103 | ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_instruction); |
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| 104 | ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION ,"out_DECOD_INSTRUCTION ",Tinstruction_t ,_param->_nb_instruction); |
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[112] | 105 | ALLOC0_SC_SIGNAL(out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t ); |
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| 106 | ALLOC0_SC_SIGNAL(out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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| 107 | ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t ); |
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| 108 | ALLOC0_SC_SIGNAL(out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ); |
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| 109 | ALLOC0_SC_SIGNAL(out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Tprediction_ptr_t ); |
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| 110 | ALLOC0_SC_SIGNAL( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ); |
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| 111 | ALLOC0_SC_SIGNAL(out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ); |
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| 112 | ALLOC0_SC_SIGNAL( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ); |
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[78] | 113 | ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_instruction); |
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[112] | 114 | ALLOC0_SC_SIGNAL( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ); |
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| 115 | ALLOC0_SC_SIGNAL( in_EVENT_RESET_VAL ," in_EVENT_RESET_VAL ",Tcontrol_t ); |
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| 116 | ALLOC0_SC_SIGNAL(out_EVENT_RESET_ACK ,"out_EVENT_RESET_ACK ",Tcontrol_t ); |
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[78] | 117 | |
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| 118 | /******************************************************** |
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| 119 | * Instanciation |
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| 120 | ********************************************************/ |
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| 121 | |
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| 122 | msg(_("<%s> : Instanciation of _Ifetch_queue.\n"),name.c_str()); |
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| 123 | |
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| 124 | (*(_Ifetch_queue->in_CLOCK)) (*(in_CLOCK)); |
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| 125 | (*(_Ifetch_queue->in_NRESET)) (*(in_NRESET)); |
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| 126 | |
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[112] | 127 | INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_VAL ); |
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| 128 | INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ADDRESS_ACK ); |
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[88] | 129 | if (_param->_have_port_ifetch_queue_ptr) |
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[112] | 130 | INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID ); |
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[78] | 131 | INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
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[112] | 132 | INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS ); |
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[88] | 133 | if (_param->_have_port_inst_ifetch_ptr) |
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[112] | 134 | INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR ); |
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| 135 | INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_BRANCH_STATE ); |
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[88] | 136 | if (_param->_have_port_depth) |
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[112] | 137 | INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); |
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[78] | 138 | INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL ,_param->_nb_instruction); |
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| 139 | INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_DECOD_ACK ,_param->_nb_instruction); |
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| 140 | INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION ,_param->_nb_instruction); |
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[112] | 141 | INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_ADDRESS ); |
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[88] | 142 | if (_param->_have_port_inst_ifetch_ptr) |
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[112] | 143 | INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_INST_IFETCH_PTR ); |
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| 144 | INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_BRANCH_STATE ); |
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[88] | 145 | if (_param->_have_port_depth) |
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[112] | 146 | INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); |
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| 147 | INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_DECOD_EXCEPTION ); |
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| 148 | INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_VAL ); |
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| 149 | INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_ICACHE_RSP_ACK ); |
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[88] | 150 | if (_param->_have_port_ifetch_queue_ptr) |
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[112] | 151 | INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_PACKET_ID ); |
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[78] | 152 | INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction); |
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[112] | 153 | INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_ERROR ); |
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| 154 | INSTANCE0_SC_SIGNAL(_Ifetch_queue, in_EVENT_RESET_VAL ); |
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| 155 | INSTANCE0_SC_SIGNAL(_Ifetch_queue,out_EVENT_RESET_ACK ); |
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[78] | 156 | |
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| 157 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 158 | |
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| 159 | Time * _time = new Time(); |
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| 160 | |
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| 161 | /******************************************************** |
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| 162 | * Simulation - Begin |
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| 163 | ********************************************************/ |
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| 164 | |
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| 165 | // Initialisation |
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| 166 | |
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| 167 | const uint32_t seed = 0; |
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| 168 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 169 | |
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| 170 | srand(seed); |
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| 171 | |
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| 172 | const int32_t percent_transaction_address = 75; |
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| 173 | const int32_t percent_transaction_decod = 75; |
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| 174 | const int32_t percent_transaction_event_reset = 10; |
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| 175 | const int32_t percent_icache_hit = 100; |
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| 176 | const int32_t icache_miss_penality = 10; |
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| 177 | |
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| 178 | SC_START(0); |
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| 179 | LABEL("Initialisation"); |
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| 180 | |
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| 181 | LABEL("Reset"); |
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| 182 | in_NRESET->write(0); |
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| 183 | SC_START(5); |
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| 184 | in_NRESET->write(1); |
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| 185 | |
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| 186 | LABEL("Loop of Test"); |
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| 187 | |
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| 188 | list<Tgeneral_data_t> list_wait_decod; |
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| 189 | list<entry_t> list_req_icache; |
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| 190 | |
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| 191 | Tgeneral_data_t modulo_iberr = 23; |
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| 192 | Tinstruction_t xor_inst = 0xdeadbeef; |
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| 193 | Tgeneral_data_t address; |
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| 194 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 195 | { |
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| 196 | LABEL("Iteration %d",iteration); |
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| 197 | |
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| 198 | int32_t nb_request_in = 64; |
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| 199 | int32_t nb_request_out = 64; |
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| 200 | |
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| 201 | address = 0x100; |
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| 202 | |
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| 203 | list_wait_decod.clear(); |
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| 204 | |
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| 205 | while ((nb_request_in > 0) and |
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| 206 | (nb_request_out > 0)) |
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| 207 | { |
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| 208 | // ===== |
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| 209 | // ===== ADDRESS |
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| 210 | // ===== |
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| 211 | in_ADDRESS_VAL ->write((nb_request_in > 0) and ((rand()%100)<percent_transaction_address)); |
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| 212 | in_ADDRESS_INSTRUCTION_ADDRESS ->write(address); |
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| 213 | uint32_t nb_inst_enable = (rand() % _param->_nb_instruction); |
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| 214 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 215 | in_ADDRESS_INSTRUCTION_ENABLE [i] ->write(i<=nb_inst_enable); |
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[88] | 216 | if (_param->_have_port_inst_ifetch_ptr) |
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[78] | 217 | in_ADDRESS_INST_IFETCH_PTR ->write(address%_param->_nb_instruction); |
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| 218 | in_ADDRESS_BRANCH_STATE ->write(address%SIZE_BRANCH_STATE); |
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[88] | 219 | if (_param->_have_port_depth) |
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| 220 | in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_depth); |
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[78] | 221 | |
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| 222 | // ===== |
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| 223 | // ===== DECOD |
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| 224 | // ===== |
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| 225 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 226 | in_DECOD_ACK [i]->write(0); |
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| 227 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 228 | { |
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| 229 | if ((rand()%100)>percent_transaction_decod) |
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| 230 | break; |
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| 231 | in_DECOD_ACK [i]->write(1); |
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| 232 | } |
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| 233 | |
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| 234 | // ===== |
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| 235 | // ===== ICACHE_RSP |
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| 236 | // ===== |
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| 237 | Tcontrol_t icache_rsp_val = not list_req_icache.empty() and (list_req_icache.front()._cycle == 0); |
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| 238 | |
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| 239 | // LABEL("Test ICACHE_RSP :"); |
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| 240 | // LABEL(" * list_req_icache.empty() : %d",list_req_icache.empty()); |
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| 241 | // if (not list_req_icache.empty()) |
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| 242 | // LABEL(" * list_req_icache.front()._cycle : %d",list_req_icache.front()._cycle); |
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| 243 | |
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| 244 | in_ICACHE_RSP_VAL->write(icache_rsp_val); |
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| 245 | |
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| 246 | if (icache_rsp_val) |
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| 247 | { |
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| 248 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 249 | in_ICACHE_RSP_INSTRUCTION [i]->write((list_req_icache.front()._addr + 4*i)^xor_inst); |
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| 250 | in_ICACHE_RSP_PACKET_ID ->write(list_req_icache.front()._packet); |
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| 251 | in_ICACHE_RSP_ERROR ->write(((list_req_icache.front()._addr % modulo_iberr)==0)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE); |
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| 252 | } |
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| 253 | |
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| 254 | // ===== |
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| 255 | // ===== EVENT_RESET |
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| 256 | // ===== |
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| 257 | in_EVENT_RESET_VAL->write((rand()%100)<percent_transaction_event_reset); |
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| 258 | |
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| 259 | // ---------------------------------------------- |
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| 260 | // ---------------------------------------------- |
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| 261 | // ---------------------------------------------- |
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| 262 | SC_START(0); |
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| 263 | // ---------------------------------------------- |
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| 264 | // ---------------------------------------------- |
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| 265 | // ---------------------------------------------- |
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| 266 | |
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| 267 | // ===== |
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| 268 | // ===== ADDRESS |
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| 269 | // ===== |
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| 270 | if ( in_ADDRESS_VAL->read() and |
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| 271 | out_ADDRESS_ACK->read()) |
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| 272 | { |
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| 273 | LABEL("ADDRESS : transaction accepted"); |
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| 274 | LABEL(" * address : %.8x",address); |
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| 275 | |
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| 276 | list_wait_decod.push_back(address); |
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[88] | 277 | // list_req_icache.insert(, entry_t((_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address)); |
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[78] | 278 | |
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| 279 | uint32_t cycle = ((rand()%100)<percent_icache_hit)?1:icache_miss_penality; |
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| 280 | LABEL(" * cycle : %d",cycle); |
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| 281 | |
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| 282 | list<entry_t>::iterator it; |
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| 283 | for (it=list_req_icache.begin(); it != list_req_icache.end(); it++) |
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| 284 | if (cycle < it->_cycle) |
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| 285 | break; |
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| 286 | |
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| 287 | LABEL(" * list_req_icache : %d",list_req_icache.size()); |
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[88] | 288 | list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address)); |
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[78] | 289 | LABEL(" * list_req_icache : %d",list_req_icache.size()); |
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| 290 | address += 4*_param->_nb_instruction; |
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| 291 | } |
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| 292 | |
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| 293 | // ===== |
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| 294 | // ===== DECOD |
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| 295 | // ===== |
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| 296 | bool have_decod_transaction = false; |
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| 297 | uint32_t nb_decod_keep = 0; |
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| 298 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 299 | { |
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| 300 | if (out_DECOD_VAL [i]->read()) |
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| 301 | { |
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| 302 | LABEL("DECOD_VAL [%d] ",i); |
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| 303 | nb_decod_keep ++; |
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| 304 | |
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| 305 | if (in_DECOD_ACK [i]->read()) |
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| 306 | { |
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| 307 | LABEL("DECOD_ACK [%d] ",i); |
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| 308 | |
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| 309 | have_decod_transaction = true; |
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| 310 | nb_decod_keep --; |
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| 311 | |
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| 312 | TEST(bool , list_wait_decod.empty() , false); |
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| 313 | TEST(Tinstruction_t , out_DECOD_INSTRUCTION[i]->read(), (list_wait_decod.front()+4*i)^xor_inst); |
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| 314 | } |
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| 315 | } |
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| 316 | } |
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| 317 | |
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| 318 | if (have_decod_transaction) |
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| 319 | { |
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| 320 | |
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| 321 | Tgeneral_data_t addr = list_wait_decod.front(); |
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| 322 | |
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| 323 | LABEL("DECOD : transaction accepted"); |
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| 324 | LABEL(" * address : %.8x",addr); |
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| 325 | |
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| 326 | TEST(Tgeneral_data_t ,out_DECOD_ADDRESS ->read(), addr); |
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| 327 | TEST(Tbranch_state_t ,out_DECOD_BRANCH_STATE ->read(),addr%SIZE_BRANCH_STATE); |
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[88] | 328 | if (_param->_have_port_inst_ifetch_ptr) |
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[78] | 329 | TEST(Tinst_ifetch_ptr_t,out_DECOD_INST_IFETCH_PTR ->read(),addr%_param->_nb_instruction); |
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[88] | 330 | if (_param->_have_port_depth) |
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| 331 | TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_depth); |
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[78] | 332 | if ((addr % modulo_iberr) == 0) |
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| 333 | TEST(Texception_t ,out_DECOD_EXCEPTION ->read(),EXCEPTION_IFETCH_BUS_ERROR); |
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| 334 | else |
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| 335 | TEST(Texception_t ,out_DECOD_EXCEPTION ->read(),EXCEPTION_IFETCH_NONE ); |
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| 336 | |
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| 337 | // all is decod |
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| 338 | LABEL(" * nb_decod_keep : %d",nb_decod_keep); |
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| 339 | if (nb_decod_keep == 0) |
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| 340 | { |
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| 341 | LABEL(" * decod all bundle"); |
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| 342 | list_wait_decod.pop_front(); |
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| 343 | nb_request_out --; |
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| 344 | } |
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| 345 | } |
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| 346 | |
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| 347 | // ===== |
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| 348 | // ===== ICACHE_RSP |
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| 349 | // ===== |
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| 350 | if ( in_ICACHE_RSP_VAL->read() and |
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| 351 | out_ICACHE_RSP_ACK->read()) |
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| 352 | { |
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| 353 | LABEL("ICACHE_RSP : transaction accepted"); |
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| 354 | LABEL(" * address : %.8x",list_req_icache.front()._addr); |
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| 355 | LABEL(" * list_req_icache : %d",list_req_icache.size()); |
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| 356 | list_req_icache.pop_front(); |
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| 357 | LABEL(" * list_req_icache : %d",list_req_icache.size()); |
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| 358 | |
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| 359 | } |
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| 360 | |
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| 361 | // ===== |
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| 362 | // ===== EVENT_RESET |
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| 363 | // ===== |
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| 364 | if ( in_EVENT_RESET_VAL->read() and |
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| 365 | out_EVENT_RESET_ACK->read() ) |
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| 366 | { |
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| 367 | LABEL("EVENT_RESET : transaction accepted"); |
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| 368 | list_wait_decod.clear(); |
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| 369 | } |
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| 370 | |
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| 371 | SC_START(1); |
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| 372 | |
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| 373 | for (list<entry_t>::iterator it=list_req_icache.begin(); it != list_req_icache.end(); it++) |
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| 374 | { |
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| 375 | LABEL("ICACHE : %d %d %.8x",it->_cycle, it->_packet, it->_addr); |
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| 376 | if (it->_cycle > 0) |
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| 377 | it->_cycle --; |
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| 378 | } |
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| 379 | } |
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| 380 | } |
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| 381 | |
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| 382 | /******************************************************** |
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| 383 | * Simulation - End |
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| 384 | ********************************************************/ |
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| 385 | |
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| 386 | TEST_OK ("End of Simulation"); |
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| 387 | delete _time; |
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| 388 | |
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| 389 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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| 390 | |
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| 391 | delete in_CLOCK; |
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| 392 | delete in_NRESET; |
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| 393 | delete in_ADDRESS_VAL ; |
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| 394 | delete out_ADDRESS_ACK ; |
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| 395 | delete out_ADDRESS_IFETCH_QUEUE_ID ; |
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| 396 | delete [] in_ADDRESS_INSTRUCTION_ENABLE ; |
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| 397 | delete in_ADDRESS_INSTRUCTION_ADDRESS ; |
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| 398 | delete in_ADDRESS_INST_IFETCH_PTR ; |
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| 399 | delete in_ADDRESS_BRANCH_STATE ; |
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| 400 | delete in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; |
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| 401 | delete [] out_DECOD_VAL ; |
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| 402 | delete [] in_DECOD_ACK ; |
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| 403 | delete [] out_DECOD_INSTRUCTION ; |
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| 404 | delete out_DECOD_ADDRESS ; |
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| 405 | delete out_DECOD_INST_IFETCH_PTR ; |
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| 406 | delete out_DECOD_BRANCH_STATE ; |
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| 407 | delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; |
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| 408 | delete out_DECOD_EXCEPTION ; |
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| 409 | delete in_ICACHE_RSP_VAL ; |
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| 410 | delete out_ICACHE_RSP_ACK ; |
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| 411 | delete in_ICACHE_RSP_PACKET_ID ; |
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| 412 | delete [] in_ICACHE_RSP_INSTRUCTION ; |
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| 413 | delete in_ICACHE_RSP_ERROR ; |
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| 414 | delete in_EVENT_RESET_VAL ; |
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| 415 | delete out_EVENT_RESET_ACK ; |
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| 416 | |
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| 417 | #endif |
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| 418 | |
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| 419 | delete _Ifetch_queue; |
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| 420 | #ifdef STATISTICS |
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| 421 | delete _parameters_statistics; |
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| 422 | #endif |
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| 423 | } |
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