1 | /* |
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2 | * $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #define NB_ITERATION 1 |
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10 | #define CYCLE_MAX (2048*NB_ITERATION) |
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11 | |
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12 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/include/test.h" |
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13 | #include "Common/include/Test.h" |
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14 | #include "Behavioural/include/Allocation.h" |
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15 | #include <list> |
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16 | #include <set> |
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17 | |
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18 | class entry_t |
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19 | { |
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20 | public : uint32_t _cycle; |
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21 | public : Tpacket_t _packet; |
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22 | public : Tgeneral_address_t _addr; |
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23 | |
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24 | public : entry_t (uint32_t cycle, |
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25 | Tpacket_t packet, |
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26 | Tgeneral_address_t addr ) |
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27 | { |
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28 | _cycle = cycle ; |
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29 | _packet = packet; |
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30 | _addr = addr ; |
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31 | } |
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32 | }; |
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33 | |
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34 | void test (string name, |
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35 | morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Parameters * _param) |
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36 | { |
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37 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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38 | |
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39 | #ifdef STATISTICS |
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40 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,1000); |
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41 | #endif |
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42 | |
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43 | Tusage_t _usage = USE_ALL; |
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44 | |
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45 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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46 | // _usage = usage_unset(_usage,USE_VHDL ); |
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47 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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48 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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49 | // _usage = usage_unset(_usage,USE_POSITION ); |
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50 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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51 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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52 | |
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53 | Ifetch_queue * _Ifetch_queue = new Ifetch_queue |
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54 | (name.c_str(), |
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55 | #ifdef STATISTICS |
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56 | _parameters_statistics, |
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57 | #endif |
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58 | _param, |
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59 | _usage); |
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60 | |
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61 | #ifdef SYSTEMC |
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62 | /********************************************************************* |
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63 | * Déclarations des signaux |
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64 | *********************************************************************/ |
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65 | string rename; |
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66 | |
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67 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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68 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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69 | |
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70 | ALLOC_SC_SIGNAL ( in_ADDRESS_VAL ," in_ADDRESS_VAL ",Tcontrol_t ); |
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71 | ALLOC_SC_SIGNAL (out_ADDRESS_ACK ,"out_ADDRESS_ACK ",Tcontrol_t ); |
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72 | ALLOC_SC_SIGNAL (out_ADDRESS_IFETCH_QUEUE_ID ,"out_ADDRESS_IFETCH_QUEUE_ID ",Tifetch_queue_ptr_t ); |
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73 | ALLOC1_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE ," in_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); |
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74 | ALLOC_SC_SIGNAL ( in_ADDRESS_INSTRUCTION_ADDRESS ," in_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t ); |
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75 | ALLOC_SC_SIGNAL ( in_ADDRESS_INST_IFETCH_PTR ," in_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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76 | ALLOC_SC_SIGNAL ( in_ADDRESS_BRANCH_STATE ," in_ADDRESS_BRANCH_STATE ",Tbranch_state_t ); |
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77 | ALLOC_SC_SIGNAL ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID," in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); |
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78 | ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_instruction); |
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79 | ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_instruction); |
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80 | ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION ,"out_DECOD_INSTRUCTION ",Tinstruction_t ,_param->_nb_instruction); |
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81 | ALLOC_SC_SIGNAL (out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t ); |
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82 | ALLOC_SC_SIGNAL (out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t ); |
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83 | ALLOC_SC_SIGNAL (out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t ); |
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84 | ALLOC_SC_SIGNAL (out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ); |
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85 | ALLOC_SC_SIGNAL (out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Tprediction_ptr_t ); |
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86 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t ); |
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87 | ALLOC_SC_SIGNAL (out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t ); |
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88 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t ); |
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89 | ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_instruction); |
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90 | ALLOC_SC_SIGNAL ( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t ); |
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91 | ALLOC_SC_SIGNAL ( in_EVENT_RESET_VAL ," in_EVENT_RESET_VAL ",Tcontrol_t ); |
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92 | ALLOC_SC_SIGNAL (out_EVENT_RESET_ACK ,"out_EVENT_RESET_ACK ",Tcontrol_t ); |
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93 | |
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94 | /******************************************************** |
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95 | * Instanciation |
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96 | ********************************************************/ |
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97 | |
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98 | msg(_("<%s> : Instanciation of _Ifetch_queue.\n"),name.c_str()); |
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99 | |
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100 | (*(_Ifetch_queue->in_CLOCK)) (*(in_CLOCK)); |
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101 | (*(_Ifetch_queue->in_NRESET)) (*(in_NRESET)); |
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102 | |
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103 | INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_VAL ); |
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104 | INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_ACK ); |
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105 | if (_param->_have_port_ifetch_queue_ptr) |
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106 | INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID ); |
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107 | INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction); |
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108 | INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS ); |
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109 | if (_param->_have_port_inst_ifetch_ptr) |
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110 | INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR ); |
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111 | INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_STATE ); |
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112 | if (_param->_have_port_depth) |
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113 | INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID); |
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114 | INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL ,_param->_nb_instruction); |
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115 | INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_DECOD_ACK ,_param->_nb_instruction); |
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116 | INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION ,_param->_nb_instruction); |
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117 | INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_ADDRESS ); |
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118 | if (_param->_have_port_inst_ifetch_ptr) |
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119 | INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_INST_IFETCH_PTR ); |
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120 | INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_STATE ); |
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121 | if (_param->_have_port_depth) |
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122 | INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID ); |
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123 | INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_EXCEPTION ); |
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124 | INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_VAL ); |
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125 | INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ICACHE_RSP_ACK ); |
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126 | if (_param->_have_port_ifetch_queue_ptr) |
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127 | INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_PACKET_ID ); |
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128 | INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction); |
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129 | INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_ERROR ); |
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130 | INSTANCE_SC_SIGNAL (_Ifetch_queue, in_EVENT_RESET_VAL ); |
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131 | INSTANCE_SC_SIGNAL (_Ifetch_queue,out_EVENT_RESET_ACK ); |
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132 | |
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133 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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134 | |
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135 | Time * _time = new Time(); |
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136 | |
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137 | /******************************************************** |
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138 | * Simulation - Begin |
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139 | ********************************************************/ |
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140 | |
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141 | // Initialisation |
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142 | |
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143 | const uint32_t seed = 0; |
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144 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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145 | |
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146 | srand(seed); |
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147 | |
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148 | const int32_t percent_transaction_address = 75; |
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149 | const int32_t percent_transaction_decod = 75; |
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150 | const int32_t percent_transaction_event_reset = 10; |
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151 | const int32_t percent_icache_hit = 100; |
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152 | const int32_t icache_miss_penality = 10; |
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153 | |
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154 | SC_START(0); |
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155 | LABEL("Initialisation"); |
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156 | |
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157 | LABEL("Reset"); |
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158 | in_NRESET->write(0); |
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159 | SC_START(5); |
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160 | in_NRESET->write(1); |
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161 | |
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162 | LABEL("Loop of Test"); |
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163 | |
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164 | list<Tgeneral_data_t> list_wait_decod; |
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165 | list<entry_t> list_req_icache; |
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166 | |
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167 | Tgeneral_data_t modulo_iberr = 23; |
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168 | Tinstruction_t xor_inst = 0xdeadbeef; |
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169 | Tgeneral_data_t address; |
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170 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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171 | { |
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172 | LABEL("Iteration %d",iteration); |
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173 | |
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174 | int32_t nb_request_in = 64; |
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175 | int32_t nb_request_out = 64; |
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176 | |
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177 | address = 0x100; |
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178 | |
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179 | list_wait_decod.clear(); |
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180 | |
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181 | while ((nb_request_in > 0) and |
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182 | (nb_request_out > 0)) |
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183 | { |
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184 | // ===== |
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185 | // ===== ADDRESS |
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186 | // ===== |
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187 | in_ADDRESS_VAL ->write((nb_request_in > 0) and ((rand()%100)<percent_transaction_address)); |
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188 | in_ADDRESS_INSTRUCTION_ADDRESS ->write(address); |
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189 | uint32_t nb_inst_enable = (rand() % _param->_nb_instruction); |
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190 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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191 | in_ADDRESS_INSTRUCTION_ENABLE [i] ->write(i<=nb_inst_enable); |
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192 | if (_param->_have_port_inst_ifetch_ptr) |
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193 | in_ADDRESS_INST_IFETCH_PTR ->write(address%_param->_nb_instruction); |
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194 | in_ADDRESS_BRANCH_STATE ->write(address%SIZE_BRANCH_STATE); |
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195 | if (_param->_have_port_depth) |
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196 | in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_depth); |
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197 | |
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198 | // ===== |
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199 | // ===== DECOD |
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200 | // ===== |
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201 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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202 | in_DECOD_ACK [i]->write(0); |
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203 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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204 | { |
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205 | if ((rand()%100)>percent_transaction_decod) |
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206 | break; |
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207 | in_DECOD_ACK [i]->write(1); |
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208 | } |
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209 | |
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210 | // ===== |
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211 | // ===== ICACHE_RSP |
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212 | // ===== |
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213 | Tcontrol_t icache_rsp_val = not list_req_icache.empty() and (list_req_icache.front()._cycle == 0); |
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214 | |
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215 | // LABEL("Test ICACHE_RSP :"); |
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216 | // LABEL(" * list_req_icache.empty() : %d",list_req_icache.empty()); |
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217 | // if (not list_req_icache.empty()) |
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218 | // LABEL(" * list_req_icache.front()._cycle : %d",list_req_icache.front()._cycle); |
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219 | |
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220 | in_ICACHE_RSP_VAL->write(icache_rsp_val); |
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221 | |
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222 | if (icache_rsp_val) |
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223 | { |
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224 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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225 | in_ICACHE_RSP_INSTRUCTION [i]->write((list_req_icache.front()._addr + 4*i)^xor_inst); |
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226 | in_ICACHE_RSP_PACKET_ID ->write(list_req_icache.front()._packet); |
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227 | in_ICACHE_RSP_ERROR ->write(((list_req_icache.front()._addr % modulo_iberr)==0)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE); |
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228 | } |
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229 | |
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230 | // ===== |
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231 | // ===== EVENT_RESET |
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232 | // ===== |
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233 | in_EVENT_RESET_VAL->write((rand()%100)<percent_transaction_event_reset); |
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234 | |
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235 | // ---------------------------------------------- |
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236 | // ---------------------------------------------- |
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237 | // ---------------------------------------------- |
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238 | SC_START(0); |
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239 | // ---------------------------------------------- |
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240 | // ---------------------------------------------- |
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241 | // ---------------------------------------------- |
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242 | |
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243 | // ===== |
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244 | // ===== ADDRESS |
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245 | // ===== |
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246 | if ( in_ADDRESS_VAL->read() and |
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247 | out_ADDRESS_ACK->read()) |
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248 | { |
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249 | LABEL("ADDRESS : transaction accepted"); |
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250 | LABEL(" * address : %.8x",address); |
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251 | |
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252 | list_wait_decod.push_back(address); |
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253 | // list_req_icache.insert(, entry_t((_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address)); |
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254 | |
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255 | uint32_t cycle = ((rand()%100)<percent_icache_hit)?1:icache_miss_penality; |
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256 | LABEL(" * cycle : %d",cycle); |
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257 | |
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258 | list<entry_t>::iterator it; |
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259 | for (it=list_req_icache.begin(); it != list_req_icache.end(); it++) |
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260 | if (cycle < it->_cycle) |
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261 | break; |
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262 | |
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263 | LABEL(" * list_req_icache : %d",list_req_icache.size()); |
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264 | list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address)); |
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265 | LABEL(" * list_req_icache : %d",list_req_icache.size()); |
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266 | address += 4*_param->_nb_instruction; |
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267 | } |
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268 | |
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269 | // ===== |
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270 | // ===== DECOD |
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271 | // ===== |
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272 | bool have_decod_transaction = false; |
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273 | uint32_t nb_decod_keep = 0; |
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274 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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275 | { |
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276 | if (out_DECOD_VAL [i]->read()) |
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277 | { |
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278 | LABEL("DECOD_VAL [%d] ",i); |
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279 | nb_decod_keep ++; |
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280 | |
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281 | if (in_DECOD_ACK [i]->read()) |
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282 | { |
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283 | LABEL("DECOD_ACK [%d] ",i); |
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284 | |
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285 | have_decod_transaction = true; |
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286 | nb_decod_keep --; |
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287 | |
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288 | TEST(bool , list_wait_decod.empty() , false); |
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289 | TEST(Tinstruction_t , out_DECOD_INSTRUCTION[i]->read(), (list_wait_decod.front()+4*i)^xor_inst); |
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290 | } |
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291 | } |
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292 | } |
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293 | |
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294 | if (have_decod_transaction) |
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295 | { |
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296 | |
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297 | Tgeneral_data_t addr = list_wait_decod.front(); |
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298 | |
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299 | LABEL("DECOD : transaction accepted"); |
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300 | LABEL(" * address : %.8x",addr); |
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301 | |
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302 | TEST(Tgeneral_data_t ,out_DECOD_ADDRESS ->read(), addr); |
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303 | TEST(Tbranch_state_t ,out_DECOD_BRANCH_STATE ->read(),addr%SIZE_BRANCH_STATE); |
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304 | if (_param->_have_port_inst_ifetch_ptr) |
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305 | TEST(Tinst_ifetch_ptr_t,out_DECOD_INST_IFETCH_PTR ->read(),addr%_param->_nb_instruction); |
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306 | if (_param->_have_port_depth) |
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307 | TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_depth); |
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308 | if ((addr % modulo_iberr) == 0) |
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309 | TEST(Texception_t ,out_DECOD_EXCEPTION ->read(),EXCEPTION_IFETCH_BUS_ERROR); |
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310 | else |
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311 | TEST(Texception_t ,out_DECOD_EXCEPTION ->read(),EXCEPTION_IFETCH_NONE ); |
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312 | |
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313 | // all is decod |
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314 | LABEL(" * nb_decod_keep : %d",nb_decod_keep); |
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315 | if (nb_decod_keep == 0) |
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316 | { |
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317 | LABEL(" * decod all bundle"); |
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318 | list_wait_decod.pop_front(); |
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319 | nb_request_out --; |
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320 | } |
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321 | } |
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322 | |
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323 | // ===== |
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324 | // ===== ICACHE_RSP |
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325 | // ===== |
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326 | if ( in_ICACHE_RSP_VAL->read() and |
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327 | out_ICACHE_RSP_ACK->read()) |
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328 | { |
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329 | LABEL("ICACHE_RSP : transaction accepted"); |
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330 | LABEL(" * address : %.8x",list_req_icache.front()._addr); |
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331 | LABEL(" * list_req_icache : %d",list_req_icache.size()); |
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332 | list_req_icache.pop_front(); |
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333 | LABEL(" * list_req_icache : %d",list_req_icache.size()); |
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334 | |
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335 | } |
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336 | |
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337 | // ===== |
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338 | // ===== EVENT_RESET |
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339 | // ===== |
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340 | if ( in_EVENT_RESET_VAL->read() and |
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341 | out_EVENT_RESET_ACK->read() ) |
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342 | { |
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343 | LABEL("EVENT_RESET : transaction accepted"); |
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344 | list_wait_decod.clear(); |
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345 | } |
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346 | |
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347 | SC_START(1); |
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348 | |
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349 | for (list<entry_t>::iterator it=list_req_icache.begin(); it != list_req_icache.end(); it++) |
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350 | { |
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351 | LABEL("ICACHE : %d %d %.8x",it->_cycle, it->_packet, it->_addr); |
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352 | if (it->_cycle > 0) |
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353 | it->_cycle --; |
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354 | } |
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355 | } |
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356 | } |
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357 | |
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358 | /******************************************************** |
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359 | * Simulation - End |
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360 | ********************************************************/ |
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361 | |
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362 | TEST_OK ("End of Simulation"); |
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363 | delete _time; |
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364 | |
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365 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
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366 | |
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367 | delete in_CLOCK; |
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368 | delete in_NRESET; |
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369 | delete in_ADDRESS_VAL ; |
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370 | delete out_ADDRESS_ACK ; |
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371 | delete out_ADDRESS_IFETCH_QUEUE_ID ; |
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372 | delete [] in_ADDRESS_INSTRUCTION_ENABLE ; |
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373 | delete in_ADDRESS_INSTRUCTION_ADDRESS ; |
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374 | delete in_ADDRESS_INST_IFETCH_PTR ; |
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375 | delete in_ADDRESS_BRANCH_STATE ; |
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376 | delete in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID; |
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377 | delete [] out_DECOD_VAL ; |
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378 | delete [] in_DECOD_ACK ; |
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379 | delete [] out_DECOD_INSTRUCTION ; |
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380 | delete out_DECOD_ADDRESS ; |
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381 | delete out_DECOD_INST_IFETCH_PTR ; |
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382 | delete out_DECOD_BRANCH_STATE ; |
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383 | delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ; |
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384 | delete out_DECOD_EXCEPTION ; |
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385 | delete in_ICACHE_RSP_VAL ; |
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386 | delete out_ICACHE_RSP_ACK ; |
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387 | delete in_ICACHE_RSP_PACKET_ID ; |
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388 | delete [] in_ICACHE_RSP_INSTRUCTION ; |
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389 | delete in_ICACHE_RSP_ERROR ; |
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390 | delete in_EVENT_RESET_VAL ; |
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391 | delete out_EVENT_RESET_ACK ; |
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392 | |
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393 | #endif |
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394 | |
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395 | delete _Ifetch_queue; |
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396 | #ifdef STATISTICS |
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397 | delete _parameters_statistics; |
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398 | #endif |
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399 | } |
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