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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/src/test.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 16 years ago
Almost complete design with Test and test platform
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1	/*
2	* $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX (2048*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15	#include <list>
16	#include <set>
17
18	class entry_t
19	{
20	public : uint32_t _cycle;
21	public : Tpacket_t _packet;
22	public : Tgeneral_address_t _addr;
23
24	public : entry_t (uint32_t cycle,
25	Tpacket_t packet,
26	Tgeneral_address_t addr )
27	{
28	_cycle = cycle ;
29	_packet = packet;
30	_addr = addr ;
31	}
32	};
33
34	void test (string name,
35	morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Parameters * _param)
36	{
37	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
38
39	#ifdef STATISTICS
40	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,1000);
41	#endif
42
43	Tusage_t _usage = USE_ALL;
44
45	// _usage = usage_unset(_usage,USE_SYSTEMC );
46	// _usage = usage_unset(_usage,USE_VHDL );
47	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
48	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
49	// _usage = usage_unset(_usage,USE_POSITION );
50	// _usage = usage_unset(_usage,USE_STATISTICS );
51	// _usage = usage_unset(_usage,USE_INFORMATION );
52
53	Ifetch_queue * _Ifetch_queue = new Ifetch_queue
54	(name.c_str(),
55	#ifdef STATISTICS
56	_parameters_statistics,
57	#endif
58	_param,
59	_usage);
60
61	#ifdef SYSTEMC
62	/*********************************************************************
63	* Déclarations des signaux
64	*********************************************************************/
65	string rename;
66
67	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
68	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
69
70	ALLOC_SC_SIGNAL ( in_ADDRESS_VAL ," in_ADDRESS_VAL ",Tcontrol_t );
71	ALLOC_SC_SIGNAL (out_ADDRESS_ACK ,"out_ADDRESS_ACK ",Tcontrol_t );
72	ALLOC_SC_SIGNAL (out_ADDRESS_IFETCH_QUEUE_ID ,"out_ADDRESS_IFETCH_QUEUE_ID ",Tifetch_queue_ptr_t );
73	ALLOC1_SC_SIGNAL( in_ADDRESS_INSTRUCTION_ENABLE ," in_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
74	ALLOC_SC_SIGNAL ( in_ADDRESS_INSTRUCTION_ADDRESS ," in_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t );
75	ALLOC_SC_SIGNAL ( in_ADDRESS_INST_IFETCH_PTR ," in_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t );
76	ALLOC_SC_SIGNAL ( in_ADDRESS_BRANCH_STATE ," in_ADDRESS_BRANCH_STATE ",Tbranch_state_t );
77	ALLOC_SC_SIGNAL ( in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID," in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
78	ALLOC1_SC_SIGNAL(out_DECOD_VAL ,"out_DECOD_VAL ",Tcontrol_t ,_param->_nb_instruction);
79	ALLOC1_SC_SIGNAL( in_DECOD_ACK ," in_DECOD_ACK ",Tcontrol_t ,_param->_nb_instruction);
80	ALLOC1_SC_SIGNAL(out_DECOD_INSTRUCTION ,"out_DECOD_INSTRUCTION ",Tinstruction_t ,_param->_nb_instruction);
81	ALLOC_SC_SIGNAL (out_DECOD_ADDRESS ,"out_DECOD_ADDRESS ",Tgeneral_address_t );
82	ALLOC_SC_SIGNAL (out_DECOD_INST_IFETCH_PTR ,"out_DECOD_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t );
83	ALLOC_SC_SIGNAL (out_DECOD_BRANCH_STATE ,"out_DECOD_BRANCH_STATE ",Tbranch_state_t );
84	ALLOC_SC_SIGNAL (out_DECOD_BRANCH_UPDATE_PREDICTION_ID ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID ",Tprediction_ptr_t );
85	ALLOC_SC_SIGNAL (out_DECOD_EXCEPTION ,"out_DECOD_EXCEPTION ",Tprediction_ptr_t );
86	ALLOC_SC_SIGNAL ( in_ICACHE_RSP_VAL ," in_ICACHE_RSP_VAL ",Tcontrol_t );
87	ALLOC_SC_SIGNAL (out_ICACHE_RSP_ACK ,"out_ICACHE_RSP_ACK ",Tcontrol_t );
88	ALLOC_SC_SIGNAL ( in_ICACHE_RSP_PACKET_ID ," in_ICACHE_RSP_PACKET_ID ",Tpacket_t );
89	ALLOC1_SC_SIGNAL( in_ICACHE_RSP_INSTRUCTION ," in_ICACHE_RSP_INSTRUCTION ",Ticache_instruction_t,_param->_nb_instruction);
90	ALLOC_SC_SIGNAL ( in_ICACHE_RSP_ERROR ," in_ICACHE_RSP_ERROR ",Ticache_error_t );
91	ALLOC_SC_SIGNAL ( in_EVENT_RESET_VAL ," in_EVENT_RESET_VAL ",Tcontrol_t );
92	ALLOC_SC_SIGNAL (out_EVENT_RESET_ACK ,"out_EVENT_RESET_ACK ",Tcontrol_t );
93
94	/********************************************************
95	* Instanciation
96	********************************************************/
97
98	msg(_("<%s> : Instanciation of _Ifetch_queue.\n"),name.c_str());
99
100	((_Ifetch_queue->in_CLOCK)) ((in_CLOCK));
101	((_Ifetch_queue->in_NRESET)) ((in_NRESET));
102
103	INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_VAL );
104	INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_ACK );
105	if (_param->_have_port_ifetch_queue_ptr)
106	INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ADDRESS_IFETCH_QUEUE_ID );
107	INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction);
108	INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INSTRUCTION_ADDRESS );
109	if (_param->_have_port_inst_ifetch_ptr)
110	INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_INST_IFETCH_PTR );
111	INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_STATE );
112	if (_param->_have_port_depth)
113	INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
114	INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_VAL ,_param->_nb_instruction);
115	INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_DECOD_ACK ,_param->_nb_instruction);
116	INSTANCE1_SC_SIGNAL(_Ifetch_queue,out_DECOD_INSTRUCTION ,_param->_nb_instruction);
117	INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_ADDRESS );
118	if (_param->_have_port_inst_ifetch_ptr)
119	INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_INST_IFETCH_PTR );
120	INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_STATE );
121	if (_param->_have_port_depth)
122	INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_BRANCH_UPDATE_PREDICTION_ID );
123	INSTANCE_SC_SIGNAL (_Ifetch_queue,out_DECOD_EXCEPTION );
124	INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_VAL );
125	INSTANCE_SC_SIGNAL (_Ifetch_queue,out_ICACHE_RSP_ACK );
126	if (_param->_have_port_ifetch_queue_ptr)
127	INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_PACKET_ID );
128	INSTANCE1_SC_SIGNAL(_Ifetch_queue, in_ICACHE_RSP_INSTRUCTION ,_param->_nb_instruction);
129	INSTANCE_SC_SIGNAL (_Ifetch_queue, in_ICACHE_RSP_ERROR );
130	INSTANCE_SC_SIGNAL (_Ifetch_queue, in_EVENT_RESET_VAL );
131	INSTANCE_SC_SIGNAL (_Ifetch_queue,out_EVENT_RESET_ACK );
132
133	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
134
135	Time * _time = new Time();
136
137	/********************************************************
138	* Simulation - Begin
139	********************************************************/
140
141	// Initialisation
142
143	const uint32_t seed = 0;
144	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
145
146	srand(seed);
147
148	const int32_t percent_transaction_address = 75;
149	const int32_t percent_transaction_decod = 75;
150	const int32_t percent_transaction_event_reset = 10;
151	const int32_t percent_icache_hit = 100;
152	const int32_t icache_miss_penality = 10;
153
154	SC_START(0);
155	LABEL("Initialisation");
156
157	LABEL("Reset");
158	in_NRESET->write(0);
159	SC_START(5);
160	in_NRESET->write(1);
161
162	LABEL("Loop of Test");
163
164	list<Tgeneral_data_t> list_wait_decod;
165	list<entry_t> list_req_icache;
166
167	Tgeneral_data_t modulo_iberr = 23;
168	Tinstruction_t xor_inst = 0xdeadbeef;
169	Tgeneral_data_t address;
170	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
171	{
172	LABEL("Iteration %d",iteration);
173
174	int32_t nb_request_in = 64;
175	int32_t nb_request_out = 64;
176
177	address = 0x100;
178
179	list_wait_decod.clear();
180
181	while ((nb_request_in > 0) and
182	(nb_request_out > 0))
183	{
184	// =====
185	// ===== ADDRESS
186	// =====
187	in_ADDRESS_VAL ->write((nb_request_in > 0) and ((rand()%100)<percent_transaction_address));
188	in_ADDRESS_INSTRUCTION_ADDRESS ->write(address);
189	uint32_t nb_inst_enable = (rand() % _param->_nb_instruction);
190	for (uint32_t i=0; i<_param->_nb_instruction; i++)
191	in_ADDRESS_INSTRUCTION_ENABLE [i] ->write(i<=nb_inst_enable);
192	if (_param->_have_port_inst_ifetch_ptr)
193	in_ADDRESS_INST_IFETCH_PTR ->write(address%_param->_nb_instruction);
194	in_ADDRESS_BRANCH_STATE ->write(address%SIZE_BRANCH_STATE);
195	if (_param->_have_port_depth)
196	in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID ->write(address%_param->_size_depth);
197
198	// =====
199	// ===== DECOD
200	// =====
201	for (uint32_t i=0; i<_param->_nb_instruction; i++)
202	in_DECOD_ACK [i]->write(0);
203	for (uint32_t i=0; i<_param->_nb_instruction; i++)
204	{
205	if ((rand()%100)>percent_transaction_decod)
206	break;
207	in_DECOD_ACK [i]->write(1);
208	}
209
210	// =====
211	// ===== ICACHE_RSP
212	// =====
213	Tcontrol_t icache_rsp_val = not list_req_icache.empty() and (list_req_icache.front()._cycle == 0);
214
215	// LABEL("Test ICACHE_RSP :");
216	// LABEL(" * list_req_icache.empty() : %d",list_req_icache.empty());
217	// if (not list_req_icache.empty())
218	// LABEL(" * list_req_icache.front()._cycle : %d",list_req_icache.front()._cycle);
219
220	in_ICACHE_RSP_VAL->write(icache_rsp_val);
221
222	if (icache_rsp_val)
223	{
224	for (uint32_t i=0; i<_param->_nb_instruction; i++)
225	in_ICACHE_RSP_INSTRUCTION [i]->write((list_req_icache.front()._addr + 4*i)^xor_inst);
226	in_ICACHE_RSP_PACKET_ID ->write(list_req_icache.front()._packet);
227	in_ICACHE_RSP_ERROR ->write(((list_req_icache.front()._addr % modulo_iberr)==0)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
228	}
229
230	// =====
231	// ===== EVENT_RESET
232	// =====
233	in_EVENT_RESET_VAL->write((rand()%100)<percent_transaction_event_reset);
234
235	// ----------------------------------------------
236	// ----------------------------------------------
237	// ----------------------------------------------
238	SC_START(0);
239	// ----------------------------------------------
240	// ----------------------------------------------
241	// ----------------------------------------------
242
243	// =====
244	// ===== ADDRESS
245	// =====
246	if ( in_ADDRESS_VAL->read() and
247	out_ADDRESS_ACK->read())
248	{
249	LABEL("ADDRESS : transaction accepted");
250	LABEL(" * address : %.8x",address);
251
252	list_wait_decod.push_back(address);
253	// list_req_icache.insert(, entry_t((_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
254
255	uint32_t cycle = ((rand()%100)<percent_icache_hit)?1:icache_miss_penality;
256	LABEL(" * cycle : %d",cycle);
257
258	list<entry_t>::iterator it;
259	for (it=list_req_icache.begin(); it != list_req_icache.end(); it++)
260	if (cycle < it->_cycle)
261	break;
262
263	LABEL(" * list_req_icache : %d",list_req_icache.size());
264	list_req_icache.insert(it,entry_t(cycle,(_param->_have_port_ifetch_queue_ptr)?out_ADDRESS_IFETCH_QUEUE_ID->read():0,address));
265	LABEL(" * list_req_icache : %d",list_req_icache.size());
266	address += 4*_param->_nb_instruction;
267	}
268
269	// =====
270	// ===== DECOD
271	// =====
272	bool have_decod_transaction = false;
273	uint32_t nb_decod_keep = 0;
274	for (uint32_t i=0; i<_param->_nb_instruction; i++)
275	{
276	if (out_DECOD_VAL [i]->read())
277	{
278	LABEL("DECOD_VAL [%d] ",i);
279	nb_decod_keep ++;
280
281	if (in_DECOD_ACK [i]->read())
282	{
283	LABEL("DECOD_ACK [%d] ",i);
284
285	have_decod_transaction = true;
286	nb_decod_keep --;
287
288	TEST(bool , list_wait_decod.empty() , false);
289	TEST(Tinstruction_t , out_DECOD_INSTRUCTION[i]->read(), (list_wait_decod.front()+4*i)^xor_inst);
290	}
291	}
292	}
293
294	if (have_decod_transaction)
295	{
296
297	Tgeneral_data_t addr = list_wait_decod.front();
298
299	LABEL("DECOD : transaction accepted");
300	LABEL(" * address : %.8x",addr);
301
302	TEST(Tgeneral_data_t ,out_DECOD_ADDRESS ->read(), addr);
303	TEST(Tbranch_state_t ,out_DECOD_BRANCH_STATE ->read(),addr%SIZE_BRANCH_STATE);
304	if (_param->_have_port_inst_ifetch_ptr)
305	TEST(Tinst_ifetch_ptr_t,out_DECOD_INST_IFETCH_PTR ->read(),addr%_param->_nb_instruction);
306	if (_param->_have_port_depth)
307	TEST(Tprediction_ptr_t ,out_DECOD_BRANCH_UPDATE_PREDICTION_ID->read(),addr%_param->_size_depth);
308	if ((addr % modulo_iberr) == 0)
309	TEST(Texception_t ,out_DECOD_EXCEPTION ->read(),EXCEPTION_IFETCH_BUS_ERROR);
310	else
311	TEST(Texception_t ,out_DECOD_EXCEPTION ->read(),EXCEPTION_IFETCH_NONE );
312
313	// all is decod
314	LABEL(" * nb_decod_keep : %d",nb_decod_keep);
315	if (nb_decod_keep == 0)
316	{
317	LABEL(" * decod all bundle");
318	list_wait_decod.pop_front();
319	nb_request_out --;
320	}
321	}
322
323	// =====
324	// ===== ICACHE_RSP
325	// =====
326	if ( in_ICACHE_RSP_VAL->read() and
327	out_ICACHE_RSP_ACK->read())
328	{
329	LABEL("ICACHE_RSP : transaction accepted");
330	LABEL(" * address : %.8x",list_req_icache.front()._addr);
331	LABEL(" * list_req_icache : %d",list_req_icache.size());
332	list_req_icache.pop_front();
333	LABEL(" * list_req_icache : %d",list_req_icache.size());
334
335	}
336
337	// =====
338	// ===== EVENT_RESET
339	// =====
340	if ( in_EVENT_RESET_VAL->read() and
341	out_EVENT_RESET_ACK->read() )
342	{
343	LABEL("EVENT_RESET : transaction accepted");
344	list_wait_decod.clear();
345	}
346
347	SC_START(1);
348
349	for (list<entry_t>::iterator it=list_req_icache.begin(); it != list_req_icache.end(); it++)
350	{
351	LABEL("ICACHE : %d %d %.8x",it->_cycle, it->_packet, it->_addr);
352	if (it->_cycle > 0)
353	it->_cycle --;
354	}
355	}
356	}
357
358	/********************************************************
359	* Simulation - End
360	********************************************************/
361
362	TEST_OK ("End of Simulation");
363	delete _time;
364
365	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
366
367	delete in_CLOCK;
368	delete in_NRESET;
369	delete in_ADDRESS_VAL ;
370	delete out_ADDRESS_ACK ;
371	delete out_ADDRESS_IFETCH_QUEUE_ID ;
372	delete [] in_ADDRESS_INSTRUCTION_ENABLE ;
373	delete in_ADDRESS_INSTRUCTION_ADDRESS ;
374	delete in_ADDRESS_INST_IFETCH_PTR ;
375	delete in_ADDRESS_BRANCH_STATE ;
376	delete in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
377	delete [] out_DECOD_VAL ;
378	delete [] in_DECOD_ACK ;
379	delete [] out_DECOD_INSTRUCTION ;
380	delete out_DECOD_ADDRESS ;
381	delete out_DECOD_INST_IFETCH_PTR ;
382	delete out_DECOD_BRANCH_STATE ;
383	delete out_DECOD_BRANCH_UPDATE_PREDICTION_ID ;
384	delete out_DECOD_EXCEPTION ;
385	delete in_ICACHE_RSP_VAL ;
386	delete out_ICACHE_RSP_ACK ;
387	delete in_ICACHE_RSP_PACKET_ID ;
388	delete [] in_ICACHE_RSP_INSTRUCTION ;
389	delete in_ICACHE_RSP_ERROR ;
390	delete in_EVENT_RESET_VAL ;
391	delete out_EVENT_RESET_ACK ;
392
393	#endif
394
395	delete _Ifetch_queue;
396	#ifdef STATISTICS
397	delete _parameters_statistics;
398	#endif
399	}

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