1 | #ifdef SYSTEMC |
---|
2 | /* |
---|
3 | * $Id: Ifetch_queue_function_full_assoc_genMoore.cpp 136 2009-10-20 18:52:15Z rosiere $ |
---|
4 | * |
---|
5 | * [ Description ] |
---|
6 | * |
---|
7 | */ |
---|
8 | |
---|
9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" |
---|
10 | |
---|
11 | namespace morpheo { |
---|
12 | namespace behavioural { |
---|
13 | namespace core { |
---|
14 | namespace multi_front_end { |
---|
15 | namespace front_end { |
---|
16 | namespace ifetch_unit { |
---|
17 | namespace ifetch_queue { |
---|
18 | |
---|
19 | #undef FUNCTION |
---|
20 | #define FUNCTION "Ifetch_queue::function_full_assoc_genMoore" |
---|
21 | void Ifetch_queue::function_full_assoc_genMoore (void) |
---|
22 | { |
---|
23 | log_begin(Ifetch_queue,FUNCTION); |
---|
24 | log_function(Ifetch_queue,FUNCTION,_name.c_str()); |
---|
25 | |
---|
26 | if (PORT_READ(in_NRESET)) |
---|
27 | { |
---|
28 | // ========================================================== |
---|
29 | // =====[ ADDRESS ]========================================== |
---|
30 | // ========================================================== |
---|
31 | { |
---|
32 | internal_ADDRESS_ACK = (_queue[reg_PTR_WRITE]->_state == IFETCH_QUEUE_STATE_EMPTY); |
---|
33 | |
---|
34 | log_printf(TRACE,Ifetch_queue,FUNCTION," * ADDRESS_ACK : %d",internal_ADDRESS_ACK); |
---|
35 | |
---|
36 | if (_param->_have_port_ifetch_queue_ptr) |
---|
37 | PORT_WRITE(out_ADDRESS_IFETCH_QUEUE_ID, reg_PTR_WRITE); |
---|
38 | } |
---|
39 | |
---|
40 | // ========================================================== |
---|
41 | // =====[ DECOD ]============================================ |
---|
42 | // ========================================================== |
---|
43 | { |
---|
44 | bool stop = false; |
---|
45 | uint32_t inst = 0; |
---|
46 | |
---|
47 | // init |
---|
48 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
---|
49 | internal_DECOD_VAL [i] = 0; |
---|
50 | |
---|
51 | for (uint32_t i=0; i<_param->_size_queue; ++i) |
---|
52 | { |
---|
53 | uint32_t ptr = (reg_PTR_READ+i)%_param->_size_queue; |
---|
54 | |
---|
55 | // Test if have an respons |
---|
56 | if (_queue[ptr]->_state == IFETCH_QUEUE_STATE_HAVE_RSP) |
---|
57 | { |
---|
58 | for (uint32_t j=0; j<_param->_nb_instruction; j++) |
---|
59 | { |
---|
60 | // test if instruction is enable |
---|
61 | if (_queue[ptr]->_instruction_enable [j]) |
---|
62 | { |
---|
63 | log_printf(TRACE,Ifetch_queue,FUNCTION," * DECOD_VAL [%d] : ifetch_queue[%d][%d]",inst,ptr,j); |
---|
64 | |
---|
65 | // Find an valid instruction |
---|
66 | internal_DECOD_VAL [inst] = true; |
---|
67 | internal_DECOD_PTR [inst] = ptr; |
---|
68 | internal_DECOD_SLOT[inst] = j; |
---|
69 | |
---|
70 | // Get info |
---|
71 | Tgeneral_address_t address = _queue[ptr]->_address; |
---|
72 | Tinst_ifetch_ptr_t inst_ifetch_ptr = _queue[ptr]->_inst_ifetch_ptr; |
---|
73 | Tbranch_state_t branch_state = _queue[ptr]->_branch_state; |
---|
74 | Tprediction_ptr_t branch_update_prediction_id = _queue[ptr]->_branch_update_prediction_id; |
---|
75 | Texception_t exception = _queue[ptr]->_exception; |
---|
76 | |
---|
77 | PORT_WRITE(out_DECOD_INSTRUCTION [inst],_queue[ptr]->_instruction [j]); |
---|
78 | PORT_WRITE(out_DECOD_ADDRESS [inst],address+j); |
---|
79 | |
---|
80 | // Warning : ONE BRANCH PER SLOT |
---|
81 | if (inst_ifetch_ptr == j) |
---|
82 | PORT_WRITE(out_DECOD_BRANCH_STATE [inst],branch_state); |
---|
83 | else |
---|
84 | PORT_WRITE(out_DECOD_BRANCH_STATE [inst],BRANCH_STATE_NONE); |
---|
85 | if (_param->_have_port_depth) |
---|
86 | PORT_WRITE(out_DECOD_BRANCH_UPDATE_PREDICTION_ID[inst],branch_update_prediction_id); |
---|
87 | PORT_WRITE(out_DECOD_EXCEPTION [inst],exception); // all is same |
---|
88 | |
---|
89 | inst ++; |
---|
90 | |
---|
91 | // Test if have all slot |
---|
92 | if (inst >= _param->_nb_instruction) |
---|
93 | stop = true; |
---|
94 | } |
---|
95 | if (stop) |
---|
96 | break; |
---|
97 | } |
---|
98 | } |
---|
99 | else |
---|
100 | stop = true; // slot have not respons -> exit the loop |
---|
101 | |
---|
102 | // if not find an valid instruction, break the loop |
---|
103 | if (stop) |
---|
104 | break; |
---|
105 | } |
---|
106 | } |
---|
107 | } |
---|
108 | else |
---|
109 | { |
---|
110 | // Reset |
---|
111 | internal_ADDRESS_ACK = 0; |
---|
112 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
113 | internal_DECOD_VAL [i] = 0; |
---|
114 | |
---|
115 | } |
---|
116 | |
---|
117 | // Write Output |
---|
118 | PORT_WRITE(out_ADDRESS_ACK , internal_ADDRESS_ACK); |
---|
119 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
---|
120 | PORT_WRITE(out_DECOD_VAL [i], internal_DECOD_VAL [i]); |
---|
121 | |
---|
122 | log_end(Ifetch_queue,FUNCTION); |
---|
123 | }; |
---|
124 | |
---|
125 | }; // end namespace ifetch_queue |
---|
126 | }; // end namespace ifetch_unit |
---|
127 | }; // end namespace front_end |
---|
128 | }; // end namespace multi_front_end |
---|
129 | }; // end namespace core |
---|
130 | }; // end namespace behavioural |
---|
131 | }; // end namespace morpheo |
---|
132 | #endif |
---|