[136] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: Ifetch_queue_function_full_assoc_transition.cpp 136 2009-10-20 18:52:15Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Ifetch_queue/include/Ifetch_queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace core { |
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| 14 | namespace multi_front_end { |
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| 15 | namespace front_end { |
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| 16 | namespace ifetch_unit { |
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| 17 | namespace ifetch_queue { |
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| 18 | |
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| 19 | |
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| 20 | #undef FUNCTION |
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| 21 | #define FUNCTION "Ifetch_queue::function_full_assoc_transition" |
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| 22 | void Ifetch_queue::function_full_assoc_transition (void) |
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| 23 | { |
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| 24 | log_begin(Ifetch_queue,FUNCTION); |
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| 25 | log_function(Ifetch_queue,FUNCTION,_name.c_str()); |
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| 26 | |
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| 27 | if (PORT_READ(in_NRESET) == 0) |
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| 28 | { |
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| 29 | reg_PTR_READ = 0; |
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| 30 | reg_PTR_WRITE = 0; |
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| 31 | |
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| 32 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 33 | { |
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| 34 | _queue [i]->_state = IFETCH_QUEUE_STATE_EMPTY; |
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| 35 | _queue [i]->_address = 0; // not necessary |
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| 36 | _queue [i]->_inst_ifetch_ptr = 0; // not necessary |
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| 37 | _queue [i]->_branch_state = 0; // not necessary |
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| 38 | _queue [i]->_branch_update_prediction_id = 0; // not necessary |
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| 39 | _queue [i]->_exception = 0; // not necessary |
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| 40 | |
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| 41 | for (uint32_t j=0; j<_param->_nb_instruction; j++) |
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| 42 | { |
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| 43 | _queue [i]->_instruction [j] = 0; // not necessary |
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| 44 | _queue [i]->_instruction_enable [j] = 0; // not necessary |
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| 45 | } |
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| 46 | } |
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| 47 | } |
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| 48 | else |
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| 49 | { |
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| 50 | // ========================================================== |
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| 51 | // =====[ ADDRESS ]========================================== |
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| 52 | // ========================================================== |
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| 53 | if (PORT_READ(in_ADDRESS_VAL) and internal_ADDRESS_ACK) |
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| 54 | { |
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| 55 | log_printf(TRACE,Ifetch_queue,FUNCTION," * ADDRESS : Transaction"); |
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| 56 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); |
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| 57 | log_printf(TRACE,Ifetch_queue,FUNCTION," * ADDRESS : 0x%x",PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS)); |
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| 58 | |
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| 59 | // New slot in ifetch_queue is allocated |
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| 60 | |
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| 61 | _queue[reg_PTR_WRITE]->_state = IFETCH_QUEUE_STATE_WAIT_RSP; |
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| 62 | |
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| 63 | #ifdef STATISTICS |
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| 64 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 65 | (*_sum_transaction_address) ++; |
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| 66 | #endif |
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| 67 | |
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| 68 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 69 | { |
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| 70 | Tcontrol_t enable = PORT_READ(in_ADDRESS_INSTRUCTION_ENABLE [i]); |
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| 71 | #ifdef STATISTICS |
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| 72 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 73 | (*_sum_inst_enable) += enable; |
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| 74 | #endif |
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| 75 | _queue[reg_PTR_WRITE]->_instruction_enable [i] = enable; |
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| 76 | } |
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| 77 | |
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| 78 | _queue[reg_PTR_WRITE]->_address = PORT_READ(in_ADDRESS_INSTRUCTION_ADDRESS); |
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| 79 | _queue[reg_PTR_WRITE]->_inst_ifetch_ptr = (_param->_have_port_inst_ifetch_ptr)?PORT_READ(in_ADDRESS_INST_IFETCH_PTR ):0; |
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| 80 | _queue[reg_PTR_WRITE]->_branch_state = PORT_READ(in_ADDRESS_BRANCH_STATE); |
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| 81 | _queue[reg_PTR_WRITE]->_branch_update_prediction_id = (_param->_have_port_depth)?PORT_READ(in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID):0; |
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| 82 | |
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| 83 | reg_PTR_WRITE = (reg_PTR_WRITE+1)%_param->_size_queue; |
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| 84 | } |
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| 85 | |
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| 86 | // ========================================================== |
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| 87 | // =====[ DECOD ]============================================ |
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| 88 | // ========================================================== |
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| 89 | bool have_instruction_decod = false; |
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| 90 | bool have_instruction_enable = false; |
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| 91 | uint32_t last_ptr = reg_PTR_READ; |
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| 92 | |
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| 93 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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| 94 | { |
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| 95 | if (internal_DECOD_VAL [i] and PORT_READ(in_DECOD_ACK[i])) |
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| 96 | { |
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| 97 | log_printf(TRACE,Ifetch_queue,FUNCTION," * DECOD [%d] : Transaction",i); |
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| 98 | |
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| 99 | uint32_t ptr = internal_DECOD_PTR [i]; |
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| 100 | uint32_t slot = internal_DECOD_SLOT[i]; |
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| 101 | |
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| 102 | have_instruction_decod = true; |
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| 103 | last_ptr = ptr; |
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| 104 | |
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| 105 | _queue[ptr]->_instruction_enable [slot] = false; |
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| 106 | } |
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| 107 | have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i]; |
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| 108 | } |
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| 109 | |
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| 110 | // Test if all is decoded |
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| 111 | if (have_instruction_decod) |
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| 112 | { |
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| 113 | // Invalid all ptr |
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| 114 | while (reg_PTR_READ != last_ptr) |
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| 115 | { |
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| 116 | #ifdef DEBUG_TEST |
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| 117 | bool have_instruction_enable = false; |
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| 118 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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| 119 | have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i]; |
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| 120 | |
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| 121 | if (have_instruction_enable) |
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| 122 | throw ERRORMORPHEO(FUNCTION,toString("Can't free : Ifetch_queue[%d] content an valid instruction.\n",reg_PTR_READ)); |
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| 123 | #endif |
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| 124 | |
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| 125 | _queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY; |
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| 126 | reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue; |
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| 127 | } |
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| 128 | |
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| 129 | // For last ptr, test if all instruction is disable |
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| 130 | bool have_instruction_enable = false; |
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| 131 | for (uint32_t i=0; i<_param->_nb_instruction; ++i) |
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| 132 | have_instruction_enable |= _queue[reg_PTR_READ]->_instruction_enable [i]; |
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| 133 | |
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| 134 | if (not have_instruction_enable) |
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| 135 | { |
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| 136 | _queue[reg_PTR_READ]->_state = IFETCH_QUEUE_STATE_EMPTY; |
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| 137 | reg_PTR_READ = (reg_PTR_READ+1)%_param->_size_queue; |
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| 138 | } |
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| 139 | } |
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| 140 | |
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| 141 | // ========================================================== |
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| 142 | // =====[ ICACHE_RSP ]======================================= |
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| 143 | // ========================================================== |
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| 144 | if (PORT_READ(in_ICACHE_RSP_VAL) and internal_ICACHE_RSP_ACK) |
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| 145 | { |
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| 146 | log_printf(TRACE,Ifetch_queue,FUNCTION," * ICACHE_RSP : Transaction"); |
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| 147 | |
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| 148 | Tpacket_t ptr = (_param->_have_port_ifetch_queue_ptr)?PORT_READ(in_ICACHE_RSP_PACKET_ID):0; |
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| 149 | |
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| 150 | for (uint32_t i=0; i<_param->_nb_instruction; i++) |
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| 151 | _queue[ptr]->_instruction [i] = PORT_READ(in_ICACHE_RSP_INSTRUCTION [i]); |
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| 152 | |
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| 153 | switch (PORT_READ(in_ICACHE_RSP_ERROR)) |
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| 154 | { |
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| 155 | case ICACHE_ERROR_NONE : _queue[ptr]->_exception = EXCEPTION_IFETCH_NONE ; break; |
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| 156 | case ICACHE_ERROR_BUS_ERROR : _queue[ptr]->_exception = EXCEPTION_IFETCH_BUS_ERROR; break; |
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| 157 | default : throw ERRORMORPHEO(FUNCTION,"icache_rsp_error : unknow value."); |
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| 158 | } |
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| 159 | |
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| 160 | switch (_queue[ptr]->_state) |
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| 161 | { |
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| 162 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_HAVE_RSP; break; |
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| 163 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : _queue[ptr]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
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| 164 | default : throw ERRORMORPHEO(FUNCTION,"icache_rsp : invalid ifetch_queue state."); |
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| 165 | } |
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| 166 | } |
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| 167 | |
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| 168 | // ========================================================== |
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| 169 | // =====[ EVENT_RESET ]====================================== |
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| 170 | // ========================================================== |
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| 171 | if (PORT_READ(in_EVENT_RESET_VAL) and internal_EVENT_RESET_ACK) |
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| 172 | { |
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| 173 | log_printf(TRACE,Ifetch_queue,FUNCTION," * EVENT_RESET : Transaction"); |
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| 174 | |
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| 175 | // Scan all entry of queue and test the status |
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| 176 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 177 | switch (_queue[i]->_state) |
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| 178 | { |
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| 179 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : break; |
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| 180 | case IFETCH_QUEUE_STATE_WAIT_RSP : _queue[i]->_state = IFETCH_QUEUE_STATE_ERROR_WAIT_RSP; break; |
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| 181 | default : _queue[i]->_state = IFETCH_QUEUE_STATE_EMPTY ; break; |
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| 182 | } |
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| 183 | |
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| 184 | // all entry is empty (or wait respons to flush) |
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| 185 | // reset ptr |
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| 186 | // 1) reg_PTR_READ = reg_PTR_WRITE = = 0 |
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| 187 | // 2) reg_PTR_READ = reg_PTR_WRITE |
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| 188 | // In method 1), the probalitie than the entry pointed by reg_PTR_WRITE is a slot with state "error_wait_rsp" is more importate that the method 2) |
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| 189 | reg_PTR_READ = reg_PTR_WRITE; |
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| 190 | } |
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| 191 | |
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| 192 | #if defined(DEBUG) and (DEBUG >= DEBUG_TRACE) |
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| 193 | log_printf(TRACE,Ifetch_queue,FUNCTION," * Dump ifetch_queue"); |
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| 194 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_WRITE : %d",reg_PTR_WRITE); |
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| 195 | log_printf(TRACE,Ifetch_queue,FUNCTION," * reg_PTR_READ : %d",reg_PTR_READ ); |
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| 196 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 197 | { |
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| 198 | log_printf(TRACE,Ifetch_queue,FUNCTION," * [%d] 0x%.8x (0x%.8x) %d - %d %d %d - %s", |
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| 199 | i, |
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| 200 | _queue [i]->_address, |
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| 201 | _queue [i]->_address<<2, |
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| 202 | _queue [i]->_inst_ifetch_ptr, |
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| 203 | _queue [i]->_branch_state, |
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| 204 | _queue [i]->_branch_update_prediction_id, |
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| 205 | _queue [i]->_exception, |
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| 206 | toString(_queue [i]->_state).c_str() |
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| 207 | ); |
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| 208 | |
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| 209 | for (uint32_t j=0; j<_param->_nb_instruction; j++) |
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| 210 | log_printf(TRACE,Ifetch_queue,FUNCTION," * %d 0x%.8x", _queue [i]->_instruction_enable[j], _queue [i]->_instruction[j]); |
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| 211 | } |
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| 212 | #endif |
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| 213 | |
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| 214 | #ifdef STATISTICS |
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| 215 | if (usage_is_set(_usage,USE_STATISTICS)) |
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| 216 | for (uint32_t i=0; i<_param->_size_queue; i++) |
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| 217 | switch (_queue[i]->_state) |
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| 218 | { |
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| 219 | case IFETCH_QUEUE_STATE_EMPTY : break; |
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| 220 | case IFETCH_QUEUE_STATE_WAIT_RSP : (*_sum_use_queue_wait_rsp ) ++; break; |
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| 221 | case IFETCH_QUEUE_STATE_HAVE_RSP : (*_sum_use_queue_have_rsp ) ++; break; |
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| 222 | case IFETCH_QUEUE_STATE_ERROR_WAIT_RSP : (*_sum_use_queue_error_wait_rsp) ++; break; |
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| 223 | default : break; |
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| 224 | } |
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| 225 | #endif |
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| 226 | } |
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| 227 | |
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| 228 | log_end(Ifetch_queue,FUNCTION); |
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| 229 | }; |
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| 230 | |
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| 231 | }; // end namespace ifetch_queue |
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| 232 | }; // end namespace ifetch_unit |
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| 233 | }; // end namespace front_end |
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| 234 | }; // end namespace multi_front_end |
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| 235 | }; // end namespace core |
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| 236 | |
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| 237 | }; // end namespace behavioural |
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| 238 | }; // end namespace morpheo |
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| 239 | #endif |
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